From a411a12170f68d5864a26716f0f8d137f9683827 Mon Sep 17 00:00:00 2001 From: Aleksandar Markovic Date: Sat, 24 Feb 2018 20:45:05 -0500 Subject: [PATCH] target-mips: Add abs2008 flavor of . Updated handling of instructions .. Note that legacy (pre-abs2008) ABS and NEG instructions are arithmetic (and, therefore, any NaN operand causes signaling invalid operation), while abs2008 ones are non-arithmetic, always and only changing the sign bit, even for NaN-like operands. Details on these instructions are documented in [1] p. 35 and 359. Implementation-wise, abs2008 versions are implemented without helpers, for simplicity and performance sake. [1] "MIPS Architecture For Programmers Volume II-A: The MIPS64 Instruction Set Reference Manual", Imagination Technologies LTD, Revision 6.04, November 13, 2015 Backports commit 6be77480052b1a71557081896e7080363a8a2f95 from qemu --- qemu/target-mips/translate.c | 26 ++++++++++++++++++++++---- 1 file changed, 22 insertions(+), 4 deletions(-) diff --git a/qemu/target-mips/translate.c b/qemu/target-mips/translate.c index 0b670b19..9ad47b60 100644 --- a/qemu/target-mips/translate.c +++ b/qemu/target-mips/translate.c @@ -1420,6 +1420,7 @@ typedef struct DisasContext { bool vp; bool cmgcr; bool mrp; + bool abs2008; // Unicorn engine struct uc_struct *uc; } DisasContext; @@ -8960,7 +8961,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, TCGv_i32 fp0 = tcg_temp_new_i32(tcg_ctx); gen_load_fpr32(ctx, fp0, fs); - gen_helper_float_abs_s(tcg_ctx, fp0, fp0); + if (ctx->abs2008) { + tcg_gen_andi_i32(tcg_ctx, fp0, fp0, 0x7fffffffUL); + } else { + gen_helper_float_abs_s(tcg_ctx, fp0, fp0); + } gen_store_fpr32(ctx, fp0, fd); tcg_temp_free_i32(tcg_ctx, fp0); } @@ -8979,7 +8984,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, TCGv_i32 fp0 = tcg_temp_new_i32(tcg_ctx); gen_load_fpr32(ctx, fp0, fs); - gen_helper_float_chs_s(tcg_ctx, fp0, fp0); + if (ctx->abs2008) { + tcg_gen_xori_i32(tcg_ctx, fp0, fp0, 1UL << 31); + } else { + gen_helper_float_chs_s(tcg_ctx, fp0, fp0); + } gen_store_fpr32(ctx, fp0, fd); tcg_temp_free_i32(tcg_ctx, fp0); } @@ -9450,7 +9459,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, TCGv_i64 fp0 = tcg_temp_new_i64(tcg_ctx); gen_load_fpr64(ctx, fp0, fs); - gen_helper_float_abs_d(tcg_ctx, fp0, fp0); + if (ctx->abs2008) { + tcg_gen_andi_i64(tcg_ctx, fp0, fp0, 0x7fffffffffffffffULL); + } else { + gen_helper_float_abs_d(tcg_ctx, fp0, fp0); + } gen_store_fpr64(ctx, fp0, fd); tcg_temp_free_i64(tcg_ctx, fp0); } @@ -9471,7 +9484,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, TCGv_i64 fp0 = tcg_temp_new_i64(tcg_ctx); gen_load_fpr64(ctx, fp0, fs); - gen_helper_float_chs_d(tcg_ctx, fp0, fp0); + if (ctx->abs2008) { + tcg_gen_xori_i64(tcg_ctx, fp0, fp0, 1ULL << 63); + } else { + gen_helper_float_chs_d(tcg_ctx, fp0, fp0); + } gen_store_fpr64(ctx, fp0, fd); tcg_temp_free_i64(tcg_ctx, fp0); } @@ -19911,6 +19928,7 @@ void gen_intermediate_code(CPUMIPSState *env, struct TranslationBlock *tb) (env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F)); ctx.vp = (env->CP0_Config5 >> CP0C5_VP) & 1; ctx.mrp = (env->CP0_Config5 >> CP0C5_MRP) & 1; + ctx.abs2008 = (env->active_fpu.fcr31 >> FCR31_ABS2008) & 1; restore_cpu_state(env, &ctx); #ifdef CONFIG_USER_ONLY ctx.mem_idx = MIPS_HFLAG_UM;