From a6c323c91281a7fc557a837e9a49554b857b535c Mon Sep 17 00:00:00 2001 From: Alistair Francis Date: Thu, 25 Feb 2021 11:54:20 -0500 Subject: [PATCH] target/riscv: Set access as data_load when validating stage-2 PTEs Backports commit efe9f9c820d1322729957a60ff785c9527a79ddf from qemu --- qemu/target/riscv/cpu_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qemu/target/riscv/cpu_helper.c b/qemu/target/riscv/cpu_helper.c index 36d34121..59df5a8b 100644 --- a/qemu/target/riscv/cpu_helper.c +++ b/qemu/target/riscv/cpu_helper.c @@ -429,7 +429,7 @@ restart: hwaddr vbase; /* Do the second stage translation on the base PTE address. */ - get_physical_address(env, &vbase, &vbase_prot, base, access_type, + get_physical_address(env, &vbase, &vbase_prot, base, MMU_DATA_LOAD, mmu_idx, false, true); pte_addr = vbase + idx * ptesize;