From a79d4b6fe7ea69b7ea4c96f1235a540219bc78b6 Mon Sep 17 00:00:00 2001 From: Fredrik Noring Date: Fri, 23 Nov 2018 18:38:06 -0500 Subject: [PATCH] target/mips: Guard check_insn_opc_user_only with INSN_R5900 check Avoid using check_opc_user_only() as a decision making code wrt various architectures. Use ctx->insn_flags checks instead. Backports commit 55fc7a69aa38f5ec726e862caf4e4394caca04a8 from qemu --- qemu/target/mips/translate.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/qemu/target/mips/translate.c b/qemu/target/mips/translate.c index 6661b599..6cb2f881 100644 --- a/qemu/target/mips/translate.c +++ b/qemu/target/mips/translate.c @@ -28507,7 +28507,9 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx, bool *insn_need_pat break; case OPC_LL: /* Load and stores */ check_insn(ctx, ISA_MIPS2); - check_insn_opc_user_only(ctx, INSN_R5900); + if (ctx->insn_flags & INSN_R5900) { + check_insn_opc_user_only(ctx, INSN_R5900); + } /* Fallthrough */ case OPC_LWL: case OPC_LWR: @@ -28532,7 +28534,9 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx, bool *insn_need_pat case OPC_SC: check_insn(ctx, ISA_MIPS2); check_insn_opc_removed(ctx, ISA_MIPS32R6); - check_insn_opc_user_only(ctx, INSN_R5900); + if (ctx->insn_flags & INSN_R5900) { + check_insn_opc_user_only(ctx, INSN_R5900); + } gen_st_cond(ctx, op, rt, rs, imm); break; case OPC_CACHE: @@ -28800,7 +28804,9 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx, bool *insn_need_pat #if defined(TARGET_MIPS64) /* MIPS64 opcodes */ case OPC_LLD: - check_insn_opc_user_only(ctx, INSN_R5900); + if (ctx->insn_flags & INSN_R5900) { + check_insn_opc_user_only(ctx, INSN_R5900); + } /* fall through */ case OPC_LDL: case OPC_LDR: @@ -28824,7 +28830,9 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx, bool *insn_need_pat case OPC_SCD: check_insn_opc_removed(ctx, ISA_MIPS32R6); check_insn(ctx, ISA_MIPS3); - check_insn_opc_user_only(ctx, INSN_R5900); + if (ctx->insn_flags & INSN_R5900) { + check_insn_opc_user_only(ctx, INSN_R5900); + } check_mips_64(ctx); gen_st_cond(ctx, op, rt, rs, imm); break;