From a8fb6fc8d5f81c623ed9d8750355722c003844ff Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Tue, 18 Dec 2018 04:16:28 -0500 Subject: [PATCH] target/arm: Add SCR_EL3 bits up to ARMv8.5 Post v8.4 bits taken from SysReg_v85_xml-00bet8. Backports commit 99f8f86d365701fad695be606266aa7dac97ca1c from qemu --- qemu/target/arm/cpu.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/qemu/target/arm/cpu.h b/qemu/target/arm/cpu.h index 721df57c..b3e2914b 100644 --- a/qemu/target/arm/cpu.h +++ b/qemu/target/arm/cpu.h @@ -1246,6 +1246,16 @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) #define SCR_ST (1U << 11) #define SCR_TWI (1U << 12) #define SCR_TWE (1U << 13) +#define SCR_TLOR (1U << 14) +#define SCR_TERR (1U << 15) +#define SCR_APK (1U << 16) +#define SCR_API (1U << 17) +#define SCR_EEL2 (1U << 18) +#define SCR_EASE (1U << 19) +#define SCR_NMEA (1U << 20) +#define SCR_FIEN (1U << 21) +#define SCR_ENSCXT (1U << 25) +#define SCR_ATA (1U << 26) #define SCR_AARCH32_MASK (0x3fff & ~(SCR_RW | SCR_ST)) #define SCR_AARCH64_MASK (0x3fff & ~SCR_NET)