From aca20201d4f06b43141ac32ef343a553e25f289e Mon Sep 17 00:00:00 2001 From: Alistair Francis Date: Tue, 28 May 2019 19:18:58 -0400 Subject: [PATCH] target/riscv: Add the HGATP register masks Backports commit e06431108b0b1ef6ca76398d2b0b792ea24ae6bc from qemu --- qemu/target/riscv/cpu_bits.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/qemu/target/riscv/cpu_bits.h b/qemu/target/riscv/cpu_bits.h index d18f9464..ca1d3c61 100644 --- a/qemu/target/riscv/cpu_bits.h +++ b/qemu/target/riscv/cpu_bits.h @@ -208,6 +208,17 @@ #define CSR_HIDELEG 0xa03 #define CSR_HGATP 0xa80 +#if defined(TARGET_RISCV32) +#define HGATP_MODE SATP32_MODE +#define HGATP_ASID SATP32_ASID +#define HGATP_PPN SATP32_PPN +#endif +#if defined(TARGET_RISCV64) +#define HGATP_MODE SATP64_MODE +#define HGATP_ASID SATP64_ASID +#define HGATP_PPN SATP64_PPN +#endif + /* Performance Counters */ #define CSR_MHPMCOUNTER3 0xb03 #define CSR_MHPMCOUNTER4 0xb04