From af0e6e9be3f56bfb500ef2f7209c887ab8ec5557 Mon Sep 17 00:00:00 2001
From: Yongbok Kim <yongbok.kim@imgtec.com>
Date: Tue, 13 Feb 2018 20:47:20 -0500
Subject: [PATCH] target-mips: fix {RD, WR}PGPR in microMIPS

rt, rs were swapped

Backports commit 1bf5902de03732d4067c4e90171a1741d6542c45 from qemu
---
 qemu/target-mips/translate.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/qemu/target-mips/translate.c b/qemu/target-mips/translate.c
index 53b70722..786949e6 100644
--- a/qemu/target-mips/translate.c
+++ b/qemu/target-mips/translate.c
@@ -13091,12 +13091,12 @@ static void gen_pool32axf (CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
         case RDPGPR:
             check_cp0_enabled(ctx);
             check_insn(ctx, ISA_MIPS32R2);
-            gen_load_srsgpr(ctx, rt, rs);
+            gen_load_srsgpr(ctx, rs, rt);
             break;
         case WRPGPR:
             check_cp0_enabled(ctx);
             check_insn(ctx, ISA_MIPS32R2);
-            gen_store_srsgpr(ctx, rt, rs);
+            gen_store_srsgpr(ctx, rs, rt);
             break;
         default:
             goto pool32axf_invalid;