diff --git a/qemu/target-arm/translate-a64.c b/qemu/target-arm/translate-a64.c
index ef412584..26f12bf0 100644
--- a/qemu/target-arm/translate-a64.c
+++ b/qemu/target-arm/translate-a64.c
@@ -11285,6 +11285,9 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu,
     if (max_insns == 0) {
         max_insns = CF_COUNT_MASK;
     }
+    if (max_insns > TCG_MAX_INSNS) {
+        max_insns = TCG_MAX_INSNS;
+    }
 
     tcg_clear_temp_count();
 
diff --git a/qemu/target-arm/translate.c b/qemu/target-arm/translate.c
index b12fc806..7692d804 100644
--- a/qemu/target-arm/translate.c
+++ b/qemu/target-arm/translate.c
@@ -11433,8 +11433,12 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu,
     lj = -1;
     num_insns = 0;
     max_insns = tb->cflags & CF_COUNT_MASK;
-    if (max_insns == 0)
+    if (max_insns == 0) {
         max_insns = CF_COUNT_MASK;
+    }
+    if (max_insns > TCG_MAX_INSNS) {
+        max_insns = TCG_MAX_INSNS;
+    }
 
     tcg_clear_temp_count();
 
diff --git a/qemu/target-i386/translate.c b/qemu/target-i386/translate.c
index 255bbc84..74981a70 100644
--- a/qemu/target-i386/translate.c
+++ b/qemu/target-i386/translate.c
@@ -8665,8 +8665,12 @@ static inline void gen_intermediate_code_internal(uint8_t *gen_opc_cc_op,
     dc->is_jmp = DISAS_NEXT;
     lj = -1;
     max_insns = tb->cflags & CF_COUNT_MASK;
-    if (max_insns == 0)
+    if (max_insns == 0) {
         max_insns = CF_COUNT_MASK;
+    }
+    if (max_insns > TCG_MAX_INSNS) {
+        max_insns = TCG_MAX_INSNS;
+    }
 
     // Unicorn: trace this block on request
     // Only hook this block if the previous block was not truncated due to space
diff --git a/qemu/target-m68k/translate.c b/qemu/target-m68k/translate.c
index 7be115a0..1a93e40b 100644
--- a/qemu/target-m68k/translate.c
+++ b/qemu/target-m68k/translate.c
@@ -3087,8 +3087,12 @@ gen_intermediate_code_internal(M68kCPU *cpu, TranslationBlock *tb,
     lj = -1;
     num_insns = 0;
     max_insns = tb->cflags & CF_COUNT_MASK;
-    if (max_insns == 0)
+    if (max_insns == 0) {
         max_insns = CF_COUNT_MASK;
+    }
+    if (max_insns > TCG_MAX_INSNS) {
+        max_insns = TCG_MAX_INSNS;
+    }
 
     // Unicorn: early check to see if the address of this block is the until address
     if (tb->pc == env->uc->addr_end) {
diff --git a/qemu/target-mips/translate.c b/qemu/target-mips/translate.c
index f9ce6132..40823339 100644
--- a/qemu/target-mips/translate.c
+++ b/qemu/target-mips/translate.c
@@ -19744,8 +19744,12 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb,
 
     num_insns = 0;
     max_insns = tb->cflags & CF_COUNT_MASK;
-    if (max_insns == 0)
+    if (max_insns == 0) {
         max_insns = CF_COUNT_MASK;
+    }
+    if (max_insns > TCG_MAX_INSNS) {
+        max_insns = TCG_MAX_INSNS;
+    }
     LOG_DISAS("\ntb %p idx %d hflags %04x\n", tb, ctx.mem_idx, ctx.hflags);
 
     // Unicorn: early check to see if the address of this block is the until address
diff --git a/qemu/target-sparc/translate.c b/qemu/target-sparc/translate.c
index 752cd942..2835b432 100644
--- a/qemu/target-sparc/translate.c
+++ b/qemu/target-sparc/translate.c
@@ -5396,8 +5396,12 @@ static inline void gen_intermediate_code_internal(SPARCCPU *cpu,
     }
 
     max_insns = tb->cflags & CF_COUNT_MASK;
-    if (max_insns == 0)
+    if (max_insns == 0) {
         max_insns = CF_COUNT_MASK;
+    }
+    if (max_insns > TCG_MAX_INSNS) {
+        max_insns = TCG_MAX_INSNS;
+    }
 
     // Unicorn: early check to see if the address of this block is the until address
     if (tb->pc == env->uc->addr_end) {
diff --git a/qemu/tcg/tcg.h b/qemu/tcg/tcg.h
index a57ca85c..92966b2f 100644
--- a/qemu/tcg/tcg.h
+++ b/qemu/tcg/tcg.h
@@ -197,6 +197,7 @@ typedef struct TCGPool {
 #define TCG_POOL_CHUNK_SIZE 32768
 
 #define TCG_MAX_TEMPS 512
+#define TCG_MAX_INSNS 512
 
 /* when the size of the arguments of a called function is smaller than
    this value, they are statically allocated in the TB stack frame */