From b14793a9338b2d5eff363d30d63af30f71e3878e Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Tue, 3 Jul 2018 03:52:34 -0400 Subject: [PATCH] target/arm: Implement SVE floating-point trig multiply-add coefficient Backports commit 67fcd9ad35d2b38630ee34e8ced8878d334c74fb from qemu --- qemu/aarch64.h | 3 ++ qemu/aarch64eb.h | 3 ++ qemu/header_gen.py | 3 ++ qemu/target/arm/helper-sve.h | 4 ++ qemu/target/arm/sve.decode | 3 ++ qemu/target/arm/sve_helper.c | 70 +++++++++++++++++++++++++++++++++ qemu/target/arm/translate-sve.c | 28 +++++++++++++ 7 files changed, 114 insertions(+) diff --git a/qemu/aarch64.h b/qemu/aarch64.h index 0ad79296..693a8810 100644 --- a/qemu/aarch64.h +++ b/qemu/aarch64.h @@ -3642,6 +3642,9 @@ #define helper_sve_fsubs_d helper_sve_fsubs_d_aarch64 #define helper_sve_fsubs_h helper_sve_fsubs_h_aarch64 #define helper_sve_fsubs_s helper_sve_fsubs_s_aarch64 +#define helper_sve_ftmad_d helper_sve_ftmad_d_aarch64 +#define helper_sve_ftmad_h helper_sve_ftmad_h_aarch64 +#define helper_sve_ftmad_s helper_sve_ftmad_s_aarch64 #define helper_sve_ftssel_d helper_sve_ftssel_d_aarch64 #define helper_sve_ftssel_h helper_sve_ftssel_h_aarch64 #define helper_sve_ftssel_s helper_sve_ftssel_s_aarch64 diff --git a/qemu/aarch64eb.h b/qemu/aarch64eb.h index a6c60d9f..4c78fa99 100644 --- a/qemu/aarch64eb.h +++ b/qemu/aarch64eb.h @@ -3642,6 +3642,9 @@ #define helper_sve_fsubs_d helper_sve_fsubs_d_aarch64eb #define helper_sve_fsubs_h helper_sve_fsubs_h_aarch64eb #define helper_sve_fsubs_s helper_sve_fsubs_s_aarch64eb +#define helper_sve_ftmad_d helper_sve_ftmad_d_aarch64eb +#define helper_sve_ftmad_h helper_sve_ftmad_h_aarch64eb +#define helper_sve_ftmad_s helper_sve_ftmad_s_aarch64eb #define helper_sve_ftssel_d helper_sve_ftssel_d_aarch64eb #define helper_sve_ftssel_h helper_sve_ftssel_h_aarch64eb #define helper_sve_ftssel_s helper_sve_ftssel_s_aarch64eb diff --git a/qemu/header_gen.py b/qemu/header_gen.py index 0f1c2faa..618265dc 100644 --- a/qemu/header_gen.py +++ b/qemu/header_gen.py @@ -3663,6 +3663,9 @@ aarch64_symbols = ( 'helper_sve_fsubs_d', 'helper_sve_fsubs_h', 'helper_sve_fsubs_s', + 'helper_sve_ftmad_d', + 'helper_sve_ftmad_h', + 'helper_sve_ftmad_s', 'helper_sve_ftssel_d', 'helper_sve_ftssel_h', 'helper_sve_ftssel_s', diff --git a/qemu/target/arm/helper-sve.h b/qemu/target/arm/helper-sve.h index 44a98440..aca137fc 100644 --- a/qemu/target/arm/helper-sve.h +++ b/qemu/target/arm/helper-sve.h @@ -1037,6 +1037,10 @@ DEF_HELPER_FLAGS_3(sve_fnmls_zpzzz_h, TCG_CALL_NO_RWG, void, env, ptr, i32) DEF_HELPER_FLAGS_3(sve_fnmls_zpzzz_s, TCG_CALL_NO_RWG, void, env, ptr, i32) DEF_HELPER_FLAGS_3(sve_fnmls_zpzzz_d, TCG_CALL_NO_RWG, void, env, ptr, i32) +DEF_HELPER_FLAGS_5(sve_ftmad_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_ftmad_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_ftmad_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) + DEF_HELPER_FLAGS_4(sve_ld1bb_r, TCG_CALL_NO_WG, void, env, ptr, tl, i32) DEF_HELPER_FLAGS_4(sve_ld2bb_r, TCG_CALL_NO_WG, void, env, ptr, tl, i32) DEF_HELPER_FLAGS_4(sve_ld3bb_r, TCG_CALL_NO_WG, void, env, ptr, tl, i32) diff --git a/qemu/target/arm/sve.decode b/qemu/target/arm/sve.decode index 669225f4..b124f875 100644 --- a/qemu/target/arm/sve.decode +++ b/qemu/target/arm/sve.decode @@ -800,6 +800,9 @@ FMULX 01100101 .. 00 1010 100 ... ..... ..... @rdn_pg_rm FDIV 01100101 .. 00 1100 100 ... ..... ..... @rdm_pg_rn # FDIVR FDIV 01100101 .. 00 1101 100 ... ..... ..... @rdn_pg_rm +# SVE floating-point trig multiply-add coefficient +FTMAD 01100101 esz:2 010 imm:3 100000 rm:5 rd:5 rn=%reg_movprfx + ### SVE FP Multiply-Add Group # SVE floating-point multiply-accumulate writing addend diff --git a/qemu/target/arm/sve_helper.c b/qemu/target/arm/sve_helper.c index dd36aeb8..3eb442be 100644 --- a/qemu/target/arm/sve_helper.c +++ b/qemu/target/arm/sve_helper.c @@ -3114,6 +3114,76 @@ DO_FPCMP_PPZ0_ALL(sve_fcmlt0, DO_FCMLT) DO_FPCMP_PPZ0_ALL(sve_fcmeq0, DO_FCMEQ) DO_FPCMP_PPZ0_ALL(sve_fcmne0, DO_FCMNE) +/* FP Trig Multiply-Add. */ + +void HELPER(sve_ftmad_h)(void *vd, void *vn, void *vm, void *vs, uint32_t desc) +{ + static const float16 coeff[16] = { + 0x3c00, 0xb155, 0x2030, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x3c00, 0xb800, 0x293a, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + }; + intptr_t i, opr_sz = simd_oprsz(desc) / sizeof(float16); + intptr_t x = simd_data(desc); + float16 *d = vd, *n = vn, *m = vm; + for (i = 0; i < opr_sz; i++) { + float16 mm = m[i]; + intptr_t xx = x; + if (float16_is_neg(mm)) { + mm = float16_abs(mm); + xx += 8; + } + d[i] = float16_muladd(n[i], mm, coeff[xx], 0, vs); + } +} + +void HELPER(sve_ftmad_s)(void *vd, void *vn, void *vm, void *vs, uint32_t desc) +{ + static const float32 coeff[16] = { + 0x3f800000, 0xbe2aaaab, 0x3c088886, 0xb95008b9, + 0x36369d6d, 0x00000000, 0x00000000, 0x00000000, + 0x3f800000, 0xbf000000, 0x3d2aaaa6, 0xbab60705, + 0x37cd37cc, 0x00000000, 0x00000000, 0x00000000, + }; + intptr_t i, opr_sz = simd_oprsz(desc) / sizeof(float32); + intptr_t x = simd_data(desc); + float32 *d = vd, *n = vn, *m = vm; + for (i = 0; i < opr_sz; i++) { + float32 mm = m[i]; + intptr_t xx = x; + if (float32_is_neg(mm)) { + mm = float32_abs(mm); + xx += 8; + } + d[i] = float32_muladd(n[i], mm, coeff[xx], 0, vs); + } +} + +void HELPER(sve_ftmad_d)(void *vd, void *vn, void *vm, void *vs, uint32_t desc) +{ + static const float64 coeff[16] = { + 0x3ff0000000000000ull, 0xbfc5555555555543ull, + 0x3f8111111110f30cull, 0xbf2a01a019b92fc6ull, + 0x3ec71de351f3d22bull, 0xbe5ae5e2b60f7b91ull, + 0x3de5d8408868552full, 0x0000000000000000ull, + 0x3ff0000000000000ull, 0xbfe0000000000000ull, + 0x3fa5555555555536ull, 0xbf56c16c16c13a0bull, + 0x3efa01a019b1e8d8ull, 0xbe927e4f7282f468ull, + 0x3e21ee96d2641b13ull, 0xbda8f76380fbb401ull, + }; + intptr_t i, opr_sz = simd_oprsz(desc) / sizeof(float64); + intptr_t x = simd_data(desc); + float64 *d = vd, *n = vn, *m = vm; + for (i = 0; i < opr_sz; i++) { + float64 mm = m[i]; + intptr_t xx = x; + if (float64_is_neg(mm)) { + mm = float64_abs(mm); + xx += 8; + } + d[i] = float64_muladd(n[i], mm, coeff[xx], 0, vs); + } +} + /* * Load contiguous data, protected by a governing predicate. */ diff --git a/qemu/target/arm/translate-sve.c b/qemu/target/arm/translate-sve.c index 14f14706..393f9688 100644 --- a/qemu/target/arm/translate-sve.c +++ b/qemu/target/arm/translate-sve.c @@ -3745,6 +3745,34 @@ DO_PPZ(FCMNE_ppz0, fcmne0) #undef DO_PPZ +/* + *** SVE floating-point trig multiply-add coefficient + */ + +static bool trans_FTMAD(DisasContext *s, arg_FTMAD *a, uint32_t insn) +{ + static gen_helper_gvec_3_ptr * const fns[3] = { + gen_helper_sve_ftmad_h, + gen_helper_sve_ftmad_s, + gen_helper_sve_ftmad_d, + }; + + if (a->esz == 0) { + return false; + } + if (sve_access_check(s)) { + TCGContext *tcg_ctx = s->uc->tcg_ctx; + unsigned vsz = vec_full_reg_size(s); + TCGv_ptr status = get_fpstatus_ptr(tcg_ctx, a->esz == MO_16); + tcg_gen_gvec_3_ptr(tcg_ctx, vec_full_reg_offset(s, a->rd), + vec_full_reg_offset(s, a->rn), + vec_full_reg_offset(s, a->rm), + status, vsz, vsz, a->imm, fns[a->esz - 1]); + tcg_temp_free_ptr(tcg_ctx, status); + } + return true; +} + /* *** SVE Floating Point Accumulating Reduction Group */