From b23e78677932b7420c6131c288f57e0ac2ec9ed2 Mon Sep 17 00:00:00 2001 From: Alistair Francis Date: Mon, 8 Mar 2021 15:20:39 -0500 Subject: [PATCH] riscv: spike: Remove target macro conditionals Backports dc4d4aaee31cd3ac4020d3b15729f0a104ce8862 --- qemu/include/hw/riscv/spike.h | 8 -------- 1 file changed, 8 deletions(-) diff --git a/qemu/include/hw/riscv/spike.h b/qemu/include/hw/riscv/spike.h index b3f76330..d439b6f5 100644 --- a/qemu/include/hw/riscv/spike.h +++ b/qemu/include/hw/riscv/spike.h @@ -1,14 +1,6 @@ #ifndef HW_RISCV_SPIKE_H #define HW_RISCV_SPIKE_H -#if defined(TARGET_RISCV32) -#define SPIKE_V1_09_1_CPU TYPE_RISCV_CPU_RV32GCSU_V1_09_1 -#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_RV32GCSU_V1_10_0 -#elif defined(TARGET_RISCV64) -#define SPIKE_V1_09_1_CPU TYPE_RISCV_CPU_RV64GCSU_V1_09_1 -#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_RV64GCSU_V1_10_0 -#endif - void spike_v1_10_0_machine_init_register_types(struct uc_struct *uc); #endif /* HW_RISCV_SPIKE_H */