From b35fb57c84a37e585b8204ee9de68c08d5c05a6a Mon Sep 17 00:00:00 2001 From: James Hogan Date: Sun, 4 Mar 2018 01:09:41 -0500 Subject: [PATCH] target/mips: Enable CP0_EBase.WG on MIPS64 CPUs Enable the CP0_EBase.WG (write gate) on the I6400 and MIPS64R2-generic CPUs. This allows 64-bit guests to run KVM itself, which uses CP0_EBase.WG to point CP0_EBase at XKPhys. Backports commit bad63a8008a0aaefcd00542c89bee01623d7c9de from qemu --- qemu/target/mips/translate_init.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qemu/target/mips/translate_init.c b/qemu/target/mips/translate_init.c index b44db3d7..c0628f8a 100644 --- a/qemu/target/mips/translate_init.c +++ b/qemu/target/mips/translate_init.c @@ -871,7 +871,7 @@ static const mips_def_t mips_defs[] = 42, 36, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, - 0, + (1 << CP0EBase_WG), CPU_MIPS64R2 | ASE_MIPS3D, MMU_TYPE_R4000, }, @@ -916,7 +916,7 @@ static const mips_def_t mips_defs[] = (1 << CP0PG_ELPA), (1 << CP0PG_IEC) | (1 << CP0PG_XIE) | (1U << CP0PG_RIE), - 0, + (1 << CP0EBase_WG), CPU_MIPS64R6 | ASE_MSA, MMU_TYPE_R4000, },