From b3fccc4841463ccfd4850526a75d8ac5d9c24c3c Mon Sep 17 00:00:00 2001 From: Robert Hoo Date: Fri, 17 Aug 2018 14:26:02 -0400 Subject: [PATCH] i386: Add new MSR indices for IA32_PRED_CMD and IA32_ARCH_CAPABILITIES IA32_PRED_CMD MSR gives software a way to issue commands that affect the state of indirect branch predictors. Enumerated by CPUID.(EAX=7H,ECX=0):EDX[26]. IA32_ARCH_CAPABILITIES MSR enumerates architectural features of RDCL_NO and IBRS_ALL. Enumerated by CPUID.(EAX=07H, ECX=0):EDX[29]. https://software.intel.com/sites/default/files/managed/c5/63/336996-Speculative-Execution-Side-Channel-Mitigations.pdf Backports commit 8c80c99fcceabd0708a5a83f08577e778c9419f5 from qemu --- qemu/target/i386/cpu.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qemu/target/i386/cpu.h b/qemu/target/i386/cpu.h index 82e5efa5..9cd6bcfa 100644 --- a/qemu/target/i386/cpu.h +++ b/qemu/target/i386/cpu.h @@ -332,6 +332,8 @@ #define MSR_TSC_ADJUST 0x0000003b #define MSR_IA32_SPEC_CTRL 0x48 #define MSR_VIRT_SSBD 0xc001011f +#define MSR_IA32_PRED_CMD 0x49 +#define MSR_IA32_ARCH_CAPABILITIES 0x10a #define MSR_IA32_TSCDEADLINE 0x6e0 #define FEATURE_CONTROL_LOCKED (1<<0)