From b6b0c18ce5d3f107006bd874fdcc85633ff72cf9 Mon Sep 17 00:00:00 2001 From: Aaron Lindsay Date: Tue, 22 Jan 2019 17:01:32 -0500 Subject: [PATCH] target/arm: Swap PMU values before/after migrations Because of the PMU's design, many register accesses have side effects which are inter-related, meaning that the normal method of saving CP registers can result in inconsistent state. These side-effects are largely handled in pmu_op_start/finish functions which can be called before and after the state is saved/restored. By doing this and adding raw read/write functions for the affected registers, we avoid migration-related inconsistencies. Backports relevant parts of commit 980ebe87053792a5bdefaa87777c40914fd4f673 from qemu --- qemu/target/arm/helper.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/qemu/target/arm/helper.c b/qemu/target/arm/helper.c index e78671b3..b5cf93eb 100644 --- a/qemu/target/arm/helper.c +++ b/qemu/target/arm/helper.c @@ -1299,12 +1299,12 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { ARM_CP_ALIAS | ARM_CP_IO, PL0_RW, 0, NULL, 0, 0, {0, 0}, pmreg_access_ccntr, pmccntr_read, pmccntr_write32, }, { "PMCCNTR_EL0", 0,9,13, 3,3,0, ARM_CP_STATE_AA64, - ARM_CP_IO, PL0_RW, 0, NULL, 0, 0, {0, 0}, - pmreg_access_ccntr, pmccntr_read, pmccntr_write, }, + ARM_CP_IO, PL0_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c15_ccnt), {0, 0}, + pmreg_access_ccntr, pmccntr_read, pmccntr_write, raw_read, raw_write }, #endif { "PMCCFILTR_EL0", 0,14,15, 3,3,7, ARM_CP_STATE_AA64, ARM_CP_IO, PL0_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.pmccfiltr_el0), {0, 0}, - pmreg_access, NULL, pmccfiltr_write, }, + pmreg_access, NULL, pmccfiltr_write, NULL, raw_write }, { "PMXEVTYPER", 15,9,13, 0,0,1, 0, ARM_CP_NO_RAW, PL0_RW, 0, NULL, 0, 0, {0, 0}, pmreg_access, pmxevtyper_read, pmxevtyper_write },