From b6db70808df22937055a24b265d558327c595782 Mon Sep 17 00:00:00 2001 From: Ryan Hileman Date: Sun, 10 Jan 2016 23:51:11 -0800 Subject: [PATCH] add regress for #366 --- tests/regress/arm_vldr_invalid.py | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100755 tests/regress/arm_vldr_invalid.py diff --git a/tests/regress/arm_vldr_invalid.py b/tests/regress/arm_vldr_invalid.py new file mode 100755 index 00000000..febf93e7 --- /dev/null +++ b/tests/regress/arm_vldr_invalid.py @@ -0,0 +1,18 @@ +#!/usr/bin/python + +from unicorn import * +from unicorn.arm_const import * + +import regress + +class VldrPcInsn(regress.RegressTest): + + def runTest(self): + uc = Uc(UC_ARCH_ARM, UC_MODE_ARM) + uc.mem_map(0x1000, 0x1000) + uc.mem_write(0x1000, 'ed9f8a3d'.decode('hex')) # vldr s16, [pc, #244] + # this will raise invalid insn + uc.emu_start(0x1000, 0x1004) + +if __name__ == '__main__': + regress.main()