From b711147cc39098592cf123844109ecf3171f3899 Mon Sep 17 00:00:00 2001 From: Greg Bellows Date: Mon, 12 Feb 2018 10:02:48 -0500 Subject: [PATCH] target-arm: make MAIR0/1 banked Added CP register info entries for the ARMv7 MAIR0/1 secure banks. Backports commit be693c87e440e671ed913784554384349ce8331d from qemu --- qemu/target-arm/cpu.h | 21 ++++++++++++++++++++- qemu/target-arm/helper.c | 12 +++++++++--- 2 files changed, 29 insertions(+), 4 deletions(-) diff --git a/qemu/target-arm/cpu.h b/qemu/target-arm/cpu.h index 75b093d7..bf41cff1 100644 --- a/qemu/target-arm/cpu.h +++ b/qemu/target-arm/cpu.h @@ -298,7 +298,26 @@ typedef struct CPUARMState { uint32_t c9_pmxevtyper; /* perf monitor event type */ uint32_t c9_pmuserenr; /* perf monitor user enable */ uint32_t c9_pminten; /* perf monitor interrupt enables */ - uint64_t mair_el1; + union { /* Memory attribute redirection */ + struct { +#ifdef HOST_WORDS_BIGENDIAN + uint64_t _unused_mair_0; + uint32_t mair1_ns; + uint32_t mair0_ns; + uint64_t _unused_mair_1; + uint32_t mair1_s; + uint32_t mair0_s; +#else + uint64_t _unused_mair_0; + uint32_t mair0_ns; + uint32_t mair1_ns; + uint64_t _unused_mair_1; + uint32_t mair0_s; + uint32_t mair1_s; +#endif + }; + uint64_t mair_el[4]; + }; union { /* vector base address register */ struct { uint64_t _unused_vbar; diff --git a/qemu/target-arm/helper.c b/qemu/target-arm/helper.c index cecfe1e1..2fd2349c 100644 --- a/qemu/target-arm/helper.c +++ b/qemu/target-arm/helper.c @@ -808,17 +808,23 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { * and so don't need to care about memory attributes. */ { "MAIR_EL1", 0,10,2, 3,0,0, ARM_CP_STATE_AA64, - 0, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.mair_el1), }, + 0, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.mair_el[1]), }, /* For non-long-descriptor page tables these are PRRR and NMRR; * regardless they still act as reads-as-written for QEMU. * The override is necessary because of the overly-broad TLB_LOCKDOWN * definition. */ + /* MAIR0/1 are defined separately from their 64-bit counterpart which + * allows them to assign the correct fieldoffset based on the endianness + * handled in the field definitions. + */ { "MAIR0", 15,10,2, 0,0,0, ARM_CP_STATE_AA32, - ARM_CP_OVERRIDE, PL1_RW, 0, NULL, 0, offsetoflow32(CPUARMState, cp15.mair_el1), {0, 0}, + ARM_CP_OVERRIDE, PL1_RW, 0, NULL, 0, 0, + { offsetof(CPUARMState, cp15.mair0_s), offsetof(CPUARMState, cp15.mair0_ns) }, NULL, NULL, NULL, NULL, NULL, arm_cp_reset_ignore }, { "MAIR1", 15,10,2, 0,0,1, ARM_CP_STATE_AA32, - ARM_CP_OVERRIDE, PL1_RW, 0, NULL, 0, offsetofhigh32(CPUARMState, cp15.mair_el1), {0, 0}, + ARM_CP_OVERRIDE, PL1_RW, 0, NULL, 0, 0, + { offsetof(CPUARMState, cp15.mair1_s), offsetof(CPUARMState, cp15.mair1_ns) }, NULL, NULL, NULL, NULL, NULL, arm_cp_reset_ignore }, { "ISR_EL1", 0,12,1, 3,0,0, ARM_CP_STATE_BOTH, ARM_CP_NO_MIGRATE, PL1_R, 0, NULL, 0, 0, {0, 0},