From b82fe8b95c4566c113391a6e4497dcd229aafd83 Mon Sep 17 00:00:00 2001 From: Laurent Vivier Date: Tue, 6 Mar 2018 08:25:59 -0500 Subject: [PATCH] target/m68k: add reset The instruction traps if the CPU is not in Supervisor state but the helper is empty because there is no easy way to reset all the peripherals without resetting the CPU itself. Backports commit 0bdb2b3bf5660f892ddbfa09baea56cdca57ad1d from qemu --- qemu/target/m68k/helper.c | 7 +++++++ qemu/target/m68k/helper.h | 4 ++++ qemu/target/m68k/translate.c | 15 +++++++++++++++ 3 files changed, 26 insertions(+) diff --git a/qemu/target/m68k/helper.c b/qemu/target/m68k/helper.c index 6ef93ad7..0219fe2c 100644 --- a/qemu/target/m68k/helper.c +++ b/qemu/target/m68k/helper.c @@ -586,3 +586,10 @@ void HELPER(set_mac_extu)(CPUM68KState *env, uint32_t val, uint32_t acc) res |= (uint64_t)(val & 0xffff0000) << 16; env->macc[acc + 1] = res; } + +#if defined(CONFIG_SOFTMMU) +void HELPER(reset)(CPUM68KState *env) +{ + /* FIXME: reset all except CPU */ +} +#endif diff --git a/qemu/target/m68k/helper.h b/qemu/target/m68k/helper.h index 61b773bf..dc49e1e6 100644 --- a/qemu/target/m68k/helper.h +++ b/qemu/target/m68k/helper.h @@ -98,3 +98,7 @@ DEF_HELPER_FLAGS_4(bfffo_mem, TCG_CALL_NO_WG, i64, env, i32, s32, i32) DEF_HELPER_3(chk, void, env, s32, s32) DEF_HELPER_4(chk2, void, env, s32, s32, s32) + +#if defined(CONFIG_SOFTMMU) +DEF_HELPER_FLAGS_1(reset, TCG_CALL_NO_RWG, void, env) +#endif diff --git a/qemu/target/m68k/translate.c b/qemu/target/m68k/translate.c index 3dee2abf..fce09c40 100644 --- a/qemu/target/m68k/translate.c +++ b/qemu/target/m68k/translate.c @@ -2848,6 +2848,20 @@ DISAS_INSN(unlk) tcg_temp_free(tcg_ctx, src); } +#if defined(CONFIG_SOFTMMU) +DISAS_INSN(reset) +{ + TCGContext *tcg_ctx = s->uc->tcg_ctx; + + if (IS_USER(s)) { + gen_exception(s, s->insn_pc, EXCP_PRIVILEGE); + return; + } + + gen_helper_reset(tcg_ctx, tcg_ctx->cpu_env); +} +#endif + DISAS_INSN(nop) { } @@ -5779,6 +5793,7 @@ void register_m68k_insns (CPUM68KState *env) #if defined(CONFIG_SOFTMMU) INSN(move_to_usp, 4e60, fff8, USP); INSN(move_from_usp, 4e68, fff8, USP); + INSN(reset, 4e70, ffff, M68000); BASE(stop, 4e72, ffff); BASE(rte, 4e73, ffff); INSN(movec, 4e7b, ffff, CF_ISA_A);