diff --git a/qemu/exec.c b/qemu/exec.c
index c1d5279b..b2bf3d8d 100644
--- a/qemu/exec.c
+++ b/qemu/exec.c
@@ -640,11 +640,13 @@ void cpu_exec_init(CPUState *cpu, Error **errp, void *opaque)
     // Unicorn: Required to clean-slate TLB state
     tlb_flush(cpu);
 
+#ifdef CONFIG_TCG
     if (tcg_enabled(uc) && !cc->tcg_initialized) {
         cc->tcg_initialized = true;
-        cc->tcg_initialize(uc);
+        cc->tcg_ops.initialize(uc);
     }
     tlb_init(cpu);
+#endif /* CONFIG_TCG */
 
 #ifndef CONFIG_USER_ONLY
 
diff --git a/qemu/include/qom/cpu.h b/qemu/include/qom/cpu.h
index 9b0229cb..7998ff37 100644
--- a/qemu/include/qom/cpu.h
+++ b/qemu/include/qom/cpu.h
@@ -74,6 +74,19 @@ typedef void (*CPUUnassignedAccess)(CPUState *cpu, hwaddr addr,
 
 struct TranslationBlock;
 
+/**
+ * struct TcgCpuOperations: TCG operations specific to a CPU class
+ */
+typedef struct TcgCpuOperations {
+    /**
+     * @initialize: Initalize TCG state
+     *
+     * Called when the first CPU is realized.
+     */
+    void (*initialize)(struct uc_struct *uc);
+
+} TcgCpuOperations;
+
 /**
  * CPUClass:
  * @class_by_name: Callback to map -cpu command line model name to an
@@ -183,9 +196,9 @@ typedef struct CPUClass {
     void (*cpu_exec_exit)(CPUState *cpu);
     bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request);
     vaddr (*adjust_watchpoint_address)(CPUState *cpu, vaddr addr, int len);
-    void (*tcg_initialize)(struct uc_struct *uc);
 
     /* Keep non-pointer data at the end to minimize holes.  */
+    TcgCpuOperations tcg_ops;
     bool tcg_initialized;
 } CPUClass;
 
diff --git a/qemu/target/arm/cpu.c b/qemu/target/arm/cpu.c
index cc7457c6..fcb6862d 100644
--- a/qemu/target/arm/cpu.c
+++ b/qemu/target/arm/cpu.c
@@ -2108,7 +2108,7 @@ static void arm_cpu_class_init(struct uc_struct *uc, ObjectClass *oc, void *data
     //cc->virtio_is_big_endian = arm_cpu_is_big_endian;
 #endif
 #ifdef CONFIG_TCG
-    cc->tcg_initialize = arm_translate_init;
+    cc->tcg_ops.initialize = arm_translate_init;
     cc->tlb_fill = arm_cpu_tlb_fill;
     cc->debug_excp_handler = arm_debug_excp_handler;
     cc->debug_check_watchpoint = arm_debug_check_watchpoint;
diff --git a/qemu/target/i386/cpu.c b/qemu/target/i386/cpu.c
index 51da6a0c..dbbb04e0 100644
--- a/qemu/target/i386/cpu.c
+++ b/qemu/target/i386/cpu.c
@@ -5893,7 +5893,7 @@ static void x86_cpu_common_class_init(struct uc_struct *uc, ObjectClass *oc, voi
     cc->cpu_exec_enter = x86_cpu_exec_enter;
     cc->cpu_exec_exit = x86_cpu_exec_exit;
 #ifdef CONFIG_TCG
-    cc->tcg_initialize = tcg_x86_init;
+    cc->tcg_ops.initialize = tcg_x86_init;
     cc->tlb_fill = x86_cpu_tlb_fill;
 #endif
 }
diff --git a/qemu/target/m68k/cpu.c b/qemu/target/m68k/cpu.c
index 6993cb5a..6141bd7c 100644
--- a/qemu/target/m68k/cpu.c
+++ b/qemu/target/m68k/cpu.c
@@ -273,7 +273,7 @@ static void m68k_cpu_class_init(struct uc_struct *uc, ObjectClass *c, void *data
     cc->do_transaction_failed = m68k_cpu_transaction_failed;
     cc->get_phys_page_debug = m68k_cpu_get_phys_page_debug;
 #endif
-    cc->tcg_initialize = m68k_tcg_init;
+    cc->tcg_ops.initialize = m68k_tcg_init;
 }
 
 #define DEFINE_M68K_CPU_TYPE(cpu_model, initfn) \
diff --git a/qemu/target/mips/cpu.c b/qemu/target/mips/cpu.c
index 2cfcbaa3..6dcb5e2a 100644
--- a/qemu/target/mips/cpu.c
+++ b/qemu/target/mips/cpu.c
@@ -181,7 +181,7 @@ static void mips_cpu_class_init(struct uc_struct *uc, ObjectClass *c, void *data
     cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
 #endif
 #ifdef CONFIG_TCG
-    cc->tcg_initialize = mips_tcg_init;
+    cc->tcg_ops.initialize = mips_tcg_init;
     cc->tlb_fill = mips_cpu_tlb_fill;
 #endif
 }
diff --git a/qemu/target/riscv/cpu.c b/qemu/target/riscv/cpu.c
index f3a6c951..8017dc4a 100644
--- a/qemu/target/riscv/cpu.c
+++ b/qemu/target/riscv/cpu.c
@@ -373,7 +373,7 @@ static void riscv_cpu_class_init(struct uc_struct *uc, ObjectClass *oc, void *da
     cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
 #endif
 #ifdef CONFIG_TCG
-    cc->tcg_initialize = riscv_translate_init;
+    cc->tcg_ops.initialize = riscv_translate_init;
     cc->tlb_fill = riscv_cpu_tlb_fill;
 #endif
     /* For now, mark unmigratable: */
diff --git a/qemu/target/sparc/cpu.c b/qemu/target/sparc/cpu.c
index 00426d7c..63f608d9 100644
--- a/qemu/target/sparc/cpu.c
+++ b/qemu/target/sparc/cpu.c
@@ -856,7 +856,7 @@ static void sparc_cpu_class_init(struct uc_struct *uc, ObjectClass *oc, void *da
     // Unicorn: commented out
     //cc->vmsd = &vmstate_sparc_cpu;
 #endif
-    cc->tcg_initialize = sparc_tcg_init;
+    cc->tcg_ops.initialize = sparc_tcg_init;
 }
 
 static void sparc_cpu_cpudef_class_init(struct uc_struct *uc, ObjectClass *oc, void *data)