From b9eda7c4644748e33024b1e4bf5a853ec5932118 Mon Sep 17 00:00:00 2001 From: Bastian Koppelmann Date: Tue, 19 Mar 2019 05:23:45 -0400 Subject: [PATCH] target/riscv: Remove shift and slt insn manual decoding Backports commit 34446e845829f55eaa9a07a915950af0b2710b47 from qemu --- qemu/target/riscv/insn_trans/trans_rvi.inc.c | 99 +++++++++++++------- qemu/target/riscv/translate.c | 60 ++++-------- 2 files changed, 85 insertions(+), 74 deletions(-) diff --git a/qemu/target/riscv/insn_trans/trans_rvi.inc.c b/qemu/target/riscv/insn_trans/trans_rvi.inc.c index 7645e67c..24332517 100644 --- a/qemu/target/riscv/insn_trans/trans_rvi.inc.c +++ b/qemu/target/riscv/insn_trans/trans_rvi.inc.c @@ -228,32 +228,24 @@ static bool trans_addi(DisasContext *ctx, arg_addi *a) return gen_arith_imm(ctx, a, &tcg_gen_add_tl); } +static void gen_slt(TCGContext *tcg_ctx, TCGv ret, TCGv s1, TCGv s2) +{ + tcg_gen_setcond_tl(tcg_ctx, TCG_COND_LT, ret, s1, s2); +} + +static void gen_sltu(TCGContext *tcg_ctx, TCGv ret, TCGv s1, TCGv s2) +{ + tcg_gen_setcond_tl(tcg_ctx, TCG_COND_LTU, ret, s1, s2); +} + static bool trans_slti(DisasContext *ctx, arg_slti *a) { - TCGContext *tcg_ctx = ctx->uc->tcg_ctx; - TCGv source1; - source1 = tcg_temp_new(tcg_ctx); - gen_get_gpr(ctx, source1, a->rs1); - - tcg_gen_setcondi_tl(tcg_ctx, TCG_COND_LT, source1, source1, a->imm); - - gen_set_gpr(ctx, a->rd, source1); - tcg_temp_free(tcg_ctx, source1); - return true; + return gen_arith_imm(ctx, a, &gen_slt); } static bool trans_sltiu(DisasContext *ctx, arg_sltiu *a) { - TCGContext *tcg_ctx = ctx->uc->tcg_ctx; - TCGv source1; - source1 = tcg_temp_new(tcg_ctx); - gen_get_gpr(ctx, source1, a->rs1); - - tcg_gen_setcondi_tl(tcg_ctx, TCG_COND_LTU, source1, source1, a->imm); - - gen_set_gpr(ctx, a->rd, source1); - tcg_temp_free(tcg_ctx, source1); - return true; + return gen_arith_imm(ctx, a, &gen_sltu); } static bool trans_xori(DisasContext *ctx, arg_xori *a) @@ -335,20 +327,17 @@ static bool trans_sub(DisasContext *ctx, arg_sub *a) static bool trans_sll(DisasContext *ctx, arg_sll *a) { - gen_arith(ctx, OPC_RISC_SLL, a->rd, a->rs1, a->rs2); - return true; + return gen_shift(ctx, a, &tcg_gen_shl_tl); } static bool trans_slt(DisasContext *ctx, arg_slt *a) { - gen_arith(ctx, OPC_RISC_SLT, a->rd, a->rs1, a->rs2); - return true; + return trans_arith(ctx, a, &gen_slt); } static bool trans_sltu(DisasContext *ctx, arg_sltu *a) { - gen_arith(ctx, OPC_RISC_SLTU, a->rd, a->rs1, a->rs2); - return true; + return trans_arith(ctx, a, &gen_sltu); } static bool trans_xor(DisasContext *ctx, arg_xor *a) @@ -358,14 +347,12 @@ static bool trans_xor(DisasContext *ctx, arg_xor *a) static bool trans_srl(DisasContext *ctx, arg_srl *a) { - gen_arith(ctx, OPC_RISC_SRL, a->rd, a->rs1, a->rs2); - return true; + return gen_shift(ctx, a, &tcg_gen_shr_tl); } static bool trans_sra(DisasContext *ctx, arg_sra *a) { - gen_arith(ctx, OPC_RISC_SRA, a->rd, a->rs1, a->rs2); - return true; + return gen_shift(ctx, a, &tcg_gen_sar_tl); } static bool trans_or(DisasContext *ctx, arg_or *a) @@ -435,19 +422,65 @@ static bool trans_subw(DisasContext *ctx, arg_subw *a) static bool trans_sllw(DisasContext *ctx, arg_sllw *a) { - gen_arith(ctx, OPC_RISC_SLLW, a->rd, a->rs1, a->rs2); + TCGContext *tcg_ctx = ctx->uc->tcg_ctx; + TCGv source1 = tcg_temp_new(tcg_ctx); + TCGv source2 = tcg_temp_new(tcg_ctx); + + gen_get_gpr(ctx, source1, a->rs1); + gen_get_gpr(ctx, source2, a->rs2); + + tcg_gen_andi_tl(tcg_ctx, source2, source2, 0x1F); + tcg_gen_shl_tl(tcg_ctx, source1, source1, source2); + + tcg_gen_ext32s_tl(tcg_ctx, source1, source1); + gen_set_gpr(ctx, a->rd, source1); + tcg_temp_free(tcg_ctx, source1); + tcg_temp_free(tcg_ctx, source2); return true; } static bool trans_srlw(DisasContext *ctx, arg_srlw *a) { - gen_arith(ctx, OPC_RISC_SRLW, a->rd, a->rs1, a->rs2); + TCGContext *tcg_ctx = ctx->uc->tcg_ctx; + TCGv source1 = tcg_temp_new(tcg_ctx); + TCGv source2 = tcg_temp_new(tcg_ctx); + + gen_get_gpr(ctx, source1, a->rs1); + gen_get_gpr(ctx, source2, a->rs2); + + /* clear upper 32 */ + tcg_gen_ext32u_tl(tcg_ctx, source1, source1); + tcg_gen_andi_tl(tcg_ctx, source2, source2, 0x1F); + tcg_gen_shr_tl(tcg_ctx, source1, source1, source2); + + tcg_gen_ext32s_tl(tcg_ctx, source1, source1); + gen_set_gpr(ctx, a->rd, source1); + tcg_temp_free(tcg_ctx, source1); + tcg_temp_free(tcg_ctx, source2); return true; } static bool trans_sraw(DisasContext *ctx, arg_sraw *a) { - gen_arith(ctx, OPC_RISC_SRAW, a->rd, a->rs1, a->rs2); + TCGContext *tcg_ctx = ctx->uc->tcg_ctx; + TCGv source1 = tcg_temp_new(tcg_ctx); + TCGv source2 = tcg_temp_new(tcg_ctx); + + gen_get_gpr(ctx, source1, a->rs1); + gen_get_gpr(ctx, source2, a->rs2); + + /* + * first, trick to get it to act like working on 32 bits (get rid of + * upper 32, sign extend to fill space) + */ + tcg_gen_ext32s_tl(tcg_ctx, source1, source1); + tcg_gen_andi_tl(tcg_ctx, source2, source2, 0x1F); + tcg_gen_sar_tl(tcg_ctx, source1, source1, source2); + + gen_set_gpr(ctx, a->rd, source1); + tcg_temp_free(tcg_ctx, source1); + tcg_temp_free(tcg_ctx, source2); + return true; } #endif diff --git a/qemu/target/riscv/translate.c b/qemu/target/riscv/translate.c index c7601f58..19b73898 100644 --- a/qemu/target/riscv/translate.c +++ b/qemu/target/riscv/translate.c @@ -212,47 +212,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, int rd, int rs1, gen_get_gpr(ctx, source2, rs2); switch (opc) { -#if defined(TARGET_RISCV64) - case OPC_RISC_SLLW: - tcg_gen_andi_tl(tcg_ctx, source2, source2, 0x1F); - tcg_gen_shl_tl(tcg_ctx, source1, source1, source2); - break; -#endif - case OPC_RISC_SLL: - tcg_gen_andi_tl(tcg_ctx, source2, source2, TARGET_LONG_BITS - 1); - tcg_gen_shl_tl(tcg_ctx, source1, source1, source2); - break; - case OPC_RISC_SLT: - tcg_gen_setcond_tl(tcg_ctx, TCG_COND_LT, source1, source1, source2); - break; - case OPC_RISC_SLTU: - tcg_gen_setcond_tl(tcg_ctx, TCG_COND_LTU, source1, source1, source2); - break; -#if defined(TARGET_RISCV64) - case OPC_RISC_SRLW: - /* clear upper 32 */ - tcg_gen_ext32u_tl(tcg_ctx, source1, source1); - tcg_gen_andi_tl(tcg_ctx, source2, source2, 0x1F); - tcg_gen_shr_tl(tcg_ctx, source1, source1, source2); - break; -#endif - case OPC_RISC_SRL: - tcg_gen_andi_tl(tcg_ctx, source2, source2, TARGET_LONG_BITS - 1); - tcg_gen_shr_tl(tcg_ctx, source1, source1, source2); - break; -#if defined(TARGET_RISCV64) - case OPC_RISC_SRAW: - /* first, trick to get it to act like working on 32 bits (get rid of - upper 32, sign extend to fill space) */ - tcg_gen_ext32s_tl(tcg_ctx, source1, source1); - tcg_gen_andi_tl(tcg_ctx, source2, source2, 0x1F); - tcg_gen_sar_tl(tcg_ctx, source1, source1, source2); - break; -#endif - case OPC_RISC_SRA: - tcg_gen_andi_tl(tcg_ctx, source2, source2, TARGET_LONG_BITS - 1); - tcg_gen_sar_tl(tcg_ctx, source1, source1, source2); - break; CASE_OP_32_64(OPC_RISC_MUL): if (!has_ext(ctx, RVM)) { goto do_illegal; @@ -766,6 +725,25 @@ static bool trans_arith(DisasContext *ctx, arg_r *a, return true; } +static bool gen_shift(DisasContext *ctx, arg_r *a, + void(*func)(TCGContext *, TCGv, TCGv, TCGv)) +{ + TCGContext *tcg_ctx = ctx->uc->tcg_ctx; + TCGv source1 = tcg_temp_new(tcg_ctx); + TCGv source2 = tcg_temp_new(tcg_ctx); + + gen_get_gpr(ctx, source1, a->rs1); + gen_get_gpr(ctx, source2, a->rs2); + + tcg_gen_andi_tl(tcg_ctx, source2, source2, TARGET_LONG_BITS - 1); + (*func)(tcg_ctx, source1, source1, source2); + + gen_set_gpr(ctx, a->rd, source1); + tcg_temp_free(tcg_ctx, source1); + tcg_temp_free(tcg_ctx, source2); + return true; +} + /* Include insn module translation function */ #include "insn_trans/trans_rvi.inc.c" #include "insn_trans/trans_rvm.inc.c"