From ba8df54753b03384a5e2083c8160eff3b6f46c1f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20Benn=C3=A9e?= Date: Thu, 8 Mar 2018 12:59:06 -0500 Subject: [PATCH] arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to simd_three_reg_same_fp16 These use the generic float16_compare functionality which in turn uses the common float_compare code from the softfloat re-factor. Backports commit d32adeae1a71a8e71374fa48d3d6ab0ad4c23e94 from qemu --- qemu/aarch64.h | 5 ++++ qemu/aarch64eb.h | 5 ++++ qemu/header_gen.py | 5 ++++ qemu/target/arm/helper-a64.c | 49 +++++++++++++++++++++++++++++++++ qemu/target/arm/helper-a64.h | 5 ++++ qemu/target/arm/translate-a64.c | 15 ++++++++++ 6 files changed, 84 insertions(+) diff --git a/qemu/aarch64.h b/qemu/aarch64.h index 96b8c525..9a1a2295 100644 --- a/qemu/aarch64.h +++ b/qemu/aarch64.h @@ -3720,7 +3720,12 @@ #define arm_set_cpu_off arm_set_cpu_off_aarch64 #define arm_set_cpu_on arm_set_cpu_on_aarch64 #define gen_a64_set_pc_im gen_a64_set_pc_im_aarch64 +#define helper_advsimd_acge_f16 helper_advsimd_acge_f16_aarch64 +#define helper_advsimd_acgt_f16 helper_advsimd_acgt_f16_aarch64 #define helper_advsimd_addh helper_advsimd_addh_aarch64 +#define helper_advsimd_ceq_f16 helper_advsimd_ceq_f16_aarch64 +#define helper_advsimd_cge_f16 helper_advsimd_cge_f16_aarch64 +#define helper_advsimd_cgt_f16 helper_advsimd_cgt_f16_aarch64 #define helper_advsimd_divh helper_advsimd_divh_aarch64 #define helper_advsimd_maxh helper_advsimd_maxh_aarch64 #define helper_advsimd_maxnumh helper_advsimd_maxnumh_aarch64 diff --git a/qemu/aarch64eb.h b/qemu/aarch64eb.h index 5fb8ca97..e2738489 100644 --- a/qemu/aarch64eb.h +++ b/qemu/aarch64eb.h @@ -3720,7 +3720,12 @@ #define arm_set_cpu_off arm_set_cpu_off_aarch64eb #define arm_set_cpu_on arm_set_cpu_on_aarch64eb #define gen_a64_set_pc_im gen_a64_set_pc_im_aarch64eb +#define helper_advsimd_acge_f16 helper_advsimd_acge_f16_aarch64eb +#define helper_advsimd_acgt_f16 helper_advsimd_acgt_f16_aarch64eb #define helper_advsimd_addh helper_advsimd_addh_aarch64eb +#define helper_advsimd_ceq_f16 helper_advsimd_ceq_f16_aarch64eb +#define helper_advsimd_cge_f16 helper_advsimd_cge_f16_aarch64eb +#define helper_advsimd_cgt_f16 helper_advsimd_cgt_f16_aarch64eb #define helper_advsimd_divh helper_advsimd_divh_aarch64eb #define helper_advsimd_maxh helper_advsimd_maxh_aarch64eb #define helper_advsimd_maxnumh helper_advsimd_maxnumh_aarch64eb diff --git a/qemu/header_gen.py b/qemu/header_gen.py index 8e70cd74..faea172e 100644 --- a/qemu/header_gen.py +++ b/qemu/header_gen.py @@ -3740,7 +3740,12 @@ aarch64_symbols = ( 'arm_set_cpu_off', 'arm_set_cpu_on', 'gen_a64_set_pc_im', + 'helper_advsimd_acge_f16', + 'helper_advsimd_acgt_f16', 'helper_advsimd_addh', + 'helper_advsimd_ceq_f16', + 'helper_advsimd_cge_f16', + 'helper_advsimd_cgt_f16', 'helper_advsimd_divh', 'helper_advsimd_maxh', 'helper_advsimd_maxnumh', diff --git a/qemu/target/arm/helper-a64.c b/qemu/target/arm/helper-a64.c index 21bb994a..f2ab52b4 100644 --- a/qemu/target/arm/helper-a64.c +++ b/qemu/target/arm/helper-a64.c @@ -640,3 +640,52 @@ ADVSIMD_HALFOP(min) ADVSIMD_HALFOP(max) ADVSIMD_HALFOP(minnum) ADVSIMD_HALFOP(maxnum) + +/* + * Floating point comparisons produce an integer result. Softfloat + * routines return float_relation types which we convert to the 0/-1 + * Neon requires. + */ + +#define ADVSIMD_CMPRES(test) (test) ? 0xffff : 0 + +uint32_t HELPER(advsimd_ceq_f16)(float16 a, float16 b, void *fpstp) +{ + float_status *fpst = fpstp; + int compare = float16_compare_quiet(a, b, fpst); + return ADVSIMD_CMPRES(compare == float_relation_equal); +} + +uint32_t HELPER(advsimd_cge_f16)(float16 a, float16 b, void *fpstp) +{ + float_status *fpst = fpstp; + int compare = float16_compare(a, b, fpst); + return ADVSIMD_CMPRES(compare == float_relation_greater || + compare == float_relation_equal); +} + +uint32_t HELPER(advsimd_cgt_f16)(float16 a, float16 b, void *fpstp) +{ + float_status *fpst = fpstp; + int compare = float16_compare(a, b, fpst); + return ADVSIMD_CMPRES(compare == float_relation_greater); +} + +uint32_t HELPER(advsimd_acge_f16)(float16 a, float16 b, void *fpstp) +{ + float_status *fpst = fpstp; + float16 f0 = float16_abs(a); + float16 f1 = float16_abs(b); + int compare = float16_compare(f0, f1, fpst); + return ADVSIMD_CMPRES(compare == float_relation_greater || + compare == float_relation_equal); +} + +uint32_t HELPER(advsimd_acgt_f16)(float16 a, float16 b, void *fpstp) +{ + float_status *fpst = fpstp; + float16 f0 = float16_abs(a); + float16 f1 = float16_abs(b); + int compare = float16_compare(f0, f1, fpst); + return ADVSIMD_CMPRES(compare == float_relation_greater); +} diff --git a/qemu/target/arm/helper-a64.h b/qemu/target/arm/helper-a64.h index 289ea481..c5c4b390 100644 --- a/qemu/target/arm/helper-a64.h +++ b/qemu/target/arm/helper-a64.h @@ -52,3 +52,8 @@ DEF_HELPER_3(advsimd_addh, f16, f16, f16, ptr) DEF_HELPER_3(advsimd_subh, f16, f16, f16, ptr) DEF_HELPER_3(advsimd_mulh, f16, f16, f16, ptr) DEF_HELPER_3(advsimd_divh, f16, f16, f16, ptr) +DEF_HELPER_3(advsimd_ceq_f16, i32, f16, f16, ptr) +DEF_HELPER_3(advsimd_cge_f16, i32, f16, f16, ptr) +DEF_HELPER_3(advsimd_cgt_f16, i32, f16, f16, ptr) +DEF_HELPER_3(advsimd_acge_f16, i32, f16, f16, ptr) +DEF_HELPER_3(advsimd_acgt_f16, i32, f16, f16, ptr) diff --git a/qemu/target/arm/translate-a64.c b/qemu/target/arm/translate-a64.c index 7eeac3bc..531d435e 100644 --- a/qemu/target/arm/translate-a64.c +++ b/qemu/target/arm/translate-a64.c @@ -10441,6 +10441,9 @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn) case 0x2: /* FADD */ gen_helper_advsimd_addh(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst); break; + case 0x4: /* FCMEQ */ + gen_helper_advsimd_ceq_f16(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst); + break; case 0x6: /* FMAX */ gen_helper_advsimd_maxh(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst); break; @@ -10456,6 +10459,12 @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn) case 0x13: /* FMUL */ gen_helper_advsimd_mulh(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst); break; + case 0x14: /* FCMGE */ + gen_helper_advsimd_cge_f16(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x15: /* FACGE */ + gen_helper_advsimd_acge_f16(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst); + break; case 0x17: /* FDIV */ gen_helper_advsimd_divh(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst); break; @@ -10463,6 +10472,12 @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn) gen_helper_advsimd_subh(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst); tcg_gen_andi_i32(tcg_ctx, tcg_res, tcg_res, 0x7fff); break; + case 0x1c: /* FCMGT */ + gen_helper_advsimd_cgt_f16(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst); + break; + case 0x1d: /* FACGT */ + gen_helper_advsimd_acgt_f16(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst); + break; default: fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n", __func__, insn, fpopcode, s->pc);