From c0cebeb5b5e2f60d1dc4d48d86ba9d034b12a4d3 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Tue, 30 Apr 2019 10:20:44 -0400 Subject: [PATCH] target/arm: Clear CONTROL_S.SFPA in SG insn if FPU present If the floating point extension is present, then the SG instruction must clear the CONTROL_S.SFPA bit. Implement this. (On a no-FPU system the bit will always be zero, so we don't need to make the clearing of the bit conditional on ARM_FEATURE_VFP.) Backports commit 1702071302934af77a072b7ee7c5eadc45b37573 from qemu --- qemu/target/arm/helper.c | 1 + 1 file changed, 1 insertion(+) diff --git a/qemu/target/arm/helper.c b/qemu/target/arm/helper.c index dffd2d0a..d946307b 100644 --- a/qemu/target/arm/helper.c +++ b/qemu/target/arm/helper.c @@ -8623,6 +8623,7 @@ static bool v7m_handle_execute_nsc(ARMCPU *cpu) qemu_log_mask(CPU_LOG_INT, "...really an SG instruction at 0x%08" PRIx32 ", executing it\n", env->regs[15]); env->regs[14] &= ~1; + env->v7m.control[M_REG_S] &= ~R_V7M_CONTROL_SFPA_MASK; switch_v7m_security_state(env, true); xpsr_write(env, 0, XPSR_IT); env->regs[15] += 4;