From c21d2062e4221597d1aeb5989fb752600737edfb Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Wed, 22 Aug 2018 12:45:21 -0400 Subject: [PATCH] target/arm: Implement AArch32 Hyp FARs The AArch32 virtualization extensions support these fault address registers: * HDFAR: aliased with AArch64 FAR_EL2[31:0] and AArch32 DFAR(S) * HIFAR: aliased with AArch64 FAR_EL2[63:32] and AArch32 IFAR(S) Implement the accessors for these. This fixes in passing a bug where we weren't implementing the "RES0 from EL3 if EL2 not implemented" behaviour for AArch64 FAR_EL2. Backports commit cba517c31e7df8932c4473c477a0f01d8a0adc48 from qemu --- qemu/target/arm/helper.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/qemu/target/arm/helper.c b/qemu/target/arm/helper.c index 98ec2f06..b2e78d53 100644 --- a/qemu/target/arm/helper.c +++ b/qemu/target/arm/helper.c @@ -3406,6 +3406,10 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = { access_el3_aa32ns_aa64any }, { "HSTR_EL2", 0,1,1, 3,4,3, ARM_CP_STATE_BOTH, ARM_CP_CONST, PL2_RW, 0, NULL, 0 }, + { "FAR_EL2", 0,6,0, 3,4,0, ARM_CP_STATE_BOTH, ARM_CP_CONST, + PL2_RW, 0, NULL, 0 }, + { "HIFAR", 15,6,0, 0,4,2, ARM_CP_STATE_AA32, ARM_CP_CONST, + PL2_RW, 0, NULL, 0 }, REGINFO_SENTINEL }; @@ -3449,8 +3453,10 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { ARM_CP_ALIAS, PL2_RW, 0, NULL, 0, offsetof(CPUARMState, elr_el[2]) }, { "ESR_EL2", 0,5,2, 3,4,0, ARM_CP_STATE_AA64, 0, PL2_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.esr_el[2]) }, - { "FAR_EL2", 0,6,0, 3,4,0, ARM_CP_STATE_AA64, + { "FAR_EL2", 0,6,0, 3,4,0, ARM_CP_STATE_BOTH, 0, PL2_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.far_el[2]) }, + { "HIFAR", 15,6,0, 0,4,2, ARM_CP_STATE_AA32, + ARM_CP_ALIAS, PL2_RW, 0, NULL, 0, offsetofhigh32(CPUARMState, cp15.far_el[2]) }, { "SPSR_EL2", 0,4,0, 3,4,0, ARM_CP_STATE_AA64, ARM_CP_ALIAS, PL2_RW, 0, NULL, 0, offsetof(CPUARMState, banked_spsr[BANK_HYP]) }, { "VBAR_EL2", 0,12,0, 3,4,0, ARM_CP_STATE_BOTH,