From 291b5753ebf4c9bad601addc6fbecb40c5d69f7c Mon Sep 17 00:00:00 2001 From: Lioncash Date: Fri, 2 Feb 2018 07:59:20 -0500 Subject: [PATCH 1/6] Backport the THUMB_DSP feature flag Backports commit 62b44f059a84d1ac580a653fc4110dfabaef6b83 in qemu to unicorn. --- qemu/target-arm/cpu.c | 4 ++ qemu/target-arm/cpu.h | 1 + qemu/target-arm/translate.c | 112 ++++++++++++++++++++++++++++++++---- 3 files changed, 107 insertions(+), 10 deletions(-) diff --git a/qemu/target-arm/cpu.c b/qemu/target-arm/cpu.c index 7a0b8393..32f18828 100644 --- a/qemu/target-arm/cpu.c +++ b/qemu/target-arm/cpu.c @@ -382,6 +382,10 @@ static int arm_cpu_realizefn(struct uc_struct *uc, DeviceState *dev, Error **err if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { set_feature(env, ARM_FEATURE_CBAR); } + if (arm_feature(env, ARM_FEATURE_THUMB2) && + !arm_feature(env, ARM_FEATURE_M)) { + set_feature(env, ARM_FEATURE_THUMB_DSP); + } if (cpu->reset_hivecs) { cpu->reset_sctlr |= (1 << 13); diff --git a/qemu/target-arm/cpu.h b/qemu/target-arm/cpu.h index 01c63221..c425da5f 100644 --- a/qemu/target-arm/cpu.h +++ b/qemu/target-arm/cpu.h @@ -749,6 +749,7 @@ enum arm_features { ARM_FEATURE_V8_SHA1, /* implements SHA1 part of v8 Crypto Extensions */ ARM_FEATURE_V8_SHA256, /* implements SHA256 part of v8 Crypto Extensions */ ARM_FEATURE_V8_PMULL, /* implements PMULL part of v8 Crypto Extensions */ + ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ ARM_FEATURE_V8_SHA3, /* implements SHA3 part of v8 Crypto Extensions */ }; diff --git a/qemu/target-arm/translate.c b/qemu/target-arm/translate.c index 27527811..52496793 100644 --- a/qemu/target-arm/translate.c +++ b/qemu/target-arm/translate.c @@ -9529,6 +9529,9 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw op = (insn >> 21) & 0xf; if (op == 6) { + if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { + goto illegal_op; + } /* Halfword pack. */ tmp = load_reg(s, rn); tmp2 = load_reg(s, rm); @@ -9593,6 +9596,27 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw store_reg_bx(s, rd, tmp); break; case 1: /* Sign/zero extend. */ + op = (insn >> 20) & 7; + switch (op) { + case 0: /* SXTAH, SXTH */ + case 1: /* UXTAH, UXTH */ + case 4: /* SXTAB, SXTB */ + case 5: /* UXTAB, UXTB */ + break; + case 2: /* SXTAB16, SXTB16 */ + case 3: /* UXTAB16, UXTB16 */ + if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { + goto illegal_op; + } + break; + default: + goto illegal_op; + } + if (rn != 15) { + if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { + goto illegal_op; + } + } tmp = load_reg(s, rm); shift = (insn >> 4) & 3; /* ??? In many cases it's not necessary to do a @@ -9607,7 +9631,8 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw case 3: gen_uxtb16(tmp); break; case 4: gen_sxtb(tmp); break; case 5: gen_uxtb(tmp); break; - default: goto illegal_op; + default: + g_assert_not_reached(); } if (rn != 15) { tmp2 = load_reg(s, rn); @@ -9621,6 +9646,9 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw store_reg(s, rd, tmp); break; case 2: /* SIMD add/subtract. */ + if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { + goto illegal_op; + } op = (insn >> 20) & 7; shift = (insn >> 4) & 7; if ((op & 3) == 3 || (shift & 3) == 3) @@ -9635,6 +9663,9 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw op = ((insn >> 17) & 0x38) | ((insn >> 4) & 7); if (op < 4) { /* Saturating add/subtract. */ + if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { + goto illegal_op; + } tmp = load_reg(s, rn); tmp2 = load_reg(s, rm); if (op & 1) @@ -9645,6 +9676,31 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw gen_helper_add_saturate(tcg_ctx, tmp, tcg_ctx->cpu_env, tmp, tmp2); tcg_temp_free_i32(tcg_ctx, tmp2); } else { + switch (op) { + case 0x0a: /* rbit */ + case 0x08: /* rev */ + case 0x09: /* rev16 */ + case 0x0b: /* revsh */ + case 0x18: /* clz */ + break; + case 0x10: /* sel */ + if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { + goto illegal_op; + } + break; + case 0x20: /* crc32/crc32c */ + case 0x21: + case 0x22: + case 0x28: + case 0x29: + case 0x2a: + if (!arm_dc_feature(s, ARM_FEATURE_CRC)) { + goto illegal_op; + } + break; + default: + goto illegal_op; + } tmp = load_reg(s, rn); switch (op) { case 0x0a: /* rbit */ @@ -9681,10 +9737,6 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw uint32_t sz = op & 0x3; uint32_t c = op & 0x8; - if (!arm_dc_feature(s, ARM_FEATURE_CRC)) { - goto illegal_op; - } - tmp2 = load_reg(s, rm); if (sz == 0) { tcg_gen_andi_i32(tcg_ctx, tmp2, tmp2, 0xff); @@ -9702,12 +9754,26 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw break; } default: - goto illegal_op; + g_assert_not_reached(); } } store_reg(s, rd, tmp); break; case 4: case 5: /* 32-bit multiply. Sum of absolute differences. */ + switch ((insn >> 20) & 7) { + case 0: /* 32 x 32 -> 32 */ + case 7: /* Unsigned sum of absolute differences. */ + break; + case 1: /* 16 x 16 -> 32 */ + case 2: /* Dual multiply add. */ + case 3: /* 32 * 16 -> 32msb */ + case 4: /* Dual multiply subtract. */ + case 5: case 6: /* 32 * 32 -> 32msb (SMMUL, SMMLA, SMMLS) */ + if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { + goto illegal_op; + } + break; + } op = (insn >> 4) & 0xf; tmp = load_reg(s, rn); tmp2 = load_reg(s, rm); @@ -9820,6 +9886,11 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw store_reg(s, rd, tmp); } else if ((op & 0xe) == 0xc) { /* Dual multiply accumulate long. */ + if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { + tcg_temp_free_i32(tcg_ctx, tmp); + tcg_temp_free_i32(tcg_ctx, tmp2); + goto illegal_op; + } if (op & 1) gen_swap_half(s, tmp2); gen_smul_dual(s, tmp, tmp2); @@ -9843,6 +9914,11 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw } else { if (op & 8) { /* smlalxy */ + if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { + tcg_temp_free_i32(tcg_ctx, tmp2); + tcg_temp_free_i32(tcg_ctx, tmp); + goto illegal_op; + } gen_mulxy(s, tmp, tmp2, op & 2, op & 1); tcg_temp_free_i32(tcg_ctx, tmp2); tmp64 = tcg_temp_new_i64(tcg_ctx); @@ -9855,6 +9931,10 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw } if (op & 4) { /* umaal */ + if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { + tcg_temp_free_i64(tcg_ctx, tmp64); + goto illegal_op; + } gen_addq_lo(s, tmp64, rs); gen_addq_lo(s, tmp64, rd); } else if (op & 0x40) { @@ -10119,16 +10199,28 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw tmp2 = tcg_const_i32(tcg_ctx, imm); if (op & 4) { /* Unsigned. */ - if ((op & 1) && shift == 0) + if ((op & 1) && shift == 0) { + if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { + tcg_temp_free_i32(tcg_ctx, tmp); + tcg_temp_free_i32(tcg_ctx, tmp2); + goto illegal_op; + } gen_helper_usat16(tcg_ctx, tmp, tcg_ctx->cpu_env, tmp, tmp2); - else + } else { gen_helper_usat(tcg_ctx, tmp, tcg_ctx->cpu_env, tmp, tmp2); + } } else { /* Signed. */ - if ((op & 1) && shift == 0) + if ((op & 1) && shift == 0) { + if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { + tcg_temp_free_i32(tcg_ctx, tmp); + tcg_temp_free_i32(tcg_ctx, tmp2); + goto illegal_op; + } gen_helper_ssat16(tcg_ctx, tmp, tcg_ctx->cpu_env, tmp, tmp2); - else + } else { gen_helper_ssat(tcg_ctx, tmp, tcg_ctx->cpu_env, tmp, tmp2); + } } tcg_temp_free_i32(tcg_ctx, tmp2); break; From 35100ce4e03321d5e42cd9c62114f0cf64583fa4 Mon Sep 17 00:00:00 2001 From: Lioncash Date: Fri, 2 Feb 2018 08:23:47 -0500 Subject: [PATCH 2/6] Backport the VBAR feature flag Backports commit 91db4642f868cf2e591b62d31a19d35b02ea791e from qemu to unicorn --- qemu/target-arm/cpu.c | 9 +++++++++ qemu/target-arm/cpu.h | 1 + qemu/target-arm/helper.c | 13 ++++++++++--- 3 files changed, 20 insertions(+), 3 deletions(-) diff --git a/qemu/target-arm/cpu.c b/qemu/target-arm/cpu.c index 32f18828..21996742 100644 --- a/qemu/target-arm/cpu.c +++ b/qemu/target-arm/cpu.c @@ -348,6 +348,11 @@ static int arm_cpu_realizefn(struct uc_struct *uc, DeviceState *dev, Error **err } else { set_feature(env, ARM_FEATURE_V6); } + + /* Always define VBAR for V7 CPUs even if it doesn't exist in + * non-EL3 configs. This is needed by some legacy boards. + */ + set_feature(env, ARM_FEATURE_VBAR); } if (arm_feature(env, ARM_FEATURE_V6K)) { set_feature(env, ARM_FEATURE_V6); @@ -391,6 +396,10 @@ static int arm_cpu_realizefn(struct uc_struct *uc, DeviceState *dev, Error **err cpu->reset_sctlr |= (1 << 13); } + if (arm_feature(env, ARM_FEATURE_EL3)) { + set_feature(env, ARM_FEATURE_VBAR); + } + register_cp_regs_for_features(cpu); arm_cpu_register_gdb_regs_for_features(cpu); diff --git a/qemu/target-arm/cpu.h b/qemu/target-arm/cpu.h index c425da5f..c17c011c 100644 --- a/qemu/target-arm/cpu.h +++ b/qemu/target-arm/cpu.h @@ -750,6 +750,7 @@ enum arm_features { ARM_FEATURE_V8_SHA256, /* implements SHA256 part of v8 Crypto Extensions */ ARM_FEATURE_V8_PMULL, /* implements PMULL part of v8 Crypto Extensions */ ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ + ARM_FEATURE_VBAR, /* has cp15 VBAR */ ARM_FEATURE_V8_SHA3, /* implements SHA3 part of v8 Crypto Extensions */ }; diff --git a/qemu/target-arm/helper.c b/qemu/target-arm/helper.c index 93521029..0c6ba525 100644 --- a/qemu/target-arm/helper.c +++ b/qemu/target-arm/helper.c @@ -751,9 +751,6 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { { "PMINTENCLR", 15,9,14, 0,0,2, 0, ARM_CP_NO_MIGRATE, PL1_RW, NULL, 0, offsetof(CPUARMState, cp15.c9_pminten), NULL, NULL, pmintenclr_write, }, - { "VBAR", 0,12,0, 3,0,0, ARM_CP_STATE_BOTH, - 0, PL1_RW, NULL, 0, offsetof(CPUARMState, cp15.vbar_el[1]), - NULL, NULL, vbar_write, }, { "SCR", 15,1,1, 0,0,0, 0, 0, PL1_RW, NULL, 0, offsetoflow32(CPUARMState, cp15.scr_el3), NULL, NULL, scr_write }, @@ -2708,6 +2705,16 @@ void register_cp_regs_for_features(ARMCPU *cpu) } } + if (arm_feature(env, ARM_FEATURE_VBAR)) { + ARMCPRegInfo vbar_cp_reginfo[] = { + { "VBAR", 0,12,0, 3,0,0, ARM_CP_STATE_BOTH, + 0, PL1_RW, NULL, 0, offsetof(CPUARMState, cp15.vbar_el[1]), + NULL, NULL, vbar_write, }, + REGINFO_SENTINEL + }; + define_arm_cp_regs(cpu, vbar_cp_reginfo); + } + /* Generic registers whose values depend on the implementation */ { ARMCPRegInfo sctlr = { From 20038fb801e2364165a8c6fa936d2747200b27b0 Mon Sep 17 00:00:00 2001 From: Lioncash Date: Fri, 2 Feb 2018 08:28:22 -0500 Subject: [PATCH 3/6] Backport the PMU feature flag Backports the applicable code from commit 929e754d5a621cd53f30e69b766ccf381b58d124 to unicorn --- qemu/target-arm/cpu.h | 1 + qemu/target-arm/cpu64.c | 1 + 2 files changed, 2 insertions(+) diff --git a/qemu/target-arm/cpu.h b/qemu/target-arm/cpu.h index c17c011c..70b73079 100644 --- a/qemu/target-arm/cpu.h +++ b/qemu/target-arm/cpu.h @@ -750,6 +750,7 @@ enum arm_features { ARM_FEATURE_V8_SHA256, /* implements SHA256 part of v8 Crypto Extensions */ ARM_FEATURE_V8_PMULL, /* implements PMULL part of v8 Crypto Extensions */ ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ + ARM_FEATURE_PMU, /* has PMU support */ ARM_FEATURE_VBAR, /* has cp15 VBAR */ ARM_FEATURE_V8_SHA3, /* implements SHA3 part of v8 Crypto Extensions */ }; diff --git a/qemu/target-arm/cpu64.c b/qemu/target-arm/cpu64.c index 05d67a7b..c7426e00 100644 --- a/qemu/target-arm/cpu64.c +++ b/qemu/target-arm/cpu64.c @@ -85,6 +85,7 @@ static void aarch64_a57_initfn(struct uc_struct *uc, Object *obj, void *opaque) set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); set_feature(&cpu->env, ARM_FEATURE_CRC); + set_feature(&cpu->env, ARM_FEATURE_PMU); cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57; cpu->midr = 0x411fd070; cpu->reset_fpsid = 0x41034070; From 84319130cdef99d29bb073f9808f87b542de4881 Mon Sep 17 00:00:00 2001 From: Lioncash Date: Fri, 2 Feb 2018 08:44:37 -0500 Subject: [PATCH 4/6] Backport the M_SECURITY feature flag Backports relevant parts from commit 1e577cc7cffd3de14dbd321de5c3ef191c6ab07f in qemu to unicorn --- qemu/target-arm/cpu.c | 4 +++ qemu/target-arm/cpu.h | 3 ++ qemu/target-arm/translate.c | 57 ++++++++++++++++++++++++++++++------- 3 files changed, 54 insertions(+), 10 deletions(-) diff --git a/qemu/target-arm/cpu.c b/qemu/target-arm/cpu.c index 21996742..e17354ae 100644 --- a/qemu/target-arm/cpu.c +++ b/qemu/target-arm/cpu.c @@ -139,6 +139,10 @@ static void arm_cpu_reset(CPUState *s) uint32_t initial_msp; /* Loaded from 0x0 */ uint32_t initial_pc; /* Loaded from 0x4 */ + if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { + env->v7m.secure = true; + } + env->daif &= ~PSTATE_I; #if 0 uint8_t *rom; diff --git a/qemu/target-arm/cpu.h b/qemu/target-arm/cpu.h index 70b73079..e1c505f6 100644 --- a/qemu/target-arm/cpu.h +++ b/qemu/target-arm/cpu.h @@ -63,6 +63,7 @@ #define ARMV7M_EXCP_MEM 4 #define ARMV7M_EXCP_BUS 5 #define ARMV7M_EXCP_USAGE 6 +#define ARMV7M_EXCP_SECURE 7 #define ARMV7M_EXCP_SVC 11 #define ARMV7M_EXCP_DEBUG 12 #define ARMV7M_EXCP_PENDSV 14 @@ -246,6 +247,7 @@ typedef struct CPUARMState { int current_sp; int exception; int pending_exception; + uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ } v7m; /* Information associated with an exception about to be taken: @@ -752,6 +754,7 @@ enum arm_features { ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ ARM_FEATURE_PMU, /* has PMU support */ ARM_FEATURE_VBAR, /* has cp15 VBAR */ + ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ ARM_FEATURE_V8_SHA3, /* implements SHA3 part of v8 Crypto Extensions */ }; diff --git a/qemu/target-arm/translate.c b/qemu/target-arm/translate.c index 52496793..be1c7a96 100644 --- a/qemu/target-arm/translate.c +++ b/qemu/target-arm/translate.c @@ -11659,7 +11659,6 @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; int i; - uint32_t psr; if (is_a64(env)) { aarch64_cpu_dump_state(cs, f, cpu_fprintf, flags); @@ -11673,15 +11672,53 @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, else cpu_fprintf(f, " "); } - psr = cpsr_read(env); - cpu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%d\n", - psr, - psr & (1 << 31) ? 'N' : '-', - psr & (1 << 30) ? 'Z' : '-', - psr & (1 << 29) ? 'C' : '-', - psr & (1 << 28) ? 'V' : '-', - psr & CPSR_T ? 'T' : 'A', - cpu_mode_names[psr & 0xf], (psr & 0x10) ? 32 : 26); + + if (arm_feature(env, ARM_FEATURE_M)) { + uint32_t xpsr = xpsr_read(env); + const char *mode; + const char *ns_status = ""; + + if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { + ns_status = env->v7m.secure ? "S " : "NS "; + } + + if (xpsr & XPSR_EXCP) { + mode = "handler"; + } else { + if (env->v7m.control & R_V7M_CONTROL_NPRIV_MASK) { + mode = "unpriv-thread"; + } else { + mode = "priv-thread"; + } + } + + cpu_fprintf(f, "XPSR=%08x %c%c%c%c %c %s%s\n", + xpsr, + xpsr & XPSR_N ? 'N' : '-', + xpsr & XPSR_Z ? 'Z' : '-', + xpsr & XPSR_C ? 'C' : '-', + xpsr & XPSR_V ? 'V' : '-', + xpsr & XPSR_T ? 'T' : 'A', + ns_status, + mode); + } else { + uint32_t psr = cpsr_read(env); + const char *ns_status = ""; + + if (arm_feature(env, ARM_FEATURE_EL3) && + (psr & CPSR_M) != ARM_CPU_MODE_MON) { + ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; + } + + cpu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%d\n", + psr, + psr & (1 << 31) ? 'N' : '-', + psr & (1 << 30) ? 'Z' : '-', + psr & (1 << 29) ? 'C' : '-', + psr & (1 << 28) ? 'V' : '-', + psr & CPSR_T ? 'T' : 'A', + cpu_mode_names[psr & 0xf], (psr & 0x10) ? 32 : 26); + } if (flags & CPU_DUMP_FPU) { int numvfpregs = 0; From 4fb2fbfacf165853f487529e9fcba4d515775f68 Mon Sep 17 00:00:00 2001 From: Lioncash Date: Fri, 2 Feb 2018 08:50:15 -0500 Subject: [PATCH 5/6] Backport the JAZELLE feature flag Backports commit c99a55d38dd5b5131f3fcbbaf41828a09ee62544 in qemu to unicorn --- qemu/target-arm/cpu.c | 3 +++ qemu/target-arm/cpu.h | 1 + qemu/target-arm/translate.c | 2 +- 3 files changed, 5 insertions(+), 1 deletion(-) diff --git a/qemu/target-arm/cpu.c b/qemu/target-arm/cpu.c index e17354ae..021c6948 100644 --- a/qemu/target-arm/cpu.c +++ b/qemu/target-arm/cpu.c @@ -364,6 +364,7 @@ static int arm_cpu_realizefn(struct uc_struct *uc, DeviceState *dev, Error **err } if (arm_feature(env, ARM_FEATURE_V6)) { set_feature(env, ARM_FEATURE_V5); + set_feature(env, ARM_FEATURE_JAZELLE); if (!arm_feature(env, ARM_FEATURE_M)) { set_feature(env, ARM_FEATURE_AUXCR); } @@ -448,6 +449,7 @@ static void arm926_initfn(struct uc_struct *uc, Object *obj, void *opaque) set_feature(&cpu->env, ARM_FEATURE_VFP); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); + set_feature(&cpu->env, ARM_FEATURE_JAZELLE); cpu->midr = 0x41069265; cpu->reset_fpsid = 0x41011090; cpu->ctr = 0x1dd20d2; @@ -477,6 +479,7 @@ static void arm1026_initfn(struct uc_struct *uc, Object *obj, void *opaque) set_feature(&cpu->env, ARM_FEATURE_AUXCR); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); + set_feature(&cpu->env, ARM_FEATURE_JAZELLE); cpu->midr = 0x4106a262; cpu->reset_fpsid = 0x410110a0; cpu->ctr = 0x1dd20d2; diff --git a/qemu/target-arm/cpu.h b/qemu/target-arm/cpu.h index e1c505f6..d511aeb8 100644 --- a/qemu/target-arm/cpu.h +++ b/qemu/target-arm/cpu.h @@ -755,6 +755,7 @@ enum arm_features { ARM_FEATURE_PMU, /* has PMU support */ ARM_FEATURE_VBAR, /* has cp15 VBAR */ ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ + ARM_FEATURE_JAZELLE, /* has (trivial) Jazelle implementation */ ARM_FEATURE_V8_SHA3, /* implements SHA3 part of v8 Crypto Extensions */ }; diff --git a/qemu/target-arm/translate.c b/qemu/target-arm/translate.c index be1c7a96..931265fe 100644 --- a/qemu/target-arm/translate.c +++ b/qemu/target-arm/translate.c @@ -41,7 +41,7 @@ #define ENABLE_ARCH_5 arm_dc_feature(s, ARM_FEATURE_V5) /* currently all emulated v5 cores are also v5TE, so don't bother */ #define ENABLE_ARCH_5TE arm_dc_feature(s, ARM_FEATURE_V5) -#define ENABLE_ARCH_5J 0 +#define ENABLE_ARCH_5J arm_dc_feature(s, ARM_FEATURE_JAZELLE) #define ENABLE_ARCH_6 arm_dc_feature(s, ARM_FEATURE_V6) #define ENABLE_ARCH_6K arm_dc_feature(s, ARM_FEATURE_V6K) #define ENABLE_ARCH_6T2 arm_dc_feature(s, ARM_FEATURE_THUMB2) From 122d54e23efd90929b4ffbe440d7de9ace99bbdd Mon Sep 17 00:00:00 2001 From: Lioncash Date: Fri, 2 Feb 2018 08:51:56 -0500 Subject: [PATCH 6/6] Backport the SVE feature flag Backports commit 0d0a16c647650d476219a5e1313dec434f9fbebb in qemu to unicorn --- qemu/target-arm/cpu.h | 1 + 1 file changed, 1 insertion(+) diff --git a/qemu/target-arm/cpu.h b/qemu/target-arm/cpu.h index d511aeb8..732b8c32 100644 --- a/qemu/target-arm/cpu.h +++ b/qemu/target-arm/cpu.h @@ -756,6 +756,7 @@ enum arm_features { ARM_FEATURE_VBAR, /* has cp15 VBAR */ ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ ARM_FEATURE_JAZELLE, /* has (trivial) Jazelle implementation */ + ARM_FEATURE_SVE, /* has Scalable Vector Extension */ ARM_FEATURE_V8_SHA3, /* implements SHA3 part of v8 Crypto Extensions */ };