diff --git a/qemu/target/mips/translate.c b/qemu/target/mips/translate.c
index 641ffda8..236f9d77 100644
--- a/qemu/target/mips/translate.c
+++ b/qemu/target/mips/translate.c
@@ -20109,8 +20109,8 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
         case 0:
             /* SHRA_PH */
             gen_helper_shra_ph(tcg_ctx, v1_t, t0, v1_t);
-            break;
             gen_store_gpr(ctx, v1_t, rt);
+            break;
         case 1:
             /* SHRA_R_PH */
             gen_helper_shra_r_ph(tcg_ctx, v1_t, t0, v1_t);