From c387d51c1d732911d5d2996235e5a2ff0f1b1123 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 17 Aug 2018 14:05:09 -0400 Subject: [PATCH] target/arm: Use FZ not FZ16 for SVE FCVT single-half and double-half We were using the wrong flush-to-zero bit for the non-half input. Fixes: 46d33d1e3c9 Backports commit e4ab5124a5c2e2291006b24bdc21c3dd8d087ff4 from qemu --- qemu/target/arm/translate-sve.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qemu/target/arm/translate-sve.c b/qemu/target/arm/translate-sve.c index 00b852c2..ddb03df3 100644 --- a/qemu/target/arm/translate-sve.c +++ b/qemu/target/arm/translate-sve.c @@ -4255,7 +4255,7 @@ static bool do_zpz_ptr(DisasContext *s, int rd, int rn, int pg, static bool trans_FCVT_sh(DisasContext *s, arg_rpr_esz *a, uint32_t insn) { - return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvt_sh); + return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_sh); } static bool trans_FCVT_hs(DisasContext *s, arg_rpr_esz *a, uint32_t insn) @@ -4265,7 +4265,7 @@ static bool trans_FCVT_hs(DisasContext *s, arg_rpr_esz *a, uint32_t insn) static bool trans_FCVT_dh(DisasContext *s, arg_rpr_esz *a, uint32_t insn) { - return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvt_dh); + return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_dh); } static bool trans_FCVT_hd(DisasContext *s, arg_rpr_esz *a, uint32_t insn)