From c497dc0a8306acc54da0fe08c853be64eb043c53 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Tue, 3 Jul 2018 02:26:58 -0400 Subject: [PATCH] target/arm: Implement SVE load and broadcast element Backports commit 684598640dc3b28f86ccc28cc9af50ba257f4cc8 from qemu --- qemu/aarch64.h | 4 +++ qemu/aarch64eb.h | 4 +++ qemu/header_gen.py | 4 +++ qemu/target/arm/helper-sve.h | 5 +++ qemu/target/arm/sve.decode | 5 +++ qemu/target/arm/sve_helper.c | 41 +++++++++++++++++++++ qemu/target/arm/translate-sve.c | 64 +++++++++++++++++++++++++++++++++ 7 files changed, 127 insertions(+) diff --git a/qemu/aarch64.h b/qemu/aarch64.h index ef0dd450..7b807ea6 100644 --- a/qemu/aarch64.h +++ b/qemu/aarch64.h @@ -3660,6 +3660,10 @@ #define helper_sve_mls_d helper_sve_mls_d_aarch64 #define helper_sve_mls_h helper_sve_mls_h_aarch64 #define helper_sve_mls_s helper_sve_mls_s_aarch64 +#define helper_sve_movz_b helper_sve_movz_b_aarch64 +#define helper_sve_movz_d helper_sve_movz_d_aarch64 +#define helper_sve_movz_h helper_sve_movz_h_aarch64 +#define helper_sve_movz_s helper_sve_movz_s_aarch64 #define helper_sve_mul_zpzz_b helper_sve_mul_zpzz_b_aarch64 #define helper_sve_mul_zpzz_d helper_sve_mul_zpzz_d_aarch64 #define helper_sve_mul_zpzz_h helper_sve_mul_zpzz_h_aarch64 diff --git a/qemu/aarch64eb.h b/qemu/aarch64eb.h index 6d391dfa..ba21ba6a 100644 --- a/qemu/aarch64eb.h +++ b/qemu/aarch64eb.h @@ -3660,6 +3660,10 @@ #define helper_sve_mls_d helper_sve_mls_d_aarch64eb #define helper_sve_mls_h helper_sve_mls_h_aarch64eb #define helper_sve_mls_s helper_sve_mls_s_aarch64eb +#define helper_sve_movz_b helper_sve_movz_b_aarch64eb +#define helper_sve_movz_d helper_sve_movz_d_aarch64eb +#define helper_sve_movz_h helper_sve_movz_h_aarch64eb +#define helper_sve_movz_s helper_sve_movz_s_aarch64eb #define helper_sve_mul_zpzz_b helper_sve_mul_zpzz_b_aarch64eb #define helper_sve_mul_zpzz_d helper_sve_mul_zpzz_d_aarch64eb #define helper_sve_mul_zpzz_h helper_sve_mul_zpzz_h_aarch64eb diff --git a/qemu/header_gen.py b/qemu/header_gen.py index 76f91b40..f9d18686 100644 --- a/qemu/header_gen.py +++ b/qemu/header_gen.py @@ -3681,6 +3681,10 @@ aarch64_symbols = ( 'helper_sve_mls_d', 'helper_sve_mls_h', 'helper_sve_mls_s', + 'helper_sve_movz_b', + 'helper_sve_movz_d', + 'helper_sve_movz_h', + 'helper_sve_movz_s', 'helper_sve_mul_zpzz_b', 'helper_sve_mul_zpzz_d', 'helper_sve_mul_zpzz_h', diff --git a/qemu/target/arm/helper-sve.h b/qemu/target/arm/helper-sve.h index 68e55a8d..a5d3bb12 100644 --- a/qemu/target/arm/helper-sve.h +++ b/qemu/target/arm/helper-sve.h @@ -274,6 +274,11 @@ DEF_HELPER_FLAGS_3(sve_clr_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) DEF_HELPER_FLAGS_3(sve_clr_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32) DEF_HELPER_FLAGS_3(sve_clr_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve_movz_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve_movz_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve_movz_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve_movz_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + DEF_HELPER_FLAGS_4(sve_asr_zpzi_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(sve_asr_zpzi_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(sve_asr_zpzi_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) diff --git a/qemu/target/arm/sve.decode b/qemu/target/arm/sve.decode index e510b850..1754e1c4 100644 --- a/qemu/target/arm/sve.decode +++ b/qemu/target/arm/sve.decode @@ -28,6 +28,7 @@ %imm8_16_10 16:5 10:3 %imm9_16_10 16:s6 10:3 %size_23 23:2 +%dtype_23_13 23:2 13:2 # A combination of tsz:imm3 -- extract esize. %tszimm_esz 22:2 5:5 !function=tszimm_esz @@ -751,6 +752,10 @@ LDR_pri 10000101 10 ...... 000 ... ..... 0 .... @pd_rn_i9 # SVE load vector register LDR_zri 10000101 10 ...... 010 ... ..... ..... @rd_rn_i9 +# SVE load and broadcast element +LD1R_zpri 1000010 .. 1 imm:6 1.. pg:3 rn:5 rd:5 \ + &rpri_load dtype=%dtype_23_13 nreg=0 + ### SVE Memory Contiguous Load Group # SVE contiguous load (scalar plus scalar) diff --git a/qemu/target/arm/sve_helper.c b/qemu/target/arm/sve_helper.c index 0c7cd415..4a314a93 100644 --- a/qemu/target/arm/sve_helper.c +++ b/qemu/target/arm/sve_helper.c @@ -994,6 +994,47 @@ void HELPER(sve_clr_d)(void *vd, void *vg, uint32_t desc) } } +/* Copy Zn into Zd, and store zero into inactive elements. */ +void HELPER(sve_movz_b)(void *vd, void *vn, void *vg, uint32_t desc) +{ + intptr_t i, opr_sz = simd_oprsz(desc) / 8; + uint64_t *d = vd, *n = vn; + uint8_t *pg = vg; + for (i = 0; i < opr_sz; i += 1) { + d[i] = n[i] & expand_pred_b(pg[H1(i)]); + } +} + +void HELPER(sve_movz_h)(void *vd, void *vn, void *vg, uint32_t desc) +{ + intptr_t i, opr_sz = simd_oprsz(desc) / 8; + uint64_t *d = vd, *n = vn; + uint8_t *pg = vg; + for (i = 0; i < opr_sz; i += 1) { + d[i] = n[i] & expand_pred_h(pg[H1(i)]); + } +} + +void HELPER(sve_movz_s)(void *vd, void *vn, void *vg, uint32_t desc) +{ + intptr_t i, opr_sz = simd_oprsz(desc) / 8; + uint64_t *d = vd, *n = vn; + uint8_t *pg = vg; + for (i = 0; i < opr_sz; i += 1) { + d[i] = n[i] & expand_pred_s(pg[H1(i)]); + } +} + +void HELPER(sve_movz_d)(void *vd, void *vn, void *vg, uint32_t desc) +{ + intptr_t i, opr_sz = simd_oprsz(desc) / 8; + uint64_t *d = vd, *n = vn; + uint8_t *pg = vg; + for (i = 0; i < opr_sz; i += 1) { + d[i] = n[1] & -(uint64_t)(pg[H1(i)] & 1); + } +} + /* Three-operand expander, immediate operand, controlled by a predicate. */ #define DO_ZPZI(NAME, TYPE, H, OP) \ diff --git a/qemu/target/arm/translate-sve.c b/qemu/target/arm/translate-sve.c index d117163d..fd76b014 100644 --- a/qemu/target/arm/translate-sve.c +++ b/qemu/target/arm/translate-sve.c @@ -615,6 +615,21 @@ static bool do_clr_zp(DisasContext *s, int rd, int pg, int esz) return true; } +/* Copy Zn into Zd, storing zeros into inactive elements. */ +static void do_movz_zpz(DisasContext *s, int rd, int rn, int pg, int esz) +{ + static gen_helper_gvec_3 * const fns[4] = { + gen_helper_sve_movz_b, gen_helper_sve_movz_h, + gen_helper_sve_movz_s, gen_helper_sve_movz_d, + }; + TCGContext *tcg_ctx = s->uc->tcg_ctx; + unsigned vsz = vec_full_reg_size(s); + tcg_gen_gvec_3_ool(tcg_ctx, vec_full_reg_offset(s, rd), + vec_full_reg_offset(s, rn), + pred_full_reg_offset(s, pg), + vsz, vsz, 0, fns[esz]); +} + static bool do_zpzi_ool(DisasContext *s, arg_rpri_esz *a, gen_helper_gvec_3 *fn) { @@ -4154,6 +4169,55 @@ static bool trans_LD1RQ_zpri(DisasContext *s, arg_rpri_load *a, uint32_t insn) return true; } +/* Load and broadcast element. */ +static bool trans_LD1R_zpri(DisasContext *s, arg_rpri_load *a, uint32_t insn) +{ + if (!sve_access_check(s)) { + return true; + } + + TCGContext *tcg_ctx = s->uc->tcg_ctx; + unsigned vsz = vec_full_reg_size(s); + unsigned psz = pred_full_reg_size(s); + unsigned esz = dtype_esz[a->dtype]; + TCGLabel *over = gen_new_label(tcg_ctx); + TCGv_i64 temp; + + /* If the guarding predicate has no bits set, no load occurs. */ + if (psz <= 8) { + /* Reduce the pred_esz_masks value simply to reduce the + * size of the code generated here. + */ + uint64_t psz_mask = MAKE_64BIT_MASK(0, psz * 8); + temp = tcg_temp_new_i64(tcg_ctx); + tcg_gen_ld_i64(tcg_ctx, temp, tcg_ctx->cpu_env, pred_full_reg_offset(s, a->pg)); + tcg_gen_andi_i64(tcg_ctx, temp, temp, pred_esz_masks[esz] & psz_mask); + tcg_gen_brcondi_i64(tcg_ctx, TCG_COND_EQ, temp, 0, over); + tcg_temp_free_i64(tcg_ctx, temp); + } else { + TCGv_i32 t32 = tcg_temp_new_i32(tcg_ctx); + find_last_active(s, t32, esz, a->pg); + tcg_gen_brcondi_i32(tcg_ctx, TCG_COND_LT, t32, 0, over); + tcg_temp_free_i32(tcg_ctx, t32); + } + + /* Load the data. */ + temp = tcg_temp_new_i64(tcg_ctx); + tcg_gen_addi_i64(tcg_ctx, temp, cpu_reg_sp(s, a->rn), a->imm << esz); + tcg_gen_qemu_ld_i64(s->uc, temp, temp, get_mem_index(s), + s->be_data | dtype_mop[a->dtype]); + + /* Broadcast to *all* elements. */ + tcg_gen_gvec_dup_i64(tcg_ctx, esz, vec_full_reg_offset(s, a->rd), + vsz, vsz, temp); + tcg_temp_free_i64(tcg_ctx, temp); + + /* Zero the inactive elements. */ + gen_set_label(tcg_ctx, over); + do_movz_zpz(s, a->rd, a->rd, a->pg, esz); + return true; +} + static void do_st_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr, int msz, int esz, int nreg) {