From c5b8a6a704501a963baf017a15b0ff4fe748d1db Mon Sep 17 00:00:00 2001
From: Babu Moger <babu.moger@amd.com>
Date: Thu, 17 May 2018 18:56:05 -0400
Subject: [PATCH] i386: Add cache information in X86CPUDefinition

Add cache information in X86CPUDefinition and CPUX86State.

Backports commit 6aaeb05492ef668f415324f43e7d875c0f1e90b3 from qemu
---
 qemu/target/i386/cpu.c | 1 +
 qemu/target/i386/cpu.h | 8 ++++++++
 2 files changed, 9 insertions(+)

diff --git a/qemu/target/i386/cpu.c b/qemu/target/i386/cpu.c
index 6addc127..6e17e00f 100644
--- a/qemu/target/i386/cpu.c
+++ b/qemu/target/i386/cpu.c
@@ -1239,6 +1239,7 @@ struct X86CPUDefinition {
     FeatureWordArray features;
     const char *model_id;
     bool cache_info_passthrough;
+    CPUCaches *cache_info;
 };
 
 static X86CPUDefinition builtin_x86_defs[] = {
diff --git a/qemu/target/i386/cpu.h b/qemu/target/i386/cpu.h
index e2d73001..18155969 100644
--- a/qemu/target/i386/cpu.h
+++ b/qemu/target/i386/cpu.h
@@ -1053,6 +1053,13 @@ typedef struct CPUCacheInfo {
     bool complex_indexing;
 } CPUCacheInfo;
 
+typedef struct CPUCaches {
+        CPUCacheInfo l1d_cache;
+        CPUCacheInfo l1i_cache;
+        CPUCacheInfo l2_cache;
+        CPUCacheInfo l3_cache;
+} CPUCaches;
+
 typedef struct CPUX86State {
     /* standard registers */
     target_ulong regs[CPU_NB_REGS];
@@ -1227,6 +1234,7 @@ typedef struct CPUX86State {
     /* Features that were explicitly enabled/disabled */
     FeatureWordArray user_features;
     uint32_t cpuid_model[12];
+    CPUCaches *cache_info;
 
     /* MTRRs */
     uint64_t mtrr_fixed[11];