From c5c44f3a8a50e72b9fb5f821aec527b8f4400e05 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Fri, 16 Feb 2018 16:00:10 -0500 Subject: [PATCH] target-i386: allow any alignment for SMBASE Processors up to the Pentium (says Bochs---I do not have old enough manuals) require a 32KiB alignment for the SMBASE, but newer processors do not need that, and Tiano Core will use non-aligned SMBASE values. Backports commit dd75d4fcb4a82c34d4f466e7fc166162b71ff740 from qemu --- qemu/target-i386/smm_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qemu/target-i386/smm_helper.c b/qemu/target-i386/smm_helper.c index 5617a148..94736433 100644 --- a/qemu/target-i386/smm_helper.c +++ b/qemu/target-i386/smm_helper.c @@ -256,7 +256,7 @@ void helper_rsm(CPUX86State *env) val = x86_ldl_phys(cs, sm_state + 0x7efc); /* revision ID */ if (val & 0x20000) { - env->smbase = x86_ldl_phys(cs, sm_state + 0x7f00) & ~0x7fff; + env->smbase = x86_ldl_phys(cs, sm_state + 0x7f00); } #else cpu_x86_update_cr0(env, x86_ldl_phys(cs, sm_state + 0x7ffc)); @@ -309,7 +309,7 @@ void helper_rsm(CPUX86State *env) val = x86_ldl_phys(cs, sm_state + 0x7efc); /* revision ID */ if (val & 0x20000) { - env->smbase = x86_ldl_phys(cs, sm_state + 0x7ef8) & ~0x7fff; + env->smbase = x86_ldl_phys(cs, sm_state + 0x7ef8); } #endif if ((env->hflags2 & HF2_SMM_INSIDE_NMI_MASK) == 0) {