From c8a49d8593aba701c06cffd6b17ed2b7f907c12d Mon Sep 17 00:00:00 2001 From: Robert Hoo Date: Thu, 7 Feb 2019 08:56:30 -0500 Subject: [PATCH] Revert "i386: Add CPUID bit for PCONFIG" This reverts commit 5131dc433df54b37e8e918d8fba7fe10344e7a7b. For new instruction 'PCONFIG' will not be exposed to guest. Backports commit 712f807e1965c8f1f1da5bbec2b92a8c540e6631 from qemu --- qemu/target/i386/cpu.c | 2 +- qemu/target/i386/cpu.h | 1 - 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/qemu/target/i386/cpu.c b/qemu/target/i386/cpu.c index ac4aa8d6..c7490ba2 100644 --- a/qemu/target/i386/cpu.c +++ b/qemu/target/i386/cpu.c @@ -881,7 +881,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, - NULL, NULL, "pconfig", NULL, + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "spec-ctrl", "stibp", NULL, "arch-capabilities", NULL, "ssbd", diff --git a/qemu/target/i386/cpu.h b/qemu/target/i386/cpu.h index 2e59e10e..25184090 100644 --- a/qemu/target/i386/cpu.h +++ b/qemu/target/i386/cpu.h @@ -672,7 +672,6 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */ #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */ -#define CPUID_7_0_EDX_PCONFIG (1U << 18) /* Platform Configuration */ #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) /* Speculation Control */ #define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29) /*Arch Capabilities*/ #define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) /* Speculative Store Bypass Disable */