diff --git a/qemu/aarch64.h b/qemu/aarch64.h index 6b5fe808..dbf193e7 100644 --- a/qemu/aarch64.h +++ b/qemu/aarch64.h @@ -3394,6 +3394,7 @@ #define helper_frecpx_f16 helper_frecpx_f16_aarch64 #define helper_frecpx_f32 helper_frecpx_f32_aarch64 #define helper_frecpx_f64 helper_frecpx_f64_aarch64 +#define helper_fjcvtzs helper_fjcvtzs_aarch64 #define helper_gvec_recps_d helper_gvec_recps_d_aarch64 #define helper_gvec_recps_h helper_gvec_recps_h_aarch64 #define helper_gvec_recps_s helper_gvec_recps_s_aarch64 @@ -4325,6 +4326,7 @@ #define helper_vfp_cmps_a64 helper_vfp_cmps_a64_aarch64 #define helper_vfp_mulxd helper_vfp_mulxd_aarch64 #define helper_vfp_mulxs helper_vfp_mulxs_aarch64 +#define helper_vjcvt helper_vjcvt_aarch64 #define helper_xpacd helper_xpacd_aarch64 #define helper_xpaci helper_xpaci_aarch64 #define logic_imm_decode_wmask logic_imm_decode_wmask_aarch64 diff --git a/qemu/aarch64eb.h b/qemu/aarch64eb.h index 86b8d38a..4475c27e 100644 --- a/qemu/aarch64eb.h +++ b/qemu/aarch64eb.h @@ -3394,6 +3394,7 @@ #define helper_frecpx_f16 helper_frecpx_f16_aarch64eb #define helper_frecpx_f32 helper_frecpx_f32_aarch64eb #define helper_frecpx_f64 helper_frecpx_f64_aarch64eb +#define helper_fjcvtzs helper_fjcvtzs_aarch64eb #define helper_gvec_recps_d helper_gvec_recps_d_aarch64eb #define helper_gvec_recps_h helper_gvec_recps_h_aarch64eb #define helper_gvec_recps_s helper_gvec_recps_s_aarch64eb @@ -4325,6 +4326,7 @@ #define helper_vfp_cmps_a64 helper_vfp_cmps_a64_aarch64eb #define helper_vfp_mulxd helper_vfp_mulxd_aarch64eb #define helper_vfp_mulxs helper_vfp_mulxs_aarch64eb +#define helper_vjcvt helper_vjcvt_aarch64eb #define helper_xpacd helper_xpacd_aarch64eb #define helper_xpaci helper_xpaci_aarch64eb #define logic_imm_decode_wmask logic_imm_decode_wmask_aarch64eb diff --git a/qemu/arm.h b/qemu/arm.h index b1148921..ab051ad7 100644 --- a/qemu/arm.h +++ b/qemu/arm.h @@ -3337,6 +3337,8 @@ #define cmtst_op cmtst_op_arm #define fp_exception_el fp_exception_el_arm #define gen_cmtst_i64 gen_cmtst_i64_arm +#define helper_fjcvtzs helper_fjcvtzs_arm +#define helper_vjcvt helper_vjcvt_arm #define pmu_init pmu_init_arm #define mla_op mla_op_arm #define mls_op mls_op_arm diff --git a/qemu/armeb.h b/qemu/armeb.h index 86a588b8..d0a7cfaf 100644 --- a/qemu/armeb.h +++ b/qemu/armeb.h @@ -3337,6 +3337,8 @@ #define cmtst_op cmtst_op_armeb #define fp_exception_el fp_exception_el_armeb #define gen_cmtst_i64 gen_cmtst_i64_armeb +#define helper_fjcvtzs helper_fjcvtzs_armeb +#define helper_vjcvt helper_vjcvt_armeb #define pmu_init pmu_init_armeb #define mla_op mla_op_armeb #define mls_op mls_op_armeb diff --git a/qemu/header_gen.py b/qemu/header_gen.py index cfcd71f8..5699a2a2 100644 --- a/qemu/header_gen.py +++ b/qemu/header_gen.py @@ -3346,6 +3346,8 @@ arm_symbols = ( 'cmtst_op', 'fp_exception_el', 'gen_cmtst_i64', + 'helper_fjcvtzs', + 'helper_vjcvt', 'pmu_init', 'mla_op', 'mls_op', @@ -3444,6 +3446,7 @@ aarch64_symbols = ( 'helper_frecpx_f16', 'helper_frecpx_f32', 'helper_frecpx_f64', + 'helper_fjcvtzs', 'helper_gvec_recps_d', 'helper_gvec_recps_h', 'helper_gvec_recps_s', @@ -4375,6 +4378,7 @@ aarch64_symbols = ( 'helper_vfp_cmps_a64', 'helper_vfp_mulxd', 'helper_vfp_mulxs', + 'helper_vjcvt', 'helper_xpacd', 'helper_xpaci', 'logic_imm_decode_wmask', diff --git a/qemu/target/arm/cpu.c b/qemu/target/arm/cpu.c index a667572e..17d987ac 100644 --- a/qemu/target/arm/cpu.c +++ b/qemu/target/arm/cpu.c @@ -1710,6 +1710,7 @@ static void arm_max_initfn(struct uc_struct *uc, Object *obj, void *opaque) cpu->isar.id_isar5 = t; t = cpu->isar.id_isar6; + t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); t = FIELD_DP32(t, ID_ISAR6, DP, 1); cpu->isar.id_isar6 = t; diff --git a/qemu/target/arm/cpu.h b/qemu/target/arm/cpu.h index 6618bccc..8ee8ed69 100644 --- a/qemu/target/arm/cpu.h +++ b/qemu/target/arm/cpu.h @@ -3247,6 +3247,11 @@ static inline bool isar_feature_aa32_vcma(const ARMISARegisters *id) return FIELD_EX32(id->id_isar5, ID_ISAR5, VCMA) != 0; } +static inline bool isar_feature_aa32_jscvt(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_isar6, ID_ISAR6, JSCVT) != 0; +} + static inline bool isar_feature_aa32_dp(const ARMISARegisters *id) { return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) != 0; @@ -3325,6 +3330,11 @@ static inline bool isar_feature_aa64_dp(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) != 0; } +static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0; +} + static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0; diff --git a/qemu/target/arm/cpu64.c b/qemu/target/arm/cpu64.c index 1ea0b347..91fde9c4 100644 --- a/qemu/target/arm/cpu64.c +++ b/qemu/target/arm/cpu64.c @@ -256,6 +256,7 @@ static void aarch64_max_initfn(struct uc_struct *uc, Object *obj, void *opaque) cpu->isar.id_aa64isar0 = t; t = cpu->isar.id_aa64isar1; + t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); t = FIELD_DP64(t, ID_AA64ISAR1, APA, 1); /* PAuth, architected only */ t = FIELD_DP64(t, ID_AA64ISAR1, API, 0); @@ -289,6 +290,7 @@ static void aarch64_max_initfn(struct uc_struct *uc, Object *obj, void *opaque) cpu->isar.id_isar5 = u; u = cpu->isar.id_isar6; + u = FIELD_DP32(u, ID_ISAR6, JSCVT, 1); u = FIELD_DP32(u, ID_ISAR6, DP, 1); cpu->isar.id_isar6 = u; diff --git a/qemu/target/arm/helper.h b/qemu/target/arm/helper.h index 71a09827..44dbf8d6 100644 --- a/qemu/target/arm/helper.h +++ b/qemu/target/arm/helper.h @@ -220,6 +220,9 @@ DEF_HELPER_FLAGS_2(rintd_exact, TCG_CALL_NO_RWG, f64, f64, ptr) DEF_HELPER_FLAGS_2(rints, TCG_CALL_NO_RWG, f32, f32, ptr) DEF_HELPER_FLAGS_2(rintd, TCG_CALL_NO_RWG, f64, f64, ptr) +DEF_HELPER_FLAGS_2(vjcvt, TCG_CALL_NO_RWG, i32, f64, env) +DEF_HELPER_FLAGS_2(fjcvtzs, TCG_CALL_NO_RWG, i64, f64, ptr) + /* neon_helper.c */ DEF_HELPER_FLAGS_3(neon_qadd_u8, TCG_CALL_NO_RWG, i32, env, i32, i32) DEF_HELPER_FLAGS_3(neon_qadd_s8, TCG_CALL_NO_RWG, i32, env, i32, i32) diff --git a/qemu/target/arm/translate-a64.c b/qemu/target/arm/translate-a64.c index 1b342ddf..c67766d7 100644 --- a/qemu/target/arm/translate-a64.c +++ b/qemu/target/arm/translate-a64.c @@ -6644,6 +6644,25 @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof) } } +static void handle_fjcvtzs(DisasContext *s, int rd, int rn) +{ + TCGContext *tcg_ctx = s->uc->tcg_ctx; + TCGv_i64 t = read_fp_dreg(s, rn); + TCGv_ptr fpstatus = get_fpstatus_ptr(s, false); + + gen_helper_fjcvtzs(tcg_ctx, t, t, fpstatus); + + tcg_temp_free_ptr(tcg_ctx, fpstatus); + + tcg_gen_ext32u_i64(tcg_ctx, cpu_reg(s, rd), t); + tcg_gen_extrh_i64_i32(tcg_ctx, tcg_ctx->cpu_ZF, t); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_CF, 0); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_NF, 0); + tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_VF, 0); + + tcg_temp_free_i64(tcg_ctx, t); +} + /* Floating point <-> integer conversions * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+ @@ -6719,6 +6738,14 @@ static void disas_fp_int_conv(DisasContext *s, uint32_t insn) handle_fmov(s, rd, rn, type, itof); break; + case 0x3E: /* FJCVTZS */ + if (!dc_isar_feature(aa64_jscvt, s)) { + goto do_unallocated; + } else if (fp_access_check(s)) { + handle_fjcvtzs(s, rd, rn); + } + break; + default: do_unallocated: unallocated_encoding(s); diff --git a/qemu/target/arm/translate.c b/qemu/target/arm/translate.c index 103aab50..551fc4c4 100644 --- a/qemu/target/arm/translate.c +++ b/qemu/target/arm/translate.c @@ -3840,6 +3840,13 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn) rm_is_dp = false; break; + case 0x13: /* vjcvt */ + if (!dp || !dc_isar_feature(aa32_jscvt, s)) { + return 1; + } + rd_is_dp = false; + break; + default: return 1; } @@ -4210,6 +4217,9 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn) case 17: /* fsito */ gen_vfp_sito(s, dp, 0); break; + case 19: /* vjcvt */ + gen_helper_vjcvt(tcg_ctx, s->F0s, s->F0d, tcg_ctx->cpu_env); + break; case 20: /* fshto */ gen_vfp_shto(s, dp, 16 - rm, 0); break; diff --git a/qemu/target/arm/vfp_helper.c b/qemu/target/arm/vfp_helper.c index f438c2bc..2dc9283c 100644 --- a/qemu/target/arm/vfp_helper.c +++ b/qemu/target/arm/vfp_helper.c @@ -1088,3 +1088,91 @@ int arm_rmode_to_sf(int rmode) } return rmode; } + +/* + * Implement float64 to int32_t conversion without saturation; + * the result is supplied modulo 2^32. + */ +uint64_t HELPER(fjcvtzs)(float64 value, void *vstatus) +{ + float_status *status = vstatus; + uint32_t exp, sign; + uint64_t frac; + uint32_t inexact = 1; /* !Z */ + + sign = extract64(value, 63, 1); + exp = extract64(value, 52, 11); + frac = extract64(value, 0, 52); + + if (exp == 0) { + /* While not inexact for IEEE FP, -0.0 is inexact for JavaScript. */ + inexact = sign; + if (frac != 0) { + if (status->flush_inputs_to_zero) { + float_raise(float_flag_input_denormal, status); + } else { + float_raise(float_flag_inexact, status); + inexact = 1; + } + } + frac = 0; + } else if (exp == 0x7ff) { + /* This operation raises Invalid for both NaN and overflow (Inf). */ + float_raise(float_flag_invalid, status); + frac = 0; + } else { + int true_exp = exp - 1023; + int shift = true_exp - 52; + + /* Restore implicit bit. */ + frac |= 1ull << 52; + + /* Shift the fraction into place. */ + if (shift >= 0) { + /* The number is so large we must shift the fraction left. */ + if (shift >= 64) { + /* The fraction is shifted out entirely. */ + frac = 0; + } else { + frac <<= shift; + } + } else if (shift > -64) { + /* Normal case -- shift right and notice if bits shift out. */ + inexact = (frac << (64 + shift)) != 0; + frac >>= -shift; + } else { + /* The fraction is shifted out entirely. */ + frac = 0; + } + + /* Notice overflow or inexact exceptions. */ + if (true_exp > 31 || frac > (sign ? 0x80000000ull : 0x7fffffff)) { + /* Overflow, for which this operation raises invalid. */ + float_raise(float_flag_invalid, status); + inexact = 1; + } else if (inexact) { + float_raise(float_flag_inexact, status); + } + + /* Honor the sign. */ + if (sign) { + frac = -frac; + } + } + + /* Pack the result and the env->ZF representation of Z together. */ + return deposit64(frac, 32, 32, inexact); +} + +uint32_t HELPER(vjcvt)(float64 value, CPUARMState *env) +{ + uint64_t pair = HELPER(fjcvtzs)(value, &env->vfp.fp_status); + uint32_t result = pair; + uint32_t z = (pair >> 32) == 0; + + /* Store Z, clear NCV, in FPSCR.NZCV. */ + env->vfp.xregs[ARM_VFP_FPSCR] + = (env->vfp.xregs[ARM_VFP_FPSCR] & ~CPSR_NZCV) | (z * CPSR_Z); + + return result; +}