From c9bdf5e6c7b65608ee8e19a1674faf2488a1eb0d Mon Sep 17 00:00:00 2001 From: Wei Huang <wei@redhat.com> Date: Fri, 2 Mar 2018 07:58:46 -0500 Subject: [PATCH] target-arm: Enable vPMU support under TCG mode This patch contains several fixes to enable vPMU under TCG mode. It first removes the checking of kvm_enabled() while unsetting ARM_FEATURE_PMU. With it, the .pmu option can be used to turn on/off vPMU under TCG mode. Secondly the PMU node of DT table is now created under TCG. The last fix is to disable the masking of PMUver field of ID_AA64DFR0_EL1. Backports commit d6f02ce3b8a43ddd8f83553fe754a34b26fb273f from qemu --- qemu/target/arm/helper.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/qemu/target/arm/helper.c b/qemu/target/arm/helper.c index 4e8d6322..1e602036 100644 --- a/qemu/target/arm/helper.c +++ b/qemu/target/arm/helper.c @@ -4036,13 +4036,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) { "ID_AA64PFR7_EL1_RESERVED", 0,0,4, 3,0,7, ARM_CP_STATE_AA64, ARM_CP_CONST, PL1_R, 0, NULL, 0 }, { "ID_AA64DFR0_EL1", 0,0,5, 3,0,0, ARM_CP_STATE_AA64, - ARM_CP_CONST, PL1_R, 0, NULL, - /* We mask out the PMUVer field, because we don't currently - * implement the PMU. Not advertising it prevents the guest - * from trying to use it and getting UNDEFs on registers we - * don't implement. - */ - cpu->id_aa64dfr0 & ~0xf00 }, + ARM_CP_CONST, PL1_R, 0, NULL, cpu->id_aa64dfr0 }, { "ID_AA64DFR1_EL1", 0,0,5, 3,0,1, ARM_CP_STATE_AA64, ARM_CP_CONST, PL1_R, 0, NULL, cpu->id_aa64dfr1 }, { "ID_AA64DFR2_EL1_RESERVED", 0,0,5, 3,0,2, ARM_CP_STATE_AA64, ARM_CP_CONST,