From c9ee9a2729a9e14e0c6402b8a681037833c56566 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Thu, 30 Apr 2020 06:54:38 -0400 Subject: [PATCH] target/arm: Move computation of index in handle_simd_dupe Coverity reports a BAD_SHIFT with ctz32(imm5), with imm5 == 0. This is an invalid encoding, but we diagnose that just below by rejecting size > 3. Avoid the warning by sinking the computation of index below the check. Backports commit 550a04893c2bd4442211b353680b9a6408d94dba from qemu --- qemu/target/arm/translate-a64.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/qemu/target/arm/translate-a64.c b/qemu/target/arm/translate-a64.c index 7d308e41..3e3263b1 100644 --- a/qemu/target/arm/translate-a64.c +++ b/qemu/target/arm/translate-a64.c @@ -7683,7 +7683,7 @@ static void handle_simd_dupe(DisasContext *s, int is_q, int rd, int rn, { TCGContext *tcg_ctx = s->uc->tcg_ctx; int size = ctz32(imm5); - int index = imm5 >> (size + 1); + int index; if (size > 3 || (size == 3 && !is_q)) { unallocated_encoding(s); @@ -7694,6 +7694,7 @@ static void handle_simd_dupe(DisasContext *s, int is_q, int rd, int rn, return; } + index = imm5 >> (size + 1); tcg_gen_gvec_dup_mem(tcg_ctx, size, vec_full_reg_offset(s, rd), vec_reg_offset(s, rn, index, size), is_q ? 16 : 8, vec_full_reg_size(s));