diff --git a/qemu/configure b/qemu/configure
index 21630a3a..c9708cbc 100755
--- a/qemu/configure
+++ b/qemu/configure
@@ -1320,6 +1320,7 @@ mkdir -p $target_dir
 echo "# Automatically generated by configure - do not modify" > $config_target_mak
 
 bflt="no"
+mttcg="no"
 
 TARGET_ARCH="$target_name"
 TARGET_BASE_ARCH=""
@@ -1334,12 +1335,14 @@ case "$target_name" in
   ;;
   arm|armeb)
     TARGET_ARCH=arm
+    mttcg="yes"
     bflt="yes"
   ;;
   aarch64|aarch64eb)
     TARGET_BASE_ARCH=arm
     TARGET_ARCH=aarch64
     bflt="yes"
+    mttcg="yes"
   ;;
   cris)
   ;;
@@ -1437,6 +1440,9 @@ if test "$target_bigendian" = "yes" ; then
 fi
 if test "$target_softmmu" = "yes" ; then
   echo "CONFIG_SOFTMMU=y" >> $config_target_mak
+  if test "$mttcg" = "yes" ; then
+    echo "TARGET_SUPPORTS_MTTCG=y" >> $config_target_mak
+  fi
 fi
 
 # generate QEMU_CFLAGS/LDFLAGS for targets
diff --git a/qemu/target/arm/cpu.h b/qemu/target/arm/cpu.h
index b41a89e9..b25af15a 100644
--- a/qemu/target/arm/cpu.h
+++ b/qemu/target/arm/cpu.h
@@ -33,6 +33,9 @@
 
 #define TARGET_IS_BIENDIAN 1
 
+/* ARM processors have a weak memory model */
+#define TCG_GUEST_DEFAULT_MO      (0)
+
 #define CPUArchState struct CPUARMState
 
 #include "qemu-common.h"
diff --git a/qemu/tcg/i386/tcg-target.h b/qemu/tcg/i386/tcg-target.h
index be17bf4f..8a09ed82 100644
--- a/qemu/tcg/i386/tcg-target.h
+++ b/qemu/tcg/i386/tcg-target.h
@@ -165,4 +165,15 @@ static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
 {
 }
 
+/* This defines the natural memory order supported by this
+ * architecture before guarantees made by various barrier
+ * instructions.
+ *
+ * The x86 has a pretty strong memory ordering which only really
+ * allows for some stores to be re-ordered after loads.
+ */
+#include "tcg-mo.h"
+
+#define TCG_TARGET_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD)
+
 #endif