From caee2d2ddae796003343fe7d8ad25afb94c8f6bb Mon Sep 17 00:00:00 2001 From: Laurent Vivier Date: Tue, 6 Mar 2018 11:17:34 -0500 Subject: [PATCH] target/m68k: add moves and introduce SFC and DFC control registers. Backports commit 5fa9f1f28321f7268e68e58cff8c61a2ab817f91 from qemu --- qemu/target/m68k/cpu.h | 19 ++++++++-- qemu/target/m68k/helper.c | 10 ++++++ qemu/target/m68k/op_helper.c | 4 +-- qemu/target/m68k/translate.c | 70 ++++++++++++++++++++++++++++++++++-- 4 files changed, 96 insertions(+), 7 deletions(-) diff --git a/qemu/target/m68k/cpu.h b/qemu/target/m68k/cpu.h index c5ada081..4a21682a 100644 --- a/qemu/target/m68k/cpu.h +++ b/qemu/target/m68k/cpu.h @@ -140,6 +140,8 @@ typedef struct CPUM68KState { uint32_t mbar; uint32_t rambar0; uint32_t cacr; + uint32_t sfc; + uint32_t dfc; int pending_vector; int pending_level; @@ -546,13 +548,26 @@ void m68k_cpu_unassigned_access(CPUState *cs, hwaddr addr, #include "exec/cpu-all.h" +/* TB flags */ +#define TB_FLAGS_MACSR 0x0f +#define TB_FLAGS_MSR_S_BIT 13 +#define TB_FLAGS_MSR_S (1 << TB_FLAGS_MSR_S_BIT) +#define TB_FLAGS_SFC_S_BIT 14 +#define TB_FLAGS_SFC_S (1 << TB_FLAGS_SFC_S_BIT) +#define TB_FLAGS_DFC_S_BIT 15 +#define TB_FLAGS_DFC_S (1 << TB_FLAGS_DFC_S_BIT) + static inline void cpu_get_tb_cpu_state(CPUM68KState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *flags) { *pc = env->pc; *cs_base = 0; - *flags = (env->sr & SR_S) /* Bit 13 */ - | ((env->macsr >> 4) & 0xf); /* Bits 0-3 */ + *flags = (env->macsr >> 4) & TB_FLAGS_MACSR; + if (env->sr & SR_S) { + *flags |= TB_FLAGS_MSR_S; + *flags |= (env->sfc << (TB_FLAGS_SFC_S_BIT - 2)) & TB_FLAGS_SFC_S; + *flags |= (env->dfc << (TB_FLAGS_DFC_S_BIT - 2)) & TB_FLAGS_DFC_S; + } } #endif diff --git a/qemu/target/m68k/helper.c b/qemu/target/m68k/helper.c index b7705978..e274529a 100644 --- a/qemu/target/m68k/helper.c +++ b/qemu/target/m68k/helper.c @@ -78,6 +78,12 @@ void HELPER(m68k_movec_to)(CPUM68KState *env, uint32_t reg, uint32_t val) switch (reg) { /* MC680[1234]0 */ + case M68K_CR_SFC: + env->sfc = val & 7; + return; + case M68K_CR_DFC: + env->dfc = val & 7; + return; case M68K_CR_VBR: env->vbr = val; return; @@ -129,6 +135,10 @@ uint32_t HELPER(m68k_movec_from)(CPUM68KState *env, uint32_t reg) switch (reg) { /* MC680[1234]0 */ + case M68K_CR_SFC: + return env->sfc; + case M68K_CR_DFC: + return env->dfc; case M68K_CR_VBR: return env->vbr; /* MC680[234]0 */ diff --git a/qemu/target/m68k/op_helper.c b/qemu/target/m68k/op_helper.c index 0ad2a745..95ce9bb6 100644 --- a/qemu/target/m68k/op_helper.c +++ b/qemu/target/m68k/op_helper.c @@ -408,8 +408,8 @@ static void m68k_interrupt_all(CPUM68KState *env, int is_hw) env->mmu.fault = false; if (qemu_loglevel_mask(CPU_LOG_INT)) { qemu_log(" " - "ssw: %08x ea: %08x\n", - env->mmu.ssw, env->mmu.ar); + "ssw: %08x ea: %08x sfc: %d dfc: %d\n", + env->mmu.ssw, env->mmu.ar, env->sfc, env->dfc); } } else if (cs->exception_index == EXCP_ADDRESS) { do_stack_frame(env, &sp, 2, oldsr, 0, retaddr); diff --git a/qemu/target/m68k/translate.c b/qemu/target/m68k/translate.c index 3d7f76bb..1d6ed163 100644 --- a/qemu/target/m68k/translate.c +++ b/qemu/target/m68k/translate.c @@ -96,7 +96,6 @@ typedef struct DisasContext { int is_jmp; CCOp cc_op; /* Current CC operation */ int cc_op_synced; - int user; struct TranslationBlock *tb; int singlestep_enabled; TCGv_i64 mactmp; @@ -168,7 +167,11 @@ static void do_writebacks(DisasContext *s) #if defined(CONFIG_USER_ONLY) #define IS_USER(s) 1 #else -#define IS_USER(s) s->user +#define IS_USER(s) (!(s->tb->flags & TB_FLAGS_MSR_S)) +#define SFC_INDEX(s) ((s->tb->flags & TB_FLAGS_SFC_S) ? \ + MMU_KERNEL_IDX : MMU_USER_IDX) +#define DFC_INDEX(s) ((s->tb->flags & TB_FLAGS_DFC_S) ? \ + MMU_KERNEL_IDX : MMU_USER_IDX) #endif typedef void (*disas_proc)(CPUM68KState *env, DisasContext *s, uint16_t insn); @@ -4632,6 +4635,65 @@ DISAS_INSN(move_from_sr) } #if defined(CONFIG_SOFTMMU) +DISAS_INSN(moves) +{ + TCGContext *tcg_ctx = s->uc->tcg_ctx; + int opsize; + uint16_t ext; + TCGv reg; + TCGv addr; + int extend; + + if (IS_USER(s)) { + gen_exception(s, s->insn_pc, EXCP_PRIVILEGE); + return; + } + + ext = read_im16(env, s); + + opsize = insn_opsize(insn); + + if (ext & 0x8000) { + /* address register */ + reg = AREG(ext, 12); + extend = 1; + } else { + /* data register */ + reg = DREG(ext, 12); + extend = 0; + } + + addr = gen_lea(env, s, insn, opsize); + if (IS_NULL_QREG(addr)) { + gen_addr_fault(s); + return; + } + + if (ext & 0x0800) { + /* from reg to ea */ + gen_store(s, opsize, addr, reg, DFC_INDEX(s)); + } else { + /* from ea to reg */ + TCGv tmp = gen_load(s, opsize, addr, 0, SFC_INDEX(s)); + if (extend) { + gen_ext(s, reg, tmp, opsize, 1); + } else { + gen_partset_reg(s, opsize, reg, tmp); + } + } + switch (extract32(insn, 3, 3)) { + case 3: /* Indirect postincrement. */ + tcg_gen_addi_i32(tcg_ctx, AREG(insn, 0), addr, + REG(insn, 0) == 7 && opsize == OS_BYTE + ? 2 + : opsize_bytes(opsize)); + break; + case 4: /* Indirect predecrememnt. */ + tcg_gen_mov_i32(tcg_ctx, AREG(insn, 0), addr); + break; + } +} + DISAS_INSN(move_to_sr) { if (IS_USER(s)) { @@ -5825,6 +5887,9 @@ void register_m68k_insns (CPUM68KState *env) BASE(bitop_im, 08c0, ffc0); INSN(arith_im, 0a80, fff8, CF_ISA_A); INSN(arith_im, 0a00, ff00, M68000); +#if defined(CONFIG_SOFTMMU) + INSN(moves, 0e00, ff00, M68000); +#endif INSN(cas, 0ac0, ffc0, CAS); INSN(cas, 0cc0, ffc0, CAS); INSN(cas, 0ec0, ffc0, CAS); @@ -6067,7 +6132,6 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) dc->cc_op = CC_OP_DYNAMIC; dc->cc_op_synced = 1; dc->singlestep_enabled = cs->singlestep_enabled; - dc->user = (env->sr & SR_S) == 0; dc->done_mac = 0; dc->writeback_mask = 0; num_insns = 0;