diff --git a/include/uc_priv.h b/include/uc_priv.h
index bd8f2ca0..c6cd2255 100644
--- a/include/uc_priv.h
+++ b/include/uc_priv.h
@@ -228,6 +228,7 @@ struct uc_struct {
     void *tcg_ctxs;         // actually "TCGContext **tcg_ctxs"
     unsigned int n_tcg_ctxs;
     struct tcg_region_state region;
+    void *cpu_env;          // actually "TCGv_env cpu_env"
 
     /* memory.c */
     unsigned memory_region_transaction_depth;
diff --git a/qemu/aarch64.h b/qemu/aarch64.h
index 2bb7ce26..5a9f1113 100644
--- a/qemu/aarch64.h
+++ b/qemu/aarch64.h
@@ -2799,8 +2799,6 @@
 #define tcg_global_mem_new_i32 tcg_global_mem_new_i32_aarch64
 #define tcg_global_mem_new_i64 tcg_global_mem_new_i64_aarch64
 #define tcg_global_mem_new_internal tcg_global_mem_new_internal_aarch64
-#define tcg_global_reg_new_i32 tcg_global_reg_new_i32_aarch64
-#define tcg_global_reg_new_i64 tcg_global_reg_new_i64_aarch64
 #define tcg_global_reg_new_internal tcg_global_reg_new_internal_aarch64
 #define tcg_handle_interrupt tcg_handle_interrupt_aarch64
 #define tcg_init tcg_init_aarch64
diff --git a/qemu/aarch64eb.h b/qemu/aarch64eb.h
index cebfc7a8..c3929915 100644
--- a/qemu/aarch64eb.h
+++ b/qemu/aarch64eb.h
@@ -2799,8 +2799,6 @@
 #define tcg_global_mem_new_i32 tcg_global_mem_new_i32_aarch64eb
 #define tcg_global_mem_new_i64 tcg_global_mem_new_i64_aarch64eb
 #define tcg_global_mem_new_internal tcg_global_mem_new_internal_aarch64eb
-#define tcg_global_reg_new_i32 tcg_global_reg_new_i32_aarch64eb
-#define tcg_global_reg_new_i64 tcg_global_reg_new_i64_aarch64eb
 #define tcg_global_reg_new_internal tcg_global_reg_new_internal_aarch64eb
 #define tcg_handle_interrupt tcg_handle_interrupt_aarch64eb
 #define tcg_init tcg_init_aarch64eb
diff --git a/qemu/arm.h b/qemu/arm.h
index 4fa5e15b..025d8332 100644
--- a/qemu/arm.h
+++ b/qemu/arm.h
@@ -2799,8 +2799,6 @@
 #define tcg_global_mem_new_i32 tcg_global_mem_new_i32_arm
 #define tcg_global_mem_new_i64 tcg_global_mem_new_i64_arm
 #define tcg_global_mem_new_internal tcg_global_mem_new_internal_arm
-#define tcg_global_reg_new_i32 tcg_global_reg_new_i32_arm
-#define tcg_global_reg_new_i64 tcg_global_reg_new_i64_arm
 #define tcg_global_reg_new_internal tcg_global_reg_new_internal_arm
 #define tcg_handle_interrupt tcg_handle_interrupt_arm
 #define tcg_init tcg_init_arm
diff --git a/qemu/armeb.h b/qemu/armeb.h
index 6ebac398..d01f081d 100644
--- a/qemu/armeb.h
+++ b/qemu/armeb.h
@@ -2799,8 +2799,6 @@
 #define tcg_global_mem_new_i32 tcg_global_mem_new_i32_armeb
 #define tcg_global_mem_new_i64 tcg_global_mem_new_i64_armeb
 #define tcg_global_mem_new_internal tcg_global_mem_new_internal_armeb
-#define tcg_global_reg_new_i32 tcg_global_reg_new_i32_armeb
-#define tcg_global_reg_new_i64 tcg_global_reg_new_i64_armeb
 #define tcg_global_reg_new_internal tcg_global_reg_new_internal_armeb
 #define tcg_handle_interrupt tcg_handle_interrupt_armeb
 #define tcg_init tcg_init_armeb
diff --git a/qemu/header_gen.py b/qemu/header_gen.py
index 7ba28009..c7a75e61 100644
--- a/qemu/header_gen.py
+++ b/qemu/header_gen.py
@@ -2805,8 +2805,6 @@ symbols = (
     'tcg_global_mem_new_i32',
     'tcg_global_mem_new_i64',
     'tcg_global_mem_new_internal',
-    'tcg_global_reg_new_i32',
-    'tcg_global_reg_new_i64',
     'tcg_global_reg_new_internal',
     'tcg_handle_interrupt',
     'tcg_init',
diff --git a/qemu/include/exec/gen-icount.h b/qemu/include/exec/gen-icount.h
index 5bc68cef..cbd7080b 100644
--- a/qemu/include/exec/gen-icount.h
+++ b/qemu/include/exec/gen-icount.h
@@ -16,7 +16,7 @@ static inline void gen_tb_start(TCGContext *tcg_ctx, TranslationBlock *tb)
 
     tcg_ctx->exitreq_label = gen_new_label(tcg_ctx);
     flag = tcg_temp_new_i32(tcg_ctx);
-    tcg_gen_ld_i32(tcg_ctx, flag, tcg_ctx->cpu_env,
+    tcg_gen_ld_i32(tcg_ctx, flag, tcg_ctx->uc->cpu_env,
                    offsetof(CPUState, tcg_exit_req) - ENV_OFFSET);
     tcg_gen_brcondi_i32(tcg_ctx, TCG_COND_NE, flag, 0, tcg_ctx->exitreq_label);
     tcg_temp_free_i32(tcg_ctx, flag);
@@ -28,7 +28,7 @@ static inline void gen_tb_start(TCGContext *tcg_ctx, TranslationBlock *tb)
 
     icount_label = gen_new_label(tcg_ctx);
     count = tcg_temp_local_new_i32(tcg_ctx);
-    tcg_gen_ld_i32(tcg_ctx, count, tcg_ctx->tcg_env,
+    tcg_gen_ld_i32(tcg_ctx, count, tcg_ctx->uc->cpu_env,
                    -ENV_OFFSET + offsetof(CPUState, icount_decr.u32));
     imm = tcg_temp_new_i32(tcg_ctx);
     /* We emit a movi with a dummy immediate argument. Keep the insn index
@@ -41,7 +41,7 @@ static inline void gen_tb_start(TCGContext *tcg_ctx, TranslationBlock *tb)
     tcg_temp_free_i32(tcg_ctx, imm);
 
     tcg_gen_brcondi_i32(tcg_ctx, TCG_COND_LT, count, 0, icount_label);
-    tcg_gen_st16_i32(tcg_ctx, count, tcg_ctx->tcg_env,
+    tcg_gen_st16_i32(tcg_ctx, count, tcg_ctx->uc->cpu_env,
                      -ENV_OFFSET + offsetof(CPUState, icount_decr.u16.low));
     tcg_temp_free_i32(tcg_ctx, count);
 #endif
@@ -67,14 +67,14 @@ static inline void gen_tb_end(TCGContext *tcg_ctx, TranslationBlock *tb, int num
 static inline void gen_io_start(TCGContext *tcg_ctx)
 {
     TCGv_i32 tmp = tcg_const_i32(tcg_ctx, 1);
-    tcg_gen_st_i32(tcg_ctx, tmp, tcg_ctx->tcg_env, -ENV_OFFSET + offsetof(CPUState, can_do_io));
+    tcg_gen_st_i32(tcg_ctx, tmp, tcg_ctx->uc->cpu_env, -ENV_OFFSET + offsetof(CPUState, can_do_io));
     tcg_temp_free_i32(tcg_ctx, tmp);
 }
 
 static inline void gen_io_end(TCGContext *tcg_ctx)
 {
     TCGv_i32 tmp = tcg_const_i32(tcg_ctx, 0);
-    tcg_gen_st_i32(tcg_ctx, tmp, tcg_ctx->tcg_env, -ENV_OFFSET + offsetof(CPUState, can_do_io));
+    tcg_gen_st_i32(tcg_ctx, tmp, tcg_ctx->uc->cpu_env, -ENV_OFFSET + offsetof(CPUState, can_do_io));
     tcg_temp_free_i32(tcg_ctx, tmp);
 }
 #endif
diff --git a/qemu/m68k.h b/qemu/m68k.h
index ba6fb2b2..669218f2 100644
--- a/qemu/m68k.h
+++ b/qemu/m68k.h
@@ -2799,8 +2799,6 @@
 #define tcg_global_mem_new_i32 tcg_global_mem_new_i32_m68k
 #define tcg_global_mem_new_i64 tcg_global_mem_new_i64_m68k
 #define tcg_global_mem_new_internal tcg_global_mem_new_internal_m68k
-#define tcg_global_reg_new_i32 tcg_global_reg_new_i32_m68k
-#define tcg_global_reg_new_i64 tcg_global_reg_new_i64_m68k
 #define tcg_global_reg_new_internal tcg_global_reg_new_internal_m68k
 #define tcg_handle_interrupt tcg_handle_interrupt_m68k
 #define tcg_init tcg_init_m68k
diff --git a/qemu/mips.h b/qemu/mips.h
index 5ce86978..6b18ce66 100644
--- a/qemu/mips.h
+++ b/qemu/mips.h
@@ -2799,8 +2799,6 @@
 #define tcg_global_mem_new_i32 tcg_global_mem_new_i32_mips
 #define tcg_global_mem_new_i64 tcg_global_mem_new_i64_mips
 #define tcg_global_mem_new_internal tcg_global_mem_new_internal_mips
-#define tcg_global_reg_new_i32 tcg_global_reg_new_i32_mips
-#define tcg_global_reg_new_i64 tcg_global_reg_new_i64_mips
 #define tcg_global_reg_new_internal tcg_global_reg_new_internal_mips
 #define tcg_handle_interrupt tcg_handle_interrupt_mips
 #define tcg_init tcg_init_mips
diff --git a/qemu/mips64.h b/qemu/mips64.h
index e4a74586..574200d4 100644
--- a/qemu/mips64.h
+++ b/qemu/mips64.h
@@ -2799,8 +2799,6 @@
 #define tcg_global_mem_new_i32 tcg_global_mem_new_i32_mips64
 #define tcg_global_mem_new_i64 tcg_global_mem_new_i64_mips64
 #define tcg_global_mem_new_internal tcg_global_mem_new_internal_mips64
-#define tcg_global_reg_new_i32 tcg_global_reg_new_i32_mips64
-#define tcg_global_reg_new_i64 tcg_global_reg_new_i64_mips64
 #define tcg_global_reg_new_internal tcg_global_reg_new_internal_mips64
 #define tcg_handle_interrupt tcg_handle_interrupt_mips64
 #define tcg_init tcg_init_mips64
diff --git a/qemu/mips64el.h b/qemu/mips64el.h
index c6d0783f..b763bb13 100644
--- a/qemu/mips64el.h
+++ b/qemu/mips64el.h
@@ -2799,8 +2799,6 @@
 #define tcg_global_mem_new_i32 tcg_global_mem_new_i32_mips64el
 #define tcg_global_mem_new_i64 tcg_global_mem_new_i64_mips64el
 #define tcg_global_mem_new_internal tcg_global_mem_new_internal_mips64el
-#define tcg_global_reg_new_i32 tcg_global_reg_new_i32_mips64el
-#define tcg_global_reg_new_i64 tcg_global_reg_new_i64_mips64el
 #define tcg_global_reg_new_internal tcg_global_reg_new_internal_mips64el
 #define tcg_handle_interrupt tcg_handle_interrupt_mips64el
 #define tcg_init tcg_init_mips64el
diff --git a/qemu/mipsel.h b/qemu/mipsel.h
index 126b77a8..3d2bbe3c 100644
--- a/qemu/mipsel.h
+++ b/qemu/mipsel.h
@@ -2799,8 +2799,6 @@
 #define tcg_global_mem_new_i32 tcg_global_mem_new_i32_mipsel
 #define tcg_global_mem_new_i64 tcg_global_mem_new_i64_mipsel
 #define tcg_global_mem_new_internal tcg_global_mem_new_internal_mipsel
-#define tcg_global_reg_new_i32 tcg_global_reg_new_i32_mipsel
-#define tcg_global_reg_new_i64 tcg_global_reg_new_i64_mipsel
 #define tcg_global_reg_new_internal tcg_global_reg_new_internal_mipsel
 #define tcg_handle_interrupt tcg_handle_interrupt_mipsel
 #define tcg_init tcg_init_mipsel
diff --git a/qemu/powerpc.h b/qemu/powerpc.h
index d8d57200..4c7d7ff4 100644
--- a/qemu/powerpc.h
+++ b/qemu/powerpc.h
@@ -2799,8 +2799,6 @@
 #define tcg_global_mem_new_i32 tcg_global_mem_new_i32_powerpc
 #define tcg_global_mem_new_i64 tcg_global_mem_new_i64_powerpc
 #define tcg_global_mem_new_internal tcg_global_mem_new_internal_powerpc
-#define tcg_global_reg_new_i32 tcg_global_reg_new_i32_powerpc
-#define tcg_global_reg_new_i64 tcg_global_reg_new_i64_powerpc
 #define tcg_global_reg_new_internal tcg_global_reg_new_internal_powerpc
 #define tcg_handle_interrupt tcg_handle_interrupt_powerpc
 #define tcg_init tcg_init_powerpc
diff --git a/qemu/sparc.h b/qemu/sparc.h
index b1065ed1..59b80c4e 100644
--- a/qemu/sparc.h
+++ b/qemu/sparc.h
@@ -2799,8 +2799,6 @@
 #define tcg_global_mem_new_i32 tcg_global_mem_new_i32_sparc
 #define tcg_global_mem_new_i64 tcg_global_mem_new_i64_sparc
 #define tcg_global_mem_new_internal tcg_global_mem_new_internal_sparc
-#define tcg_global_reg_new_i32 tcg_global_reg_new_i32_sparc
-#define tcg_global_reg_new_i64 tcg_global_reg_new_i64_sparc
 #define tcg_global_reg_new_internal tcg_global_reg_new_internal_sparc
 #define tcg_handle_interrupt tcg_handle_interrupt_sparc
 #define tcg_init tcg_init_sparc
diff --git a/qemu/sparc64.h b/qemu/sparc64.h
index b39d45cc..6a01e328 100644
--- a/qemu/sparc64.h
+++ b/qemu/sparc64.h
@@ -2799,8 +2799,6 @@
 #define tcg_global_mem_new_i32 tcg_global_mem_new_i32_sparc64
 #define tcg_global_mem_new_i64 tcg_global_mem_new_i64_sparc64
 #define tcg_global_mem_new_internal tcg_global_mem_new_internal_sparc64
-#define tcg_global_reg_new_i32 tcg_global_reg_new_i32_sparc64
-#define tcg_global_reg_new_i64 tcg_global_reg_new_i64_sparc64
 #define tcg_global_reg_new_internal tcg_global_reg_new_internal_sparc64
 #define tcg_handle_interrupt tcg_handle_interrupt_sparc64
 #define tcg_init tcg_init_sparc64
diff --git a/qemu/target/arm/translate-a64.c b/qemu/target/arm/translate-a64.c
index f3f0ac0d..630548a7 100644
--- a/qemu/target/arm/translate-a64.c
+++ b/qemu/target/arm/translate-a64.c
@@ -95,30 +95,30 @@ void a64_translate_init(struct uc_struct *uc)
     TCGContext *tcg_ctx = uc->tcg_ctx;
     int i;
 
-    tcg_ctx->cpu_pc = tcg_global_mem_new_i64(uc->tcg_ctx, tcg_ctx->cpu_env,
+    tcg_ctx->cpu_pc = tcg_global_mem_new_i64(uc->tcg_ctx, uc->cpu_env,
                                     offsetof(CPUARMState, pc),
                                     "pc");
     for (i = 0; i < 32; i++) {
-        tcg_ctx->cpu_X[i] = tcg_global_mem_new_i64(uc->tcg_ctx, tcg_ctx->cpu_env,
+        tcg_ctx->cpu_X[i] = tcg_global_mem_new_i64(uc->tcg_ctx, uc->cpu_env,
                                           offsetof(CPUARMState, xregs[i]),
                                           regnames[i]);
     }
 
-    tcg_ctx->cpu_NF = tcg_global_mem_new_i32(uc->tcg_ctx, tcg_ctx->cpu_env, offsetof(CPUARMState, NF), "NF");
-    tcg_ctx->cpu_ZF = tcg_global_mem_new_i32(uc->tcg_ctx, tcg_ctx->cpu_env, offsetof(CPUARMState, ZF), "ZF");
-    tcg_ctx->cpu_CF = tcg_global_mem_new_i32(uc->tcg_ctx, tcg_ctx->cpu_env, offsetof(CPUARMState, CF), "CF");
-    tcg_ctx->cpu_VF = tcg_global_mem_new_i32(uc->tcg_ctx, tcg_ctx->cpu_env, offsetof(CPUARMState, VF), "VF");
+    tcg_ctx->cpu_NF = tcg_global_mem_new_i32(uc->tcg_ctx, uc->cpu_env, offsetof(CPUARMState, NF), "NF");
+    tcg_ctx->cpu_ZF = tcg_global_mem_new_i32(uc->tcg_ctx, uc->cpu_env, offsetof(CPUARMState, ZF), "ZF");
+    tcg_ctx->cpu_CF = tcg_global_mem_new_i32(uc->tcg_ctx, uc->cpu_env, offsetof(CPUARMState, CF), "CF");
+    tcg_ctx->cpu_VF = tcg_global_mem_new_i32(uc->tcg_ctx, uc->cpu_env, offsetof(CPUARMState, VF), "VF");
 
-    tcg_ctx->cpu_exclusive_addr = tcg_global_mem_new_i64(uc->tcg_ctx, tcg_ctx->cpu_env,
+    tcg_ctx->cpu_exclusive_addr = tcg_global_mem_new_i64(uc->tcg_ctx, uc->cpu_env,
         offsetof(CPUARMState, exclusive_addr), "exclusive_addr");
-    tcg_ctx->cpu_exclusive_val = tcg_global_mem_new_i64(uc->tcg_ctx, tcg_ctx->cpu_env,
+    tcg_ctx->cpu_exclusive_val = tcg_global_mem_new_i64(uc->tcg_ctx, uc->cpu_env,
         offsetof(CPUARMState, exclusive_val), "exclusive_val");
-    tcg_ctx->cpu_exclusive_high = tcg_global_mem_new_i64(uc->tcg_ctx, tcg_ctx->cpu_env,
+    tcg_ctx->cpu_exclusive_high = tcg_global_mem_new_i64(uc->tcg_ctx, uc->cpu_env,
         offsetof(CPUARMState, exclusive_high), "exclusive_high");
 #ifdef CONFIG_USER_ONLY
-    cpu_exclusive_test = tcg_global_mem_new_i64(uc->tcg_ctx, tcg_ctx->cpu_env,
+    cpu_exclusive_test = tcg_global_mem_new_i64(uc->tcg_ctx, uc->cpu_env,
         offsetof(CPUARMState, exclusive_test), "exclusive_test");
-    cpu_exclusive_info = tcg_global_mem_new_i32(uc->tcg_ctx, tcg_ctx->cpu_env,
+    cpu_exclusive_info = tcg_global_mem_new_i32(uc->tcg_ctx, uc->cpu_env,
         offsetof(CPUARMState, exclusive_info), "exclusive_info");
 #endif
 }
@@ -303,22 +303,24 @@ static void a64_free_cc(TCGContext *tcg_ctx, DisasCompare64 *c64)
 
 static void gen_exception_internal(DisasContext *s, int excp)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv_i32 tcg_excp = tcg_const_i32(tcg_ctx, excp);
 
     assert(excp_is_internal(excp));
-    gen_helper_exception_internal(tcg_ctx, tcg_ctx->cpu_env, tcg_excp);
+    gen_helper_exception_internal(tcg_ctx, uc->cpu_env, tcg_excp);
     tcg_temp_free_i32(tcg_ctx, tcg_excp);
 }
 
 static void gen_exception(DisasContext *s, int excp, uint32_t syndrome, uint32_t target_el)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv_i32 tcg_excp = tcg_const_i32(tcg_ctx, excp);
     TCGv_i32 tcg_syn = tcg_const_i32(tcg_ctx, syndrome);
     TCGv_i32 tcg_el = tcg_const_i32(tcg_ctx, target_el);
 
-    gen_helper_exception_with_syndrome(tcg_ctx, tcg_ctx->cpu_env, tcg_excp,
+    gen_helper_exception_with_syndrome(tcg_ctx, uc->cpu_env, tcg_excp,
                                        tcg_syn, tcg_el);
     tcg_temp_free_i32(tcg_ctx, tcg_el);
     tcg_temp_free_i32(tcg_ctx, tcg_syn);
@@ -342,13 +344,14 @@ static void gen_exception_insn(DisasContext *s, int offset, int excp,
 
 static void gen_ss_advance(DisasContext *s)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     /* If the singlestep state is Active-not-pending, advance to
      * Active-pending.
      */
     if (s->ss_active) {
         s->pstate_ss = 0;
-        gen_helper_clear_pstate_ss(tcg_ctx, tcg_ctx->cpu_env);
+        gen_helper_clear_pstate_ss(tcg_ctx, uc->cpu_env);
     }
 }
 
@@ -579,10 +582,11 @@ static inline int vec_full_reg_offset(DisasContext *s, int regno)
 /* Return a newly allocated pointer to the vector register.  */
 static TCGv_ptr vec_full_reg_ptr(DisasContext *s, int regno)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
 
     TCGv_ptr ret = tcg_temp_new_ptr(tcg_ctx);
-    tcg_gen_addi_ptr(tcg_ctx, ret, tcg_ctx->cpu_env, vec_full_reg_offset(s, regno));
+    tcg_gen_addi_ptr(tcg_ctx, ret, uc->cpu_env, vec_full_reg_offset(s, regno));
     return ret;
 }
 
@@ -618,19 +622,21 @@ static inline int fp_reg_hi_offset(DisasContext *s, int regno)
  */
 static TCGv_i64 read_fp_dreg(DisasContext *s, int reg)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv_i64 v = tcg_temp_new_i64(tcg_ctx);
 
-    tcg_gen_ld_i64(tcg_ctx, v, tcg_ctx->cpu_env, fp_reg_offset(s, reg, MO_64));
+    tcg_gen_ld_i64(tcg_ctx, v, uc->cpu_env, fp_reg_offset(s, reg, MO_64));
     return v;
 }
 
 static TCGv_i32 read_fp_sreg(DisasContext *s, int reg)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv_i32 v = tcg_temp_new_i32(tcg_ctx);
 
-    tcg_gen_ld_i32(tcg_ctx, v, tcg_ctx->cpu_env, fp_reg_offset(s, reg, MO_32));
+    tcg_gen_ld_i32(tcg_ctx, v, uc->cpu_env, fp_reg_offset(s, reg, MO_32));
     return v;
 }
 
@@ -639,13 +645,14 @@ static TCGv_i32 read_fp_sreg(DisasContext *s, int reg)
  */
 static void clear_vec_high(DisasContext *s, bool is_q, int rd)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     unsigned ofs = fp_reg_offset(s, rd, MO_64);
     unsigned vsz = vec_full_reg_size(s);
 
     if (!is_q) {
         TCGv_i64 tcg_zero = tcg_const_i64(tcg_ctx, 0);
-        tcg_gen_st_i64(tcg_ctx, tcg_zero, tcg_ctx->cpu_env, ofs + 8);
+        tcg_gen_st_i64(tcg_ctx, tcg_zero, uc->cpu_env, ofs + 8);
         tcg_temp_free_i64(tcg_ctx, tcg_zero);
     }
     if (vsz > 16) {
@@ -655,10 +662,11 @@ static void clear_vec_high(DisasContext *s, bool is_q, int rd)
 
 static void write_fp_dreg(DisasContext *s, int reg, TCGv_i64 v)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     unsigned ofs = fp_reg_offset(s, reg, MO_64);
 
-    tcg_gen_st_i64(tcg_ctx, v, tcg_ctx->cpu_env, ofs);
+    tcg_gen_st_i64(tcg_ctx, v, uc->cpu_env, ofs);
     clear_vec_high(s, false, reg);
 }
 
@@ -687,7 +695,7 @@ static TCGv_ptr get_fpstatus_ptr(TCGContext *tcg_ctx, bool is_f16)
     } else {
         offset = offsetof(CPUARMState, vfp.fp_status);
     }
-    tcg_gen_addi_ptr(tcg_ctx, statusptr, tcg_ctx->cpu_env, offset);
+    tcg_gen_addi_ptr(tcg_ctx, statusptr, tcg_ctx->uc->cpu_env, offset);
     return statusptr;
 }
 
@@ -752,11 +760,12 @@ static void gen_gvec_op3(DisasContext *s, bool is_q, int rd,
 static void gen_gvec_op3_env(DisasContext *s, bool is_q, int rd,
                              int rn, int rm, gen_helper_gvec_3_ptr *fn)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
 
     tcg_gen_gvec_3_ptr(tcg_ctx, vec_full_reg_offset(s, rd),
                        vec_full_reg_offset(s, rn),
-                       vec_full_reg_offset(s, rm), tcg_ctx->cpu_env,
+                       vec_full_reg_offset(s, rm), uc->cpu_env,
                        is_q ? 16 : 8, vec_full_reg_size(s), 0, fn);
 }
 
@@ -1057,21 +1066,23 @@ static void do_gpr_ld(DisasContext *s,
  */
 static void do_fp_st(DisasContext *s, int srcidx, TCGv_i64 tcg_addr, int size)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
+
     /* This writes the bottom N bits of a 128 bit wide vector to memory */
     TCGv_i64 tmp = tcg_temp_new_i64(tcg_ctx);
-    tcg_gen_ld_i64(tcg_ctx, tmp, tcg_ctx->cpu_env, fp_reg_offset(s, srcidx, MO_64));
+    tcg_gen_ld_i64(tcg_ctx, tmp, uc->cpu_env, fp_reg_offset(s, srcidx, MO_64));
     if (size < 4) {
-        tcg_gen_qemu_st_i64(s->uc, tmp, tcg_addr, get_mem_index(s),
+        tcg_gen_qemu_st_i64(uc, tmp, tcg_addr, get_mem_index(s),
                             s->be_data + size);
     } else {
         bool be = s->be_data == MO_BE;
         TCGv_i64 tcg_hiaddr = tcg_temp_new_i64(tcg_ctx);
         tcg_gen_addi_i64(tcg_ctx, tcg_hiaddr, tcg_addr, 8);
-        tcg_gen_qemu_st_i64(s->uc, tmp, be ? tcg_hiaddr : tcg_addr, get_mem_index(s),
+        tcg_gen_qemu_st_i64(uc, tmp, be ? tcg_hiaddr : tcg_addr, get_mem_index(s),
                             s->be_data | MO_Q);
-        tcg_gen_ld_i64(tcg_ctx, tmp, tcg_ctx->cpu_env, fp_reg_hi_offset(s, srcidx));
-        tcg_gen_qemu_st_i64(s->uc, tmp, be ? tcg_addr : tcg_hiaddr, get_mem_index(s),
+        tcg_gen_ld_i64(tcg_ctx, tmp, uc->cpu_env, fp_reg_hi_offset(s, srcidx));
+        tcg_gen_qemu_st_i64(uc, tmp, be ? tcg_addr : tcg_hiaddr, get_mem_index(s),
                             s->be_data | MO_Q);
         tcg_temp_free_i64(tcg_ctx, tcg_hiaddr);
     }
@@ -1084,7 +1095,9 @@ static void do_fp_st(DisasContext *s, int srcidx, TCGv_i64 tcg_addr, int size)
  */
 static void do_fp_ld(DisasContext *s, int destidx, TCGv_i64 tcg_addr, int size)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
+
     /* This always zero-extends and writes to a full 128 bit wide vector */
     TCGv_i64 tmplo = tcg_temp_new_i64(tcg_ctx);
     TCGv_i64 tmphi;
@@ -1092,7 +1105,7 @@ static void do_fp_ld(DisasContext *s, int destidx, TCGv_i64 tcg_addr, int size)
     if (size < 4) {
         TCGMemOp memop = s->be_data + size;
         tmphi = tcg_const_i64(tcg_ctx, 0);
-        tcg_gen_qemu_ld_i64(s->uc, tmplo, tcg_addr, get_mem_index(s), memop);
+        tcg_gen_qemu_ld_i64(uc, tmplo, tcg_addr, get_mem_index(s), memop);
     } else {
         bool be = s->be_data == MO_BE;
         TCGv_i64 tcg_hiaddr;
@@ -1101,15 +1114,15 @@ static void do_fp_ld(DisasContext *s, int destidx, TCGv_i64 tcg_addr, int size)
         tcg_hiaddr = tcg_temp_new_i64(tcg_ctx);
 
         tcg_gen_addi_i64(tcg_ctx, tcg_hiaddr, tcg_addr, 8);
-        tcg_gen_qemu_ld_i64(s->uc, tmplo, be ? tcg_hiaddr : tcg_addr, get_mem_index(s),
+        tcg_gen_qemu_ld_i64(uc, tmplo, be ? tcg_hiaddr : tcg_addr, get_mem_index(s),
                             s->be_data | MO_Q);
-        tcg_gen_qemu_ld_i64(s->uc, tmphi, be ? tcg_addr : tcg_hiaddr, get_mem_index(s),
+        tcg_gen_qemu_ld_i64(uc, tmphi, be ? tcg_addr : tcg_hiaddr, get_mem_index(s),
                             s->be_data | MO_Q);
         tcg_temp_free_i64(tcg_ctx, tcg_hiaddr);
     }
 
-    tcg_gen_st_i64(tcg_ctx, tmplo, tcg_ctx->cpu_env, fp_reg_offset(s, destidx, MO_64));
-    tcg_gen_st_i64(tcg_ctx, tmphi, tcg_ctx->cpu_env, fp_reg_hi_offset(s, destidx));
+    tcg_gen_st_i64(tcg_ctx, tmplo, uc->cpu_env, fp_reg_offset(s, destidx, MO_64));
+    tcg_gen_st_i64(tcg_ctx, tmphi, uc->cpu_env, fp_reg_hi_offset(s, destidx));
 
     tcg_temp_free_i64(tcg_ctx, tmplo);
     tcg_temp_free_i64(tcg_ctx, tmphi);
@@ -1133,30 +1146,31 @@ static void do_fp_ld(DisasContext *s, int destidx, TCGv_i64 tcg_addr, int size)
 static void read_vec_element(DisasContext *s, TCGv_i64 tcg_dest, int srcidx,
                              int element, TCGMemOp memop)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     int vect_off = vec_reg_offset(s, srcidx, element, memop & MO_SIZE);
     switch (memop) {
     case MO_8:
-        tcg_gen_ld8u_i64(tcg_ctx, tcg_dest, tcg_ctx->cpu_env, vect_off);
+        tcg_gen_ld8u_i64(tcg_ctx, tcg_dest, uc->cpu_env, vect_off);
         break;
     case MO_16:
-        tcg_gen_ld16u_i64(tcg_ctx, tcg_dest, tcg_ctx->cpu_env, vect_off);
+        tcg_gen_ld16u_i64(tcg_ctx, tcg_dest, uc->cpu_env, vect_off);
         break;
     case MO_32:
-        tcg_gen_ld32u_i64(tcg_ctx, tcg_dest, tcg_ctx->cpu_env, vect_off);
+        tcg_gen_ld32u_i64(tcg_ctx, tcg_dest, uc->cpu_env, vect_off);
         break;
     case MO_8|MO_SIGN:
-        tcg_gen_ld8s_i64(tcg_ctx, tcg_dest, tcg_ctx->cpu_env, vect_off);
+        tcg_gen_ld8s_i64(tcg_ctx, tcg_dest, uc->cpu_env, vect_off);
         break;
     case MO_16|MO_SIGN:
-        tcg_gen_ld16s_i64(tcg_ctx, tcg_dest, tcg_ctx->cpu_env, vect_off);
+        tcg_gen_ld16s_i64(tcg_ctx, tcg_dest, uc->cpu_env, vect_off);
         break;
     case MO_32|MO_SIGN:
-        tcg_gen_ld32s_i64(tcg_ctx, tcg_dest, tcg_ctx->cpu_env, vect_off);
+        tcg_gen_ld32s_i64(tcg_ctx, tcg_dest, uc->cpu_env, vect_off);
         break;
     case MO_64:
     case MO_64|MO_SIGN:
-        tcg_gen_ld_i64(tcg_ctx, tcg_dest, tcg_ctx->cpu_env, vect_off);
+        tcg_gen_ld_i64(tcg_ctx, tcg_dest, uc->cpu_env, vect_off);
         break;
     default:
         g_assert_not_reached();
@@ -1166,24 +1180,25 @@ static void read_vec_element(DisasContext *s, TCGv_i64 tcg_dest, int srcidx,
 static void read_vec_element_i32(DisasContext *s, TCGv_i32 tcg_dest, int srcidx,
                                  int element, TCGMemOp memop)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     int vect_off = vec_reg_offset(s, srcidx, element, memop & MO_SIZE);
     switch (memop) {
     case MO_8:
-        tcg_gen_ld8u_i32(tcg_ctx, tcg_dest, tcg_ctx->cpu_env, vect_off);
+        tcg_gen_ld8u_i32(tcg_ctx, tcg_dest, uc->cpu_env, vect_off);
         break;
     case MO_16:
-        tcg_gen_ld16u_i32(tcg_ctx, tcg_dest, tcg_ctx->cpu_env, vect_off);
+        tcg_gen_ld16u_i32(tcg_ctx, tcg_dest, uc->cpu_env, vect_off);
         break;
     case MO_8|MO_SIGN:
-        tcg_gen_ld8s_i32(tcg_ctx, tcg_dest, tcg_ctx->cpu_env, vect_off);
+        tcg_gen_ld8s_i32(tcg_ctx, tcg_dest, uc->cpu_env, vect_off);
         break;
     case MO_16|MO_SIGN:
-        tcg_gen_ld16s_i32(tcg_ctx, tcg_dest, tcg_ctx->cpu_env, vect_off);
+        tcg_gen_ld16s_i32(tcg_ctx, tcg_dest, uc->cpu_env, vect_off);
         break;
     case MO_32:
     case MO_32|MO_SIGN:
-        tcg_gen_ld_i32(tcg_ctx, tcg_dest, tcg_ctx->cpu_env, vect_off);
+        tcg_gen_ld_i32(tcg_ctx, tcg_dest, uc->cpu_env, vect_off);
         break;
     default:
         g_assert_not_reached();
@@ -1194,20 +1209,21 @@ static void read_vec_element_i32(DisasContext *s, TCGv_i32 tcg_dest, int srcidx,
 static void write_vec_element(DisasContext *s, TCGv_i64 tcg_src, int destidx,
                               int element, TCGMemOp memop)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     int vect_off = vec_reg_offset(s, destidx, element, memop & MO_SIZE);
     switch (memop) {
     case MO_8:
-        tcg_gen_st8_i64(tcg_ctx, tcg_src, tcg_ctx->cpu_env, vect_off);
+        tcg_gen_st8_i64(tcg_ctx, tcg_src, uc->cpu_env, vect_off);
         break;
     case MO_16:
-        tcg_gen_st16_i64(tcg_ctx, tcg_src, tcg_ctx->cpu_env, vect_off);
+        tcg_gen_st16_i64(tcg_ctx, tcg_src, uc->cpu_env, vect_off);
         break;
     case MO_32:
-        tcg_gen_st32_i64(tcg_ctx, tcg_src, tcg_ctx->cpu_env, vect_off);
+        tcg_gen_st32_i64(tcg_ctx, tcg_src, uc->cpu_env, vect_off);
         break;
     case MO_64:
-        tcg_gen_st_i64(tcg_ctx, tcg_src, tcg_ctx->cpu_env, vect_off);
+        tcg_gen_st_i64(tcg_ctx, tcg_src, uc->cpu_env, vect_off);
         break;
     default:
         g_assert_not_reached();
@@ -1217,17 +1233,18 @@ static void write_vec_element(DisasContext *s, TCGv_i64 tcg_src, int destidx,
 static void write_vec_element_i32(DisasContext *s, TCGv_i32 tcg_src,
                                   int destidx, int element, TCGMemOp memop)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     int vect_off = vec_reg_offset(s, destidx, element, memop & MO_SIZE);
     switch (memop) {
     case MO_8:
-        tcg_gen_st8_i32(tcg_ctx, tcg_src, tcg_ctx->cpu_env, vect_off);
+        tcg_gen_st8_i32(tcg_ctx, tcg_src, uc->cpu_env, vect_off);
         break;
     case MO_16:
-        tcg_gen_st16_i32(tcg_ctx, tcg_src, tcg_ctx->cpu_env, vect_off);
+        tcg_gen_st16_i32(tcg_ctx, tcg_src, uc->cpu_env, vect_off);
         break;
     case MO_32:
-        tcg_gen_st_i32(tcg_ctx, tcg_src, tcg_ctx->cpu_env, vect_off);
+        tcg_gen_st_i32(tcg_ctx, tcg_src, uc->cpu_env, vect_off);
         break;
     default:
         g_assert_not_reached();
@@ -1613,7 +1630,7 @@ static void handle_msr_i(DisasContext *s, uint32_t insn,
         TCGv_i32 tcg_imm = tcg_const_i32(tcg_ctx, crm);
         TCGv_i32 tcg_op = tcg_const_i32(tcg_ctx, op);
         gen_a64_set_pc_im(s, s->pc - 4);
-        gen_helper_msr_i_pstate(tcg_ctx, tcg_ctx->cpu_env, tcg_op, tcg_imm);
+        gen_helper_msr_i_pstate(tcg_ctx, s->uc->cpu_env, tcg_op, tcg_imm);
         tcg_temp_free_i32(tcg_ctx, tcg_imm);
         tcg_temp_free_i32(tcg_ctx, tcg_op);
         /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs.  */
@@ -1682,7 +1699,8 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
                        unsigned int op0, unsigned int op1, unsigned int op2,
                        unsigned int crn, unsigned int crm, unsigned int rt)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     const ARMCPRegInfo *ri;
     TCGv_i64 tcg_rt;
 
@@ -1720,7 +1738,7 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
         syndrome = syn_aa64_sysregtrap(op0, op1, op2, crn, crm, rt, isread);
         tcg_syn = tcg_const_i32(tcg_ctx, syndrome);
         tcg_isread = tcg_const_i32(tcg_ctx, isread);
-        gen_helper_access_check_cp_reg(tcg_ctx, tcg_ctx->cpu_env, tmpptr, tcg_syn, tcg_isread);
+        gen_helper_access_check_cp_reg(tcg_ctx, uc->cpu_env, tmpptr, tcg_syn, tcg_isread);
         tcg_temp_free_ptr(tcg_ctx, tmpptr);
         tcg_temp_free_i32(tcg_ctx, tcg_syn);
         tcg_temp_free_i32(tcg_ctx, tcg_isread);
@@ -1748,7 +1766,7 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
     case ARM_CP_DC_ZVA:
         /* Writes clear the aligned block of memory which rt points into. */
         tcg_rt = cpu_reg(s, rt);
-        gen_helper_dc_zva(tcg_ctx, tcg_ctx->cpu_env, tcg_rt);
+        gen_helper_dc_zva(tcg_ctx, uc->cpu_env, tcg_rt);
         return;
     default:
         break;
@@ -1775,10 +1793,10 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
         } else if (ri->readfn) {
             TCGv_ptr tmpptr;
             tmpptr = tcg_const_ptr(tcg_ctx, ri);
-            gen_helper_get_cp_reg64(tcg_ctx, tcg_rt, tcg_ctx->cpu_env, tmpptr);
+            gen_helper_get_cp_reg64(tcg_ctx, tcg_rt, uc->cpu_env, tmpptr);
             tcg_temp_free_ptr(tcg_ctx, tmpptr);
         } else {
-            tcg_gen_ld_i64(tcg_ctx, tcg_rt, tcg_ctx->cpu_env, ri->fieldoffset);
+            tcg_gen_ld_i64(tcg_ctx, tcg_rt, uc->cpu_env, ri->fieldoffset);
         }
     } else {
         if (ri->type & ARM_CP_CONST) {
@@ -1787,10 +1805,10 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
         } else if (ri->writefn) {
             TCGv_ptr tmpptr;
             tmpptr = tcg_const_ptr(tcg_ctx, ri);
-            gen_helper_set_cp_reg64(tcg_ctx, tcg_ctx->cpu_env, tmpptr, tcg_rt);
+            gen_helper_set_cp_reg64(tcg_ctx, uc->cpu_env, tmpptr, tcg_rt);
             tcg_temp_free_ptr(tcg_ctx, tmpptr);
         } else {
-            tcg_gen_st_i64(tcg_ctx, tcg_rt, tcg_ctx->cpu_env, ri->fieldoffset);
+            tcg_gen_st_i64(tcg_ctx, tcg_rt, uc->cpu_env, ri->fieldoffset);
         }
     }
 
@@ -1858,7 +1876,8 @@ static void disas_system(DisasContext *s, uint32_t insn)
  */
 static void disas_exc(DisasContext *s, uint32_t insn)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     int opc = extract32(insn, 21, 3);
     int op2_ll = extract32(insn, 0, 5);
     int imm16 = extract32(insn, 5, 16);
@@ -1886,7 +1905,7 @@ static void disas_exc(DisasContext *s, uint32_t insn)
              * as an undefined insn by runtime configuration.
              */
             gen_a64_set_pc_im(s, s->pc - 4);
-            gen_helper_pre_hvc(tcg_ctx, tcg_ctx->cpu_env);
+            gen_helper_pre_hvc(tcg_ctx, uc->cpu_env);
             gen_ss_advance(s);
             gen_exception_insn(s, 0, EXCP_HVC, syn_aa64_hvc(imm16), 2);
             break;
@@ -1897,7 +1916,7 @@ static void disas_exc(DisasContext *s, uint32_t insn)
             }
             gen_a64_set_pc_im(s, s->pc - 4);
             tmp = tcg_const_i32(tcg_ctx, syn_aa64_smc(imm16));
-            gen_helper_pre_smc(tcg_ctx, tcg_ctx->cpu_env, tmp);
+            gen_helper_pre_smc(tcg_ctx, uc->cpu_env, tmp);
             tcg_temp_free_i32(tcg_ctx, tmp);
             gen_ss_advance(s);
             gen_exception_insn(s, 0, EXCP_SMC, syn_aa64_smc(imm16), 3);
@@ -1965,7 +1984,8 @@ static void disas_exc(DisasContext *s, uint32_t insn)
  */
 static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     unsigned int opc, op2, op3, rn, op4;
 
     opc = extract32(insn, 21, 4);
@@ -1994,7 +2014,7 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
             unallocated_encoding(s);
             return;
         }
-        gen_helper_exception_return(tcg_ctx, tcg_ctx->cpu_env);
+        gen_helper_exception_return(tcg_ctx, uc->cpu_env);
         /* Must exit loop to check un-masked IRQs */
         s->base.is_jmp = DISAS_EXIT;
         return;
@@ -2103,7 +2123,8 @@ static void gen_load_exclusive(DisasContext *s, int rt, int rt2,
 static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
                                 TCGv_i64 addr, int size, int is_pair)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]
      *     && (!is_pair || env->exclusive_high == [addr + datasize])) {
      *     [addr] = {Rt};
@@ -2138,22 +2159,22 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
             tcg_gen_setcond_i64(tcg_ctx, TCG_COND_NE, tmp, tmp, tcg_ctx->cpu_exclusive_val);
         } else if (s->be_data == MO_LE) {
             if (tb_cflags(s->base.tb) & CF_PARALLEL) {
-                gen_helper_paired_cmpxchg64_le_parallel(tcg_ctx, tmp, tcg_ctx->cpu_env,
+                gen_helper_paired_cmpxchg64_le_parallel(tcg_ctx, tmp, uc->cpu_env,
                                                         tcg_ctx->cpu_exclusive_addr,
                                                         cpu_reg(s, rt),
                                                         cpu_reg(s, rt2));
             } else {
-                gen_helper_paired_cmpxchg64_le(tcg_ctx, tmp, tcg_ctx->cpu_env, tcg_ctx->cpu_exclusive_addr,
+                gen_helper_paired_cmpxchg64_le(tcg_ctx, tmp, uc->cpu_env, tcg_ctx->cpu_exclusive_addr,
                                                cpu_reg(s, rt), cpu_reg(s, rt2));
             }
         } else {
             if (tb_cflags(s->base.tb) & CF_PARALLEL) {
-                gen_helper_paired_cmpxchg64_be_parallel(tcg_ctx, tmp, tcg_ctx->cpu_env,
+                gen_helper_paired_cmpxchg64_be_parallel(tcg_ctx, tmp, uc->cpu_env,
                                                         tcg_ctx->cpu_exclusive_addr,
                                                         cpu_reg(s, rt),
                                                         cpu_reg(s, rt2));
             } else {
-                gen_helper_paired_cmpxchg64_be(tcg_ctx, tmp, tcg_ctx->cpu_env, tcg_ctx->cpu_exclusive_addr,
+                gen_helper_paired_cmpxchg64_be(tcg_ctx, tmp, uc->cpu_env, tcg_ctx->cpu_exclusive_addr,
                                                cpu_reg(s, rt), cpu_reg(s, rt2));
             }
         }
@@ -4755,7 +4776,7 @@ static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
         tcg_gen_xori_i32(tcg_ctx, tcg_res, tcg_op, 0x8000);
         break;
     case 0x3: /* FSQRT */
-        gen_helper_sqrt_f16(tcg_ctx, tcg_res, tcg_op, tcg_ctx->cpu_env);
+        gen_helper_sqrt_f16(tcg_ctx, tcg_res, tcg_op, s->uc->cpu_env);
         break;
     case 0x8: /* FRINTN */
     case 0x9: /* FRINTP */
@@ -4817,7 +4838,7 @@ static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
         gen_helper_vfp_negs(tcg_ctx, tcg_res, tcg_op);
         break;
     case 0x3: /* FSQRT */
-        gen_helper_vfp_sqrts(tcg_ctx, tcg_res, tcg_op, tcg_ctx->cpu_env);
+        gen_helper_vfp_sqrts(tcg_ctx, tcg_res, tcg_op, s->uc->cpu_env);
         break;
     case 0x8: /* FRINTN */
     case 0x9: /* FRINTP */
@@ -4877,7 +4898,7 @@ static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn)
         gen_helper_vfp_negd(tcg_ctx, tcg_res, tcg_op);
         break;
     case 0x3: /* FSQRT */
-        gen_helper_vfp_sqrtd(tcg_ctx, tcg_res, tcg_op, tcg_ctx->cpu_env);
+        gen_helper_vfp_sqrtd(tcg_ctx, tcg_res, tcg_op, s->uc->cpu_env);
         break;
     case 0x8: /* FRINTN */
     case 0x9: /* FRINTP */
@@ -4914,7 +4935,8 @@ static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn)
 static void handle_fp_fcvt(DisasContext *s, int opcode,
                            int rd, int rn, int dtype, int ntype)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     switch (ntype) {
     case 0x0:
     {
@@ -4922,13 +4944,13 @@ static void handle_fp_fcvt(DisasContext *s, int opcode,
         if (dtype == 1) {
             /* Single to double */
             TCGv_i64 tcg_rd = tcg_temp_new_i64(tcg_ctx);
-            gen_helper_vfp_fcvtds(tcg_ctx, tcg_rd, tcg_rn, tcg_ctx->cpu_env);
+            gen_helper_vfp_fcvtds(tcg_ctx, tcg_rd, tcg_rn, uc->cpu_env);
             write_fp_dreg(s, rd, tcg_rd);
             tcg_temp_free_i64(tcg_ctx, tcg_rd);
         } else {
             /* Single to half */
             TCGv_i32 tcg_rd = tcg_temp_new_i32(tcg_ctx);
-            gen_helper_vfp_fcvt_f32_to_f16(tcg_ctx, tcg_rd, tcg_rn, tcg_ctx->cpu_env);
+            gen_helper_vfp_fcvt_f32_to_f16(tcg_ctx, tcg_rd, tcg_rn, uc->cpu_env);
             /* write_fp_sreg is OK here because top half of tcg_rd is zero */
             write_fp_sreg(s, rd, tcg_rd);
             tcg_temp_free_i32(tcg_ctx, tcg_rd);
@@ -4942,10 +4964,10 @@ static void handle_fp_fcvt(DisasContext *s, int opcode,
         TCGv_i32 tcg_rd = tcg_temp_new_i32(tcg_ctx);
         if (dtype == 0) {
             /* Double to single */
-            gen_helper_vfp_fcvtsd(tcg_ctx, tcg_rd, tcg_rn, tcg_ctx->cpu_env);
+            gen_helper_vfp_fcvtsd(tcg_ctx, tcg_rd, tcg_rn, uc->cpu_env);
         } else {
             /* Double to half */
-            gen_helper_vfp_fcvt_f64_to_f16(tcg_ctx, tcg_rd, tcg_rn, tcg_ctx->cpu_env);
+            gen_helper_vfp_fcvt_f64_to_f16(tcg_ctx, tcg_rd, tcg_rn, uc->cpu_env);
             /* write_fp_sreg is OK here because top half of tcg_rd is zero */
         }
         write_fp_sreg(s, rd, tcg_rd);
@@ -4960,13 +4982,13 @@ static void handle_fp_fcvt(DisasContext *s, int opcode,
         if (dtype == 0) {
             /* Half to single */
             TCGv_i32 tcg_rd = tcg_temp_new_i32(tcg_ctx);
-            gen_helper_vfp_fcvt_f16_to_f32(tcg_ctx, tcg_rd, tcg_rn, tcg_ctx->cpu_env);
+            gen_helper_vfp_fcvt_f16_to_f32(tcg_ctx, tcg_rd, tcg_rn, uc->cpu_env);
             write_fp_sreg(s, rd, tcg_rd);
             tcg_temp_free_i32(tcg_ctx, tcg_rd);
         } else {
             /* Half to double */
             TCGv_i64 tcg_rd = tcg_temp_new_i64(tcg_ctx);
-            gen_helper_vfp_fcvt_f16_to_f64(tcg_ctx, tcg_rd, tcg_rn, tcg_ctx->cpu_env);
+            gen_helper_vfp_fcvt_f16_to_f64(tcg_ctx, tcg_rd, tcg_rn, uc->cpu_env);
             write_fp_dreg(s, rd, tcg_rd);
             tcg_temp_free_i64(tcg_ctx, tcg_rd);
         }
@@ -5542,7 +5564,8 @@ static void disas_fp_fixed_conv(DisasContext *s, uint32_t insn)
 
 static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     /* FMOV: gpr to or from float, double, or top half of quad fp reg,
      * without conversion.
      */
@@ -5556,9 +5579,9 @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)
             /* 32 bit */
             TCGv_i64 tmp = tcg_temp_new_i64(tcg_ctx);
             tcg_gen_ext32u_i64(tcg_ctx, tmp, tcg_rn);
-            tcg_gen_st_i64(tcg_ctx, tmp, tcg_ctx->cpu_env, fp_reg_offset(s, rd, MO_64));
+            tcg_gen_st_i64(tcg_ctx, tmp, uc->cpu_env, fp_reg_offset(s, rd, MO_64));
             tcg_gen_movi_i64(tcg_ctx, tmp, 0);
-            tcg_gen_st_i64(tcg_ctx, tmp, tcg_ctx->cpu_env, fp_reg_hi_offset(s, rd));
+            tcg_gen_st_i64(tcg_ctx, tmp, uc->cpu_env, fp_reg_hi_offset(s, rd));
             tcg_temp_free_i64(tcg_ctx, tmp);
             break;
         }
@@ -5566,14 +5589,14 @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)
         {
             /* 64 bit */
             TCGv_i64 tmp = tcg_const_i64(tcg_ctx, 0);
-            tcg_gen_st_i64(tcg_ctx, tcg_rn, tcg_ctx->cpu_env, fp_reg_offset(s, rd, MO_64));
-            tcg_gen_st_i64(tcg_ctx, tmp, tcg_ctx->cpu_env, fp_reg_hi_offset(s, rd));
+            tcg_gen_st_i64(tcg_ctx, tcg_rn, uc->cpu_env, fp_reg_offset(s, rd, MO_64));
+            tcg_gen_st_i64(tcg_ctx, tmp, uc->cpu_env, fp_reg_hi_offset(s, rd));
             tcg_temp_free_i64(tcg_ctx, tmp);
             break;
         }
         case 2:
             /* 64 bit to top half. */
-            tcg_gen_st_i64(tcg_ctx, tcg_rn, tcg_ctx->cpu_env, fp_reg_hi_offset(s, rd));
+            tcg_gen_st_i64(tcg_ctx, tcg_rn, uc->cpu_env, fp_reg_hi_offset(s, rd));
             break;
         }
     } else {
@@ -5582,15 +5605,15 @@ static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)
         switch (type) {
         case 0:
             /* 32 bit */
-            tcg_gen_ld32u_i64(tcg_ctx, tcg_rd, tcg_ctx->cpu_env, fp_reg_offset(s, rn, MO_32));
+            tcg_gen_ld32u_i64(tcg_ctx, tcg_rd, uc->cpu_env, fp_reg_offset(s, rn, MO_32));
             break;
         case 1:
             /* 64 bit */
-            tcg_gen_ld_i64(tcg_ctx, tcg_rd, tcg_ctx->cpu_env, fp_reg_offset(s, rn, MO_64));
+            tcg_gen_ld_i64(tcg_ctx, tcg_rd, uc->cpu_env, fp_reg_offset(s, rn, MO_64));
             break;
         case 2:
             /* 64 bits from top half */
-            tcg_gen_ld_i64(tcg_ctx, tcg_rd, tcg_ctx->cpu_env, fp_reg_hi_offset(s, rn));
+            tcg_gen_ld_i64(tcg_ctx, tcg_rd, uc->cpu_env, fp_reg_hi_offset(s, rn));
             break;
         }
     }
@@ -5814,7 +5837,8 @@ static void disas_simd_ext(DisasContext *s, uint32_t insn)
  */
 static void disas_simd_tb(DisasContext *s, uint32_t insn)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     int op2 = extract32(insn, 22, 2);
     int is_q = extract32(insn, 30, 1);
     int rm = extract32(insn, 16, 5);
@@ -5858,11 +5882,11 @@ static void disas_simd_tb(DisasContext *s, uint32_t insn)
     tcg_regno = tcg_const_i32(tcg_ctx, rn);
     tcg_numregs = tcg_const_i32(tcg_ctx, len + 1);
     read_vec_element(s, tcg_idx, rm, 0, MO_64);
-    gen_helper_simd_tbl(tcg_ctx, tcg_resl, tcg_ctx->cpu_env, tcg_resl, tcg_idx,
+    gen_helper_simd_tbl(tcg_ctx, tcg_resl, uc->cpu_env, tcg_resl, tcg_idx,
                         tcg_regno, tcg_numregs);
     if (is_q) {
         read_vec_element(s, tcg_idx, rm, 1, MO_64);
-        gen_helper_simd_tbl(tcg_ctx, tcg_resh, tcg_ctx->cpu_env, tcg_resh, tcg_idx,
+        gen_helper_simd_tbl(tcg_ctx, tcg_resh, uc->cpu_env, tcg_resh, tcg_idx,
                             tcg_regno, tcg_numregs);
     }
     tcg_temp_free_i64(tcg_ctx, tcg_idx);
@@ -6976,7 +7000,8 @@ static void handle_vec_simd_sqshrn(DisasContext *s, bool is_scalar, bool is_q,
                                    int immh, int immb, int opcode,
                                    int rn, int rd)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     int immhb = immh << 3 | immb;
     int size = 32 - clz32(immh) - 1;
     int esize = 8 << size;
@@ -7040,7 +7065,7 @@ static void handle_vec_simd_sqshrn(DisasContext *s, bool is_scalar, bool is_q,
         read_vec_element(s, tcg_rn, rn, i, ldop);
         handle_shri_with_rndacc(s, tcg_rd, tcg_rn, tcg_round,
                                 false, is_u_shift, size+1, shift);
-        narrowfn(tcg_ctx, tcg_rd_narrowed, tcg_ctx->cpu_env, tcg_rd);
+        narrowfn(tcg_ctx, tcg_rd_narrowed, uc->cpu_env, tcg_rd);
         tcg_gen_extu_i32_i64(tcg_ctx, tcg_rd, tcg_rd_narrowed);
         tcg_gen_deposit_i64(tcg_ctx, tcg_final, tcg_final, tcg_rd, esize * i, esize);
     }
@@ -7067,7 +7092,8 @@ static void handle_simd_qshl(DisasContext *s, bool scalar, bool is_q,
                              bool src_unsigned, bool dst_unsigned,
                              int immh, int immb, int rn, int rd)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     int immhb = immh << 3 | immb;
     int size = 32 - clz32(immh) - 1;
     int shift = immhb - (8 << size);
@@ -7118,7 +7144,7 @@ static void handle_simd_qshl(DisasContext *s, bool scalar, bool is_q,
             TCGv_i64 tcg_op = tcg_temp_new_i64(tcg_ctx);
 
             read_vec_element(s, tcg_op, rn, pass, MO_64);
-            genfn(tcg_ctx, tcg_op, tcg_ctx->cpu_env, tcg_op, tcg_shift);
+            genfn(tcg_ctx, tcg_op, uc->cpu_env, tcg_op, tcg_shift);
             write_vec_element(s, tcg_op, rd, pass, MO_64);
 
             tcg_temp_free_i64(tcg_ctx, tcg_op);
@@ -7150,7 +7176,7 @@ static void handle_simd_qshl(DisasContext *s, bool scalar, bool is_q,
             TCGv_i32 tcg_op = tcg_temp_new_i32(tcg_ctx);
 
             read_vec_element_i32(s, tcg_op, rn, pass, memop);
-            genfn(tcg_ctx, tcg_op, tcg_ctx->cpu_env, tcg_op, tcg_shift);
+            genfn(tcg_ctx, tcg_op, uc->cpu_env, tcg_op, tcg_shift);
             if (scalar) {
                 switch (size) {
                 case 0:
@@ -7483,7 +7509,8 @@ static void disas_simd_scalar_shift_imm(DisasContext *s, uint32_t insn)
  */
 static void disas_simd_scalar_three_reg_diff(DisasContext *s, uint32_t insn)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     bool is_u = extract32(insn, 29, 1);
     int size = extract32(insn, 22, 2);
     int opcode = extract32(insn, 12, 4);
@@ -7523,7 +7550,7 @@ static void disas_simd_scalar_three_reg_diff(DisasContext *s, uint32_t insn)
         read_vec_element(s, tcg_op2, rm, 0, MO_32 | MO_SIGN);
 
         tcg_gen_mul_i64(tcg_ctx, tcg_res, tcg_op1, tcg_op2);
-        gen_helper_neon_addl_saturate_s64(tcg_ctx, tcg_res, tcg_ctx->cpu_env, tcg_res, tcg_res);
+        gen_helper_neon_addl_saturate_s64(tcg_ctx, tcg_res, uc->cpu_env, tcg_res, tcg_res);
 
         switch (opcode) {
         case 0xd: /* SQDMULL, SQDMULL2 */
@@ -7533,7 +7560,7 @@ static void disas_simd_scalar_three_reg_diff(DisasContext *s, uint32_t insn)
             /* fall through */
         case 0x9: /* SQDMLAL, SQDMLAL2 */
             read_vec_element(s, tcg_op1, rd, 0, MO_64);
-            gen_helper_neon_addl_saturate_s64(tcg_ctx, tcg_res, tcg_ctx->cpu_env,
+            gen_helper_neon_addl_saturate_s64(tcg_ctx, tcg_res, uc->cpu_env,
                                               tcg_res, tcg_op1);
             break;
         default:
@@ -7554,7 +7581,7 @@ static void disas_simd_scalar_three_reg_diff(DisasContext *s, uint32_t insn)
         read_vec_element_i32(s, tcg_op2, rm, 0, MO_16);
 
         gen_helper_neon_mull_s16(tcg_ctx, tcg_res, tcg_op1, tcg_op2);
-        gen_helper_neon_addl_saturate_s32(tcg_ctx, tcg_res, tcg_ctx->cpu_env, tcg_res, tcg_res);
+        gen_helper_neon_addl_saturate_s32(tcg_ctx, tcg_res, uc->cpu_env, tcg_res, tcg_res);
 
         switch (opcode) {
         case 0xd: /* SQDMULL, SQDMULL2 */
@@ -7566,7 +7593,7 @@ static void disas_simd_scalar_three_reg_diff(DisasContext *s, uint32_t insn)
         {
             TCGv_i64 tcg_op3 = tcg_temp_new_i64(tcg_ctx);
             read_vec_element(s, tcg_op3, rd, 0, MO_32);
-            gen_helper_neon_addl_saturate_s32(tcg_ctx, tcg_res, tcg_ctx->cpu_env,
+            gen_helper_neon_addl_saturate_s32(tcg_ctx, tcg_res, uc->cpu_env,
                                               tcg_res, tcg_op3);
             tcg_temp_free_i64(tcg_ctx, tcg_op3);
             break;
@@ -7609,7 +7636,8 @@ static void gen_cmtst_vec(TCGContext *s, unsigned vece, TCGv_vec d, TCGv_vec a,
 static void handle_3same_64(DisasContext *s, int opcode, bool u,
                             TCGv_i64 tcg_rd, TCGv_i64 tcg_rn, TCGv_i64 tcg_rm)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     /* Handle 64x64->64 opcodes which are shared between the scalar
      * and vector 3-same groups. We cover every opcode where size == 3
      * is valid in either the three-reg-same (integer, not pairwise)
@@ -7620,16 +7648,16 @@ static void handle_3same_64(DisasContext *s, int opcode, bool u,
     switch (opcode) {
     case 0x1: /* SQADD */
         if (u) {
-            gen_helper_neon_qadd_u64(tcg_ctx, tcg_rd, tcg_ctx->cpu_env, tcg_rn, tcg_rm);
+            gen_helper_neon_qadd_u64(tcg_ctx, tcg_rd, uc->cpu_env, tcg_rn, tcg_rm);
         } else {
-            gen_helper_neon_qadd_s64(tcg_ctx, tcg_rd, tcg_ctx->cpu_env, tcg_rn, tcg_rm);
+            gen_helper_neon_qadd_s64(tcg_ctx, tcg_rd, uc->cpu_env, tcg_rn, tcg_rm);
         }
         break;
     case 0x5: /* SQSUB */
         if (u) {
-            gen_helper_neon_qsub_u64(tcg_ctx, tcg_rd, tcg_ctx->cpu_env, tcg_rn, tcg_rm);
+            gen_helper_neon_qsub_u64(tcg_ctx, tcg_rd, uc->cpu_env, tcg_rn, tcg_rm);
         } else {
-            gen_helper_neon_qsub_s64(tcg_ctx, tcg_rd, tcg_ctx->cpu_env, tcg_rn, tcg_rm);
+            gen_helper_neon_qsub_s64(tcg_ctx, tcg_rd, uc->cpu_env, tcg_rn, tcg_rm);
         }
         break;
     case 0x6: /* CMGT, CMHI */
@@ -7660,9 +7688,9 @@ static void handle_3same_64(DisasContext *s, int opcode, bool u,
         break;
     case 0x9: /* SQSHL, UQSHL */
         if (u) {
-            gen_helper_neon_qshl_u64(tcg_ctx, tcg_rd, tcg_ctx->cpu_env, tcg_rn, tcg_rm);
+            gen_helper_neon_qshl_u64(tcg_ctx, tcg_rd, uc->cpu_env, tcg_rn, tcg_rm);
         } else {
-            gen_helper_neon_qshl_s64(tcg_ctx, tcg_rd, tcg_ctx->cpu_env, tcg_rn, tcg_rm);
+            gen_helper_neon_qshl_s64(tcg_ctx, tcg_rd, uc->cpu_env, tcg_rn, tcg_rm);
         }
         break;
     case 0xa: /* SRSHL, URSHL */
@@ -7674,9 +7702,9 @@ static void handle_3same_64(DisasContext *s, int opcode, bool u,
         break;
     case 0xb: /* SQRSHL, UQRSHL */
         if (u) {
-            gen_helper_neon_qrshl_u64(tcg_ctx, tcg_rd, tcg_ctx->cpu_env, tcg_rn, tcg_rm);
+            gen_helper_neon_qrshl_u64(tcg_ctx, tcg_rd, uc->cpu_env, tcg_rn, tcg_rm);
         } else {
-            gen_helper_neon_qrshl_s64(tcg_ctx, tcg_rd, tcg_ctx->cpu_env, tcg_rn, tcg_rm);
+            gen_helper_neon_qrshl_s64(tcg_ctx, tcg_rd, uc->cpu_env, tcg_rn, tcg_rm);
         }
         break;
     case 0x10: /* ADD, SUB */
@@ -7888,7 +7916,8 @@ static void handle_3same_float(DisasContext *s, int size, int elements,
  */
 static void disas_simd_scalar_three_reg_same(DisasContext *s, uint32_t insn)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     int rd = extract32(insn, 0, 5);
     int rn = extract32(insn, 5, 5);
     int opcode = extract32(insn, 11, 5);
@@ -8035,7 +8064,7 @@ static void disas_simd_scalar_three_reg_same(DisasContext *s, uint32_t insn)
             g_assert_not_reached();
         }
 
-        genenvfn(tcg_ctx, tcg_rd32, tcg_ctx->cpu_env, tcg_rn, tcg_rm);
+        genenvfn(tcg_ctx, tcg_rd32, uc->cpu_env, tcg_rn, tcg_rm);
         tcg_gen_extu_i32_i64(tcg_ctx, tcg_rd, tcg_rd32);
         tcg_temp_free_i32(tcg_ctx, tcg_rd32);
         tcg_temp_free_i32(tcg_ctx, tcg_rn);
@@ -8155,7 +8184,8 @@ static void disas_simd_scalar_three_reg_same_fp16(DisasContext *s,
 static void disas_simd_scalar_three_reg_same_extra(DisasContext *s,
                                                    uint32_t insn)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     int rd = extract32(insn, 0, 5);
     int rn = extract32(insn, 5, 5);
     int opcode = extract32(insn, 11, 4);
@@ -8204,16 +8234,16 @@ static void disas_simd_scalar_three_reg_same_extra(DisasContext *s,
     switch (opcode) {
     case 0x0: /* SQRDMLAH */
         if (size == 1) {
-            gen_helper_neon_qrdmlah_s16(tcg_ctx, ele3, tcg_ctx->cpu_env, ele1, ele2, ele3);
+            gen_helper_neon_qrdmlah_s16(tcg_ctx, ele3, uc->cpu_env, ele1, ele2, ele3);
         } else {
-            gen_helper_neon_qrdmlah_s32(tcg_ctx, ele3, tcg_ctx->cpu_env, ele1, ele2, ele3);
+            gen_helper_neon_qrdmlah_s32(tcg_ctx, ele3, uc->cpu_env, ele1, ele2, ele3);
         }
         break;
     case 0x1: /* SQRDMLSH */
         if (size == 1) {
-            gen_helper_neon_qrdmlsh_s16(tcg_ctx, ele3, tcg_ctx->cpu_env, ele1, ele2, ele3);
+            gen_helper_neon_qrdmlsh_s16(tcg_ctx, ele3, uc->cpu_env, ele1, ele2, ele3);
         } else {
-            gen_helper_neon_qrdmlsh_s32(tcg_ctx, ele3, tcg_ctx->cpu_env, ele1, ele2, ele3);
+            gen_helper_neon_qrdmlsh_s32(tcg_ctx, ele3, uc->cpu_env, ele1, ele2, ele3);
         }
         break;
     default:
@@ -8234,7 +8264,8 @@ static void handle_2misc_64(DisasContext *s, int opcode, bool u,
                             TCGv_i64 tcg_rd, TCGv_i64 tcg_rn,
                             TCGv_i32 tcg_rmode, TCGv_ptr tcg_fpstatus)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     /* Handle 64->64 opcodes which are shared between the scalar and
      * vector 2-reg-misc groups. We cover every integer opcode where size == 3
      * is valid in either group and also the double-precision fp ops.
@@ -8259,9 +8290,9 @@ static void handle_2misc_64(DisasContext *s, int opcode, bool u,
         break;
     case 0x7: /* SQABS, SQNEG */
         if (u) {
-            gen_helper_neon_qneg_s64(tcg_ctx, tcg_rd, tcg_ctx->cpu_env, tcg_rn);
+            gen_helper_neon_qneg_s64(tcg_ctx, tcg_rd, uc->cpu_env, tcg_rn);
         } else {
-            gen_helper_neon_qabs_s64(tcg_ctx, tcg_rd, tcg_ctx->cpu_env, tcg_rn);
+            gen_helper_neon_qabs_s64(tcg_ctx, tcg_rd, uc->cpu_env, tcg_rn);
         }
         break;
     case 0xa: /* CMLT */
@@ -8298,7 +8329,7 @@ static void handle_2misc_64(DisasContext *s, int opcode, bool u,
         gen_helper_vfp_negd(tcg_ctx, tcg_rd, tcg_rn);
         break;
     case 0x7f: /* FSQRT */
-        gen_helper_vfp_sqrtd(tcg_ctx, tcg_rd, tcg_rn, tcg_ctx->cpu_env);
+        gen_helper_vfp_sqrtd(tcg_ctx, tcg_rd, tcg_rn, uc->cpu_env);
         break;
     case 0x1a: /* FCVTNS */
     case 0x1b: /* FCVTMS */
@@ -8558,7 +8589,8 @@ static void handle_2misc_narrow(DisasContext *s, bool scalar,
                                 int opcode, bool u, bool is_q,
                                 int size, int rn, int rd)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     /* Handle 2-reg-misc ops which are narrowing (so each 2*size element
      * in the source becomes a size element in the destination).
      */
@@ -8619,13 +8651,13 @@ static void handle_2misc_narrow(DisasContext *s, bool scalar,
         case 0x16: /* FCVTN, FCVTN2 */
             /* 32 bit to 16 bit or 64 bit to 32 bit float conversion */
             if (size == 2) {
-                gen_helper_vfp_fcvtsd(tcg_ctx, tcg_res[pass], tcg_op, tcg_ctx->cpu_env);
+                gen_helper_vfp_fcvtsd(tcg_ctx, tcg_res[pass], tcg_op, uc->cpu_env);
             } else {
                 TCGv_i32 tcg_lo = tcg_temp_new_i32(tcg_ctx);
                 TCGv_i32 tcg_hi = tcg_temp_new_i32(tcg_ctx);
                 tcg_gen_extr_i64_i32(tcg_ctx, tcg_lo, tcg_hi, tcg_op);
-                gen_helper_vfp_fcvt_f32_to_f16(tcg_ctx, tcg_lo, tcg_lo, tcg_ctx->cpu_env);
-                gen_helper_vfp_fcvt_f32_to_f16(tcg_ctx, tcg_hi, tcg_hi, tcg_ctx->cpu_env);
+                gen_helper_vfp_fcvt_f32_to_f16(tcg_ctx, tcg_lo, tcg_lo, uc->cpu_env);
+                gen_helper_vfp_fcvt_f32_to_f16(tcg_ctx, tcg_hi, tcg_hi, uc->cpu_env);
                 tcg_gen_deposit_i32(tcg_ctx, tcg_res[pass], tcg_lo, tcg_hi, 16, 16);
                 tcg_temp_free_i32(tcg_ctx, tcg_lo);
                 tcg_temp_free_i32(tcg_ctx, tcg_hi);
@@ -8636,7 +8668,7 @@ static void handle_2misc_narrow(DisasContext *s, bool scalar,
              * with von Neumann rounding (round to odd)
              */
             assert(size == 2);
-            gen_helper_fcvtx_f64_to_f32(tcg_ctx, tcg_res[pass], tcg_op, tcg_ctx->cpu_env);
+            gen_helper_fcvtx_f64_to_f32(tcg_ctx, tcg_res[pass], tcg_op, uc->cpu_env);
             break;
         default:
             g_assert_not_reached();
@@ -8645,7 +8677,7 @@ static void handle_2misc_narrow(DisasContext *s, bool scalar,
         if (genfn) {
             genfn(tcg_ctx, tcg_res[pass], tcg_op);
         } else if (genenvfn) {
-            genenvfn(tcg_ctx, tcg_res[pass], tcg_ctx->cpu_env, tcg_op);
+            genenvfn(tcg_ctx, tcg_res[pass], uc->cpu_env, tcg_op);
         }
 
         tcg_temp_free_i64(tcg_ctx, tcg_op);
@@ -8662,7 +8694,8 @@ static void handle_2misc_narrow(DisasContext *s, bool scalar,
 static void handle_2misc_satacc(DisasContext *s, bool is_scalar, bool is_u,
                                 bool is_q, int size, int rn, int rd)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     bool is_double = (size == 3);
 
     if (is_double) {
@@ -8675,9 +8708,9 @@ static void handle_2misc_satacc(DisasContext *s, bool is_scalar, bool is_u,
             read_vec_element(s, tcg_rd, rd, pass, MO_64);
 
             if (is_u) { /* USQADD */
-                gen_helper_neon_uqadd_s64(tcg_ctx, tcg_rd, tcg_ctx->cpu_env, tcg_rn, tcg_rd);
+                gen_helper_neon_uqadd_s64(tcg_ctx, tcg_rd, uc->cpu_env, tcg_rn, tcg_rd);
             } else { /* SUQADD */
-                gen_helper_neon_sqadd_u64(tcg_ctx, tcg_rd, tcg_ctx->cpu_env, tcg_rn, tcg_rd);
+                gen_helper_neon_sqadd_u64(tcg_ctx, tcg_rd, uc->cpu_env, tcg_rn, tcg_rd);
             }
             write_vec_element(s, tcg_rd, rd, pass, MO_64);
         }
@@ -8707,13 +8740,13 @@ static void handle_2misc_satacc(DisasContext *s, bool is_scalar, bool is_u,
             if (is_u) { /* USQADD */
                 switch (size) {
                 case 0:
-                    gen_helper_neon_uqadd_s8(tcg_ctx, tcg_rd, tcg_ctx->cpu_env, tcg_rn, tcg_rd);
+                    gen_helper_neon_uqadd_s8(tcg_ctx, tcg_rd, uc->cpu_env, tcg_rn, tcg_rd);
                     break;
                 case 1:
-                    gen_helper_neon_uqadd_s16(tcg_ctx, tcg_rd, tcg_ctx->cpu_env, tcg_rn, tcg_rd);
+                    gen_helper_neon_uqadd_s16(tcg_ctx, tcg_rd, uc->cpu_env, tcg_rn, tcg_rd);
                     break;
                 case 2:
-                    gen_helper_neon_uqadd_s32(tcg_ctx, tcg_rd, tcg_ctx->cpu_env, tcg_rn, tcg_rd);
+                    gen_helper_neon_uqadd_s32(tcg_ctx, tcg_rd, uc->cpu_env, tcg_rn, tcg_rd);
                     break;
                 default:
                     g_assert_not_reached();
@@ -8721,13 +8754,13 @@ static void handle_2misc_satacc(DisasContext *s, bool is_scalar, bool is_u,
             } else { /* SUQADD */
                 switch (size) {
                 case 0:
-                    gen_helper_neon_sqadd_u8(tcg_ctx, tcg_rd, tcg_ctx->cpu_env, tcg_rn, tcg_rd);
+                    gen_helper_neon_sqadd_u8(tcg_ctx, tcg_rd, uc->cpu_env, tcg_rn, tcg_rd);
                     break;
                 case 1:
-                    gen_helper_neon_sqadd_u16(tcg_ctx, tcg_rd, tcg_ctx->cpu_env, tcg_rn, tcg_rd);
+                    gen_helper_neon_sqadd_u16(tcg_ctx, tcg_rd, uc->cpu_env, tcg_rn, tcg_rd);
                     break;
                 case 2:
-                    gen_helper_neon_sqadd_u32(tcg_ctx, tcg_rd, tcg_ctx->cpu_env, tcg_rn, tcg_rd);
+                    gen_helper_neon_sqadd_u32(tcg_ctx, tcg_rd, uc->cpu_env, tcg_rn, tcg_rd);
                     break;
                 default:
                     g_assert_not_reached();
@@ -8755,7 +8788,8 @@ static void handle_2misc_satacc(DisasContext *s, bool is_scalar, bool is_u,
  */
 static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     int rd = extract32(insn, 0, 5);
     int rn = extract32(insn, 5, 5);
     int opcode = extract32(insn, 12, 5);
@@ -8913,7 +8947,7 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
                 { gen_helper_neon_qabs_s32, gen_helper_neon_qneg_s32 },
             };
             genfn = fns[size][u];
-            genfn(tcg_ctx, tcg_rd, tcg_ctx->cpu_env, tcg_rn);
+            genfn(tcg_ctx, tcg_rd, uc->cpu_env, tcg_rn);
             break;
         }
         case 0x1a: /* FCVTNS */
@@ -9535,7 +9569,8 @@ static void gen_neon_addl(TCGContext *tcg_ctx, int size, bool is_sub, TCGv_i64 t
 static void handle_3rd_widening(DisasContext *s, int is_q, int is_u, int size,
                                 int opcode, int rd, int rn, int rm)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     /* 3-reg-different widening insns: 64 x 64 -> 128 */
     TCGv_i64 tcg_res[2];
     int pass, accop;
@@ -9618,7 +9653,7 @@ static void handle_3rd_widening(DisasContext *s, int is_q, int is_u, int size,
             case 11: /* SQDMLSL, SQDMLSL2 */
             case 13: /* SQDMULL, SQDMULL2 */
                 tcg_gen_mul_i64(tcg_ctx, tcg_passres, tcg_op1, tcg_op2);
-                gen_helper_neon_addl_saturate_s64(tcg_ctx, tcg_passres, tcg_ctx->cpu_env,
+                gen_helper_neon_addl_saturate_s64(tcg_ctx, tcg_passres, uc->cpu_env,
                                                   tcg_passres, tcg_passres);
                 break;
             default:
@@ -9630,7 +9665,7 @@ static void handle_3rd_widening(DisasContext *s, int is_q, int is_u, int size,
                 if (accop < 0) {
                     tcg_gen_neg_i64(tcg_ctx, tcg_passres, tcg_passres);
                 }
-                gen_helper_neon_addl_saturate_s64(tcg_ctx, tcg_res[pass], tcg_ctx->cpu_env,
+                gen_helper_neon_addl_saturate_s64(tcg_ctx, tcg_res[pass], uc->cpu_env,
                                                   tcg_res[pass], tcg_passres);
             } else if (accop > 0) {
                 tcg_gen_add_i64(tcg_ctx, tcg_res[pass], tcg_res[pass], tcg_passres);
@@ -9718,7 +9753,7 @@ static void handle_3rd_widening(DisasContext *s, int is_q, int is_u, int size,
             case 13: /* SQDMULL, SQDMULL2 */
                 assert(size == 1);
                 gen_helper_neon_mull_s16(tcg_ctx, tcg_passres, tcg_op1, tcg_op2);
-                gen_helper_neon_addl_saturate_s32(tcg_ctx, tcg_passres, tcg_ctx->cpu_env,
+                gen_helper_neon_addl_saturate_s32(tcg_ctx, tcg_passres, uc->cpu_env,
                                                   tcg_passres, tcg_passres);
                 break;
             case 14: /* PMULL */
@@ -9737,7 +9772,7 @@ static void handle_3rd_widening(DisasContext *s, int is_q, int is_u, int size,
                     if (accop < 0) {
                         gen_helper_neon_negl_u32(tcg_ctx, tcg_passres, tcg_passres);
                     }
-                    gen_helper_neon_addl_saturate_s32(tcg_ctx, tcg_res[pass], tcg_ctx->cpu_env,
+                    gen_helper_neon_addl_saturate_s32(tcg_ctx, tcg_res[pass], uc->cpu_env,
                                                       tcg_res[pass],
                                                       tcg_passres);
                 } else {
@@ -10447,7 +10482,8 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
           .vece = MO_64 },
     };
 
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     int is_q = extract32(insn, 30, 1);
     int u = extract32(insn, 29, 1);
     int size = extract32(insn, 22, 2);
@@ -10710,7 +10746,7 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
             }
 
             if (genenvfn) {
-                genenvfn(tcg_ctx, tcg_res, tcg_ctx->cpu_env, tcg_op1, tcg_op2);
+                genenvfn(tcg_ctx, tcg_res, uc->cpu_env, tcg_op1, tcg_op2);
             } else {
                 genfn(tcg_ctx, tcg_res, tcg_op1, tcg_op2);
             }
@@ -11114,7 +11150,8 @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn)
 static void handle_2misc_widening(DisasContext *s, int opcode, bool is_q,
                                   int size, int rn, int rd)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     /* Handle 2-reg-misc ops which are widening (so each size element
      * in the source becomes a 2*size element in the destination.
      * The only instruction like this is FCVTL.
@@ -11131,7 +11168,7 @@ static void handle_2misc_widening(DisasContext *s, int opcode, bool is_q,
             tcg_res[pass] = tcg_temp_new_i64(tcg_ctx);
 
             read_vec_element_i32(s, tcg_op, rn, srcelt + pass, MO_32);
-            gen_helper_vfp_fcvtds(tcg_ctx, tcg_res[pass], tcg_op, tcg_ctx->cpu_env);
+            gen_helper_vfp_fcvtds(tcg_ctx, tcg_res[pass], tcg_op, uc->cpu_env);
             tcg_temp_free_i32(tcg_ctx, tcg_op);
         }
         for (pass = 0; pass < 2; pass++) {
@@ -11148,7 +11185,7 @@ static void handle_2misc_widening(DisasContext *s, int opcode, bool is_q,
 
             read_vec_element_i32(s, tcg_res[pass], rn, srcelt + pass, MO_16);
             gen_helper_vfp_fcvt_f16_to_f32(tcg_ctx, tcg_res[pass], tcg_res[pass],
-                                           tcg_ctx->cpu_env);
+                                           uc->cpu_env);
         }
         for (pass = 0; pass < 4; pass++) {
             write_vec_element_i32(s, tcg_res[pass], rd, pass, MO_32);
@@ -11341,7 +11378,8 @@ static void handle_shll(DisasContext *s, bool is_q, int size, int rn, int rd)
  */
 static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     int size = extract32(insn, 22, 2);
     int opcode = extract32(insn, 12, 5);
     bool u = extract32(insn, 29, 1);
@@ -11684,9 +11722,9 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
                     break;
                 case 0x7: /* SQABS, SQNEG */
                     if (u) {
-                        gen_helper_neon_qneg_s32(tcg_ctx, tcg_res, tcg_ctx->cpu_env, tcg_op);
+                        gen_helper_neon_qneg_s32(tcg_ctx, tcg_res, uc->cpu_env, tcg_op);
                     } else {
-                        gen_helper_neon_qabs_s32(tcg_ctx, tcg_res, tcg_ctx->cpu_env, tcg_op);
+                        gen_helper_neon_qabs_s32(tcg_ctx, tcg_res, uc->cpu_env, tcg_op);
                     }
                     break;
                 case 0xb: /* ABS, NEG */
@@ -11707,7 +11745,7 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
                     gen_helper_vfp_negs(tcg_ctx, tcg_res, tcg_op);
                     break;
                 case 0x7f: /* FSQRT */
-                    gen_helper_vfp_sqrts(tcg_ctx, tcg_res, tcg_op, tcg_ctx->cpu_env);
+                    gen_helper_vfp_sqrts(tcg_ctx, tcg_res, tcg_op, uc->cpu_env);
                     break;
                 case 0x1a: /* FCVTNS */
                 case 0x1b: /* FCVTMS */
@@ -11771,7 +11809,7 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
                         { gen_helper_neon_qabs_s16, gen_helper_neon_qneg_s16 },
                     };
                     genfn = fns[size][u];
-                    genfn(tcg_ctx, tcg_res, tcg_ctx->cpu_env, tcg_op);
+                    genfn(tcg_ctx, tcg_res, uc->cpu_env, tcg_op);
                     break;
                 }
                 case 0x8: /* CMGT, CMGE */
@@ -12173,7 +12211,8 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
  */
 static void disas_simd_indexed(DisasContext *s, uint32_t insn)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     /* This encoding has two kinds of instruction:
      *  normal, where we perform elt x idxelt => elt for each
      *     element in the vector
@@ -12519,19 +12558,19 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
                 break;
             case 0x0c: /* SQDMULH */
                 if (size == 1) {
-                    gen_helper_neon_qdmulh_s16(tcg_ctx, tcg_res, tcg_ctx->cpu_env,
+                    gen_helper_neon_qdmulh_s16(tcg_ctx, tcg_res, uc->cpu_env,
                                                tcg_op, tcg_idx);
                 } else {
-                    gen_helper_neon_qdmulh_s32(tcg_ctx, tcg_res, tcg_ctx->cpu_env,
+                    gen_helper_neon_qdmulh_s32(tcg_ctx, tcg_res, uc->cpu_env,
                                                tcg_op, tcg_idx);
                 }
                 break;
             case 0x0d: /* SQRDMULH */
                 if (size == 1) {
-                    gen_helper_neon_qrdmulh_s16(tcg_ctx, tcg_res, tcg_ctx->cpu_env,
+                    gen_helper_neon_qrdmulh_s16(tcg_ctx, tcg_res, uc->cpu_env,
                                                 tcg_op, tcg_idx);
                 } else {
-                    gen_helper_neon_qrdmulh_s32(tcg_ctx, tcg_res, tcg_ctx->cpu_env,
+                    gen_helper_neon_qrdmulh_s32(tcg_ctx, tcg_res, uc->cpu_env,
                                                 tcg_op, tcg_idx);
                 }
                 break;
@@ -12539,10 +12578,10 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
                 read_vec_element_i32(s, tcg_res, rd, pass,
                                      is_scalar ? size : MO_32);
                 if (size == 1) {
-                    gen_helper_neon_qrdmlah_s16(tcg_ctx, tcg_res, tcg_ctx->cpu_env,
+                    gen_helper_neon_qrdmlah_s16(tcg_ctx, tcg_res, uc->cpu_env,
                                                 tcg_op, tcg_idx, tcg_res);
                 } else {
-                    gen_helper_neon_qrdmlah_s32(tcg_ctx, tcg_res, tcg_ctx->cpu_env,
+                    gen_helper_neon_qrdmlah_s32(tcg_ctx, tcg_res, uc->cpu_env,
                                                 tcg_op, tcg_idx, tcg_res);
                 }
                 break;
@@ -12550,10 +12589,10 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
                 read_vec_element_i32(s, tcg_res, rd, pass,
                                      is_scalar ? size : MO_32);
                 if (size == 1) {
-                    gen_helper_neon_qrdmlsh_s16(tcg_ctx, tcg_res, tcg_ctx->cpu_env,
+                    gen_helper_neon_qrdmlsh_s16(tcg_ctx, tcg_res, uc->cpu_env,
                                                 tcg_op, tcg_idx, tcg_res);
                 } else {
-                    gen_helper_neon_qrdmlsh_s32(tcg_ctx, tcg_res, tcg_ctx->cpu_env,
+                    gen_helper_neon_qrdmlsh_s32(tcg_ctx, tcg_res, uc->cpu_env,
                                                 tcg_op, tcg_idx, tcg_res);
                 }
                 break;
@@ -12616,7 +12655,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
 
                 if (satop) {
                     /* saturating, doubling */
-                    gen_helper_neon_addl_saturate_s64(tcg_ctx, tcg_passres, tcg_ctx->cpu_env,
+                    gen_helper_neon_addl_saturate_s64(tcg_ctx, tcg_passres, uc->cpu_env,
                                                       tcg_passres, tcg_passres);
                 }
 
@@ -12638,7 +12677,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
                     tcg_gen_neg_i64(tcg_ctx, tcg_passres, tcg_passres);
                     /* fall through */
                 case 0x3: /* SQDMLAL, SQDMLAL2 */
-                    gen_helper_neon_addl_saturate_s64(tcg_ctx, tcg_res[pass], tcg_ctx->cpu_env,
+                    gen_helper_neon_addl_saturate_s64(tcg_ctx, tcg_res[pass], uc->cpu_env,
                                                       tcg_res[pass],
                                                       tcg_passres);
                     break;
@@ -12690,7 +12729,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
                     gen_helper_neon_mull_u16(tcg_ctx, tcg_passres, tcg_op, tcg_idx);
                 }
                 if (satop) {
-                    gen_helper_neon_addl_saturate_s32(tcg_ctx, tcg_passres, tcg_ctx->cpu_env,
+                    gen_helper_neon_addl_saturate_s32(tcg_ctx, tcg_passres, uc->cpu_env,
                                                       tcg_passres, tcg_passres);
                 }
                 tcg_temp_free_i32(tcg_ctx, tcg_op);
@@ -12715,7 +12754,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
                     gen_helper_neon_negl_u32(tcg_ctx, tcg_passres, tcg_passres);
                     /* fall through */
                 case 0x3: /* SQDMLAL, SQDMLAL2 */
-                    gen_helper_neon_addl_saturate_s32(tcg_ctx, tcg_res[pass], tcg_ctx->cpu_env,
+                    gen_helper_neon_addl_saturate_s32(tcg_ctx, tcg_res[pass], uc->cpu_env,
                                                       tcg_res[pass],
                                                       tcg_passres);
                     break;
@@ -13496,11 +13535,12 @@ static bool aarch64_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,
                                         const CPUBreakpoint *bp)
 {
     DisasContext *dc = container_of(dcbase, DisasContext, base);
-    TCGContext *tcg_ctx = cpu->uc->tcg_ctx;
+    struct uc_struct *uc = cpu->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
 
     if (bp->flags & BP_CPU) {
         gen_a64_set_pc_im(dc, dc->pc);
-        gen_helper_check_breakpoints(tcg_ctx, tcg_ctx->cpu_env);
+        gen_helper_check_breakpoints(tcg_ctx, uc->cpu_env);
         /* End the TB early; it likely won't be executed */
         dc->base.is_jmp = DISAS_TOO_MANY;
     } else {
@@ -13548,7 +13588,8 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
 static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
 {
     DisasContext *dc = container_of(dcbase, DisasContext, base);
-    TCGContext *tcg_ctx = cpu->uc->tcg_ctx;
+    struct uc_struct *uc = cpu->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
 
     if (unlikely(dc->base.singlestep_enabled || dc->ss_active)) {
         /* Note that this means single stepping WFI doesn't halt the CPU.
@@ -13592,11 +13633,11 @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
             break;
         case DISAS_WFE:
             gen_a64_set_pc_im(dc, dc->pc);
-            gen_helper_wfe(tcg_ctx, tcg_ctx->cpu_env);
+            gen_helper_wfe(tcg_ctx, uc->cpu_env);
             break;
         case DISAS_YIELD:
             gen_a64_set_pc_im(dc, dc->pc);
-            gen_helper_yield(tcg_ctx, tcg_ctx->cpu_env);
+            gen_helper_yield(tcg_ctx, uc->cpu_env);
             break;
         case DISAS_WFI:
         {
@@ -13606,7 +13647,7 @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
             TCGv_i32 tmp = tcg_const_i32(tcg_ctx, 4);
 
             gen_a64_set_pc_im(dc, dc->pc);
-            gen_helper_wfi(tcg_ctx, tcg_ctx->cpu_env, tmp);
+            gen_helper_wfi(tcg_ctx, uc->cpu_env, tmp);
             tcg_temp_free_i32(tcg_ctx, tmp);
             /* The helper doesn't necessarily throw an exception, but we
              * must go back to the main loop to check for interrupts anyway.
diff --git a/qemu/target/arm/translate.c b/qemu/target/arm/translate.c
index a3e91d4b..3310f90d 100644
--- a/qemu/target/arm/translate.c
+++ b/qemu/target/arm/translate.c
@@ -71,23 +71,21 @@ void arm_translate_init(struct uc_struct *uc)
 {
     int i;
     TCGContext *tcg_ctx = uc->tcg_ctx;
-
-    tcg_ctx->cpu_env = tcg_global_reg_new_ptr(uc->tcg_ctx, TCG_AREG0, "env");
-    tcg_ctx->tcg_env = tcg_ctx->cpu_env;
+    TCGv_env cpu_env = uc->cpu_env;
 
     for (i = 0; i < 16; i++) {
-        tcg_ctx->cpu_R[i] = tcg_global_mem_new_i32(uc->tcg_ctx, tcg_ctx->cpu_env,
+        tcg_ctx->cpu_R[i] = tcg_global_mem_new_i32(tcg_ctx, cpu_env,
                                           offsetof(CPUARMState, regs[i]),
                                           regnames[i]);
     }
-    tcg_ctx->cpu_CF = tcg_global_mem_new_i32(uc->tcg_ctx, tcg_ctx->cpu_env, offsetof(CPUARMState, CF), "CF");
-    tcg_ctx->cpu_NF = tcg_global_mem_new_i32(uc->tcg_ctx, tcg_ctx->cpu_env, offsetof(CPUARMState, NF), "NF");
-    tcg_ctx->cpu_VF = tcg_global_mem_new_i32(uc->tcg_ctx, tcg_ctx->cpu_env, offsetof(CPUARMState, VF), "VF");
-    tcg_ctx->cpu_ZF = tcg_global_mem_new_i32(uc->tcg_ctx, tcg_ctx->cpu_env, offsetof(CPUARMState, ZF), "ZF");
+    tcg_ctx->cpu_CF = tcg_global_mem_new_i32(tcg_ctx, cpu_env, offsetof(CPUARMState, CF), "CF");
+    tcg_ctx->cpu_NF = tcg_global_mem_new_i32(tcg_ctx, cpu_env, offsetof(CPUARMState, NF), "NF");
+    tcg_ctx->cpu_VF = tcg_global_mem_new_i32(tcg_ctx, cpu_env, offsetof(CPUARMState, VF), "VF");
+    tcg_ctx->cpu_ZF = tcg_global_mem_new_i32(tcg_ctx, cpu_env, offsetof(CPUARMState, ZF), "ZF");
 
-    tcg_ctx->cpu_exclusive_addr = tcg_global_mem_new_i64(uc->tcg_ctx, tcg_ctx->cpu_env,
+    tcg_ctx->cpu_exclusive_addr = tcg_global_mem_new_i64(tcg_ctx, cpu_env,
         offsetof(CPUARMState, exclusive_addr), "exclusive_addr");
-    tcg_ctx->cpu_exclusive_val = tcg_global_mem_new_i64(uc->tcg_ctx, tcg_ctx->cpu_env,
+    tcg_ctx->cpu_exclusive_val = tcg_global_mem_new_i64(tcg_ctx, cpu_env,
         offsetof(CPUARMState, exclusive_val), "exclusive_val");
 
     a64_translate_init(uc);
@@ -174,7 +172,7 @@ static inline TCGv_i32 load_cpu_offset(struct uc_struct *uc, int offset)
 {
     TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv_i32 tmp = tcg_temp_new_i32(tcg_ctx);
-    tcg_gen_ld_i32(tcg_ctx, tmp, tcg_ctx->cpu_env, offset);
+    tcg_gen_ld_i32(tcg_ctx, tmp, uc->cpu_env, offset);
     return tmp;
 }
 
@@ -182,7 +180,7 @@ static inline TCGv_i32 load_cpu_offset(struct uc_struct *uc, int offset)
 
 static inline void store_cpu_offset(TCGContext *tcg_ctx, TCGv_i32 var, int offset)
 {
-    tcg_gen_st_i32(tcg_ctx, var, tcg_ctx->cpu_env, offset);
+    tcg_gen_st_i32(tcg_ctx, var, tcg_ctx->uc->cpu_env, offset);
     tcg_temp_free_i32(tcg_ctx, var);
 }
 
@@ -245,9 +243,10 @@ static void store_reg(DisasContext *s, int reg, TCGv_i32 var)
 
 static inline void gen_set_cpsr(DisasContext *s, TCGv_i32 var, uint32_t mask)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv_i32 tmp_mask = tcg_const_i32(tcg_ctx, mask);
-    gen_helper_cpsr_write(tcg_ctx, tcg_ctx->cpu_env, var, tmp_mask);
+    gen_helper_cpsr_write(tcg_ctx, uc->cpu_env, var, tmp_mask);
     tcg_temp_free_i32(tcg_ctx, tmp_mask);
 }
 /* Set NZCV flags from the high 4 bits of var.  */
@@ -255,22 +254,24 @@ static inline void gen_set_cpsr(DisasContext *s, TCGv_i32 var, uint32_t mask)
 
 static void gen_exception_internal(DisasContext *s, int excp)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv_i32 tcg_excp = tcg_const_i32(tcg_ctx, excp);
 
     assert(excp_is_internal(excp));
-    gen_helper_exception_internal(tcg_ctx, tcg_ctx->cpu_env, tcg_excp);
+    gen_helper_exception_internal(tcg_ctx, uc->cpu_env, tcg_excp);
     tcg_temp_free_i32(tcg_ctx, tcg_excp);
 }
 
 static void gen_exception(DisasContext *s, int excp, uint32_t syndrome, uint32_t target_el)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv_i32 tcg_excp = tcg_const_i32(tcg_ctx, excp);
     TCGv_i32 tcg_syn = tcg_const_i32(tcg_ctx, syndrome);
     TCGv_i32 tcg_el = tcg_const_i32(tcg_ctx, target_el);
 
-    gen_helper_exception_with_syndrome(tcg_ctx, tcg_ctx->cpu_env, tcg_excp,
+    gen_helper_exception_with_syndrome(tcg_ctx, uc->cpu_env, tcg_excp,
                                        tcg_syn, tcg_el);
 
     tcg_temp_free_i32(tcg_ctx, tcg_el);
@@ -280,13 +281,14 @@ static void gen_exception(DisasContext *s, int excp, uint32_t syndrome, uint32_t
 
 static void gen_ss_advance(DisasContext *s)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     /* If the singlestep state is Active-not-pending, advance to
      * Active-pending.
      */
     if (s->ss_active) {
         s->pstate_ss = 0;
-        gen_helper_clear_pstate_ss(tcg_ctx, tcg_ctx->cpu_env);
+        gen_helper_clear_pstate_ss(tcg_ctx, uc->cpu_env);
     }
 }
 
@@ -693,13 +695,16 @@ static inline void gen_arm_shift_im(DisasContext *s, TCGv_i32 var, int shiftop,
 static inline void gen_arm_shift_reg(DisasContext *s, TCGv_i32 var, int shiftop,
                                      TCGv_i32 shift, int flags)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
+    TCGv_env cpu_env = uc->cpu_env;
+
     if (flags) {
         switch (shiftop) {
-        case 0: gen_helper_shl_cc(tcg_ctx, var, tcg_ctx->cpu_env, var, shift); break;
-        case 1: gen_helper_shr_cc(tcg_ctx, var, tcg_ctx->cpu_env, var, shift); break;
-        case 2: gen_helper_sar_cc(tcg_ctx, var, tcg_ctx->cpu_env, var, shift); break;
-        case 3: gen_helper_ror_cc(tcg_ctx, var, tcg_ctx->cpu_env, var, shift); break;
+        case 0: gen_helper_shl_cc(tcg_ctx, var, cpu_env, var, shift); break;
+        case 1: gen_helper_shr_cc(tcg_ctx, var, cpu_env, var, shift); break;
+        case 2: gen_helper_sar_cc(tcg_ctx, var, cpu_env, var, shift); break;
+        case 3: gen_helper_ror_cc(tcg_ctx, var, cpu_env, var, shift); break;
         }
     } else {
         switch (shiftop) {
@@ -730,20 +735,21 @@ static inline void gen_arm_shift_reg(DisasContext *s, TCGv_i32 var, int shiftop,
     }
 static void gen_arm_parallel_addsub(DisasContext *s, int op1, int op2, TCGv_i32 a, TCGv_i32 b)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv_ptr tmp;
 
     switch (op1) {
 #define gen_pas_helper(name) glue(gen_helper_,name)(tcg_ctx, a, a, b, tmp)
     case 1:
         tmp = tcg_temp_new_ptr(tcg_ctx);
-        tcg_gen_addi_ptr(tcg_ctx, tmp, tcg_ctx->cpu_env, offsetof(CPUARMState, GE));
+        tcg_gen_addi_ptr(tcg_ctx, tmp, uc->cpu_env, offsetof(CPUARMState, GE));
         PAS_OP(s)
         tcg_temp_free_ptr(tcg_ctx, tmp);
         break;
     case 5:
         tmp = tcg_temp_new_ptr(tcg_ctx);
-        tcg_gen_addi_ptr(tcg_ctx, tmp, tcg_ctx->cpu_env, offsetof(CPUARMState, GE));
+        tcg_gen_addi_ptr(tcg_ctx, tmp, uc->cpu_env, offsetof(CPUARMState, GE));
         PAS_OP(u)
         tcg_temp_free_ptr(tcg_ctx, tmp);
         break;
@@ -778,20 +784,21 @@ static void gen_arm_parallel_addsub(DisasContext *s, int op1, int op2, TCGv_i32
     }
 static void gen_thumb2_parallel_addsub(DisasContext *s, int op1, int op2, TCGv_i32 a, TCGv_i32 b)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv_ptr tmp;
 
     switch (op2) {
 #define gen_pas_helper(name) glue(gen_helper_,name)(tcg_ctx, a, a, b, tmp)
     case 0:
         tmp = tcg_temp_new_ptr(tcg_ctx);
-        tcg_gen_addi_ptr(tcg_ctx, tmp, tcg_ctx->cpu_env, offsetof(CPUARMState, GE));
+        tcg_gen_addi_ptr(tcg_ctx, tmp, uc->cpu_env, offsetof(CPUARMState, GE));
         PAS_OP(s)
         tcg_temp_free_ptr(tcg_ctx, tmp);
         break;
     case 4:
         tmp = tcg_temp_new_ptr(tcg_ctx);
-        tcg_gen_addi_ptr(tcg_ctx, tmp, tcg_ctx->cpu_env, offsetof(CPUARMState, GE));
+        tcg_gen_addi_ptr(tcg_ctx, tmp, uc->cpu_env, offsetof(CPUARMState, GE));
         PAS_OP(u)
         tcg_temp_free_ptr(tcg_ctx, tmp);
         break;
@@ -966,13 +973,14 @@ static inline void gen_set_pc_im(DisasContext *s, target_ulong val)
 static inline void gen_bx_im(DisasContext *s, uint32_t addr)
 {
     TCGv_i32 tmp;
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
 
     s->base.is_jmp = DISAS_JUMP;
     if (s->thumb != (addr & 1)) {
         tmp = tcg_temp_new_i32(tcg_ctx);
         tcg_gen_movi_i32(tcg_ctx, tmp, addr & 1);
-        tcg_gen_st_i32(tcg_ctx, tmp, tcg_ctx->cpu_env, offsetof(CPUARMState, thumb));
+        tcg_gen_st_i32(tcg_ctx, tmp, uc->cpu_env, offsetof(CPUARMState, thumb));
         tcg_temp_free_i32(tcg_ctx, tmp);
     }
     tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_R[15], addr & ~1);
@@ -1048,7 +1056,8 @@ static inline void gen_bx_excret_final_code(DisasContext *s)
 
 static inline void gen_bxns(DisasContext *s, int rm)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv_i32 var = load_reg(s, rm);
 
     /* The bxns helper may raise an EXCEPTION_EXIT exception, so in theory
@@ -1061,14 +1070,15 @@ static inline void gen_bxns(DisasContext *s, int rm)
      *    is correct in the non-UNPREDICTABLE cases, and we can choose
      *    "zeroes the IT bits" as our UNPREDICTABLE behaviour otherwise.
      */
-    gen_helper_v7m_bxns(tcg_ctx, tcg_ctx->cpu_env, var);
+    gen_helper_v7m_bxns(tcg_ctx, uc->cpu_env, var);
     tcg_temp_free_i32(tcg_ctx, var);
     s->base.is_jmp = DISAS_EXIT;
 }
 
 static inline void gen_blxns(DisasContext *s, int rm)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv_i32 var = load_reg(s, rm);
 
     /* We don't need to sync condexec state, for the same reason as bxns.
@@ -1076,7 +1086,7 @@ static inline void gen_blxns(DisasContext *s, int rm)
      * The blxns helper may throw an exception.
      */
     gen_set_pc_im(s, s->pc);
-    gen_helper_v7m_blxns(tcg_ctx, tcg_ctx->cpu_env, var);
+    gen_helper_v7m_blxns(tcg_ctx, uc->cpu_env, var);
     tcg_temp_free_i32(tcg_ctx, var);
     s->base.is_jmp = DISAS_EXIT;
 }
@@ -1242,13 +1252,15 @@ DO_GEN_ST(32, MO_UL)
 
 static inline void gen_hvc(DisasContext *s, int imm16)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
+
     /* The pre HVC helper handles cases when HVC gets trapped
      * as an undefined insn by runtime configuration (ie before
      * the insn really executes).
      */
     gen_set_pc_im(s, s->pc - 4);
-    gen_helper_pre_hvc(tcg_ctx, tcg_ctx->cpu_env);
+    gen_helper_pre_hvc(tcg_ctx, uc->cpu_env);
     /* Otherwise we will treat this as a real exception which
      * happens after execution of the insn. (The distinction matters
      * for the PC value reported to the exception handler and also
@@ -1265,11 +1277,12 @@ static inline void gen_smc(DisasContext *s)
      * the insn executes.
      */
     TCGv_i32 tmp;
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
 
     gen_set_pc_im(s, s->pc - 4);
     tmp = tcg_const_i32(tcg_ctx, syn_aa32_smc());
-    gen_helper_pre_smc(tcg_ctx, tcg_ctx->cpu_env, tmp);
+    gen_helper_pre_smc(tcg_ctx, uc->cpu_env, tmp);
     tcg_temp_free_i32(tcg_ctx, tmp);
     gen_set_pc_im(s, s->pc);
     s->base.is_jmp = DISAS_SMC;
@@ -1387,7 +1400,8 @@ static inline void gen_add_datah_offset(DisasContext *s, unsigned int insn,
 
 static TCGv_ptr get_fpstatus_ptr(DisasContext *s, int neon)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv_ptr statusptr = tcg_temp_new_ptr(tcg_ctx);
     int offset;
     if (neon) {
@@ -1395,7 +1409,7 @@ static TCGv_ptr get_fpstatus_ptr(DisasContext *s, int neon)
     } else {
         offset = offsetof(CPUARMState, vfp.fp_status);
     }
-    tcg_gen_addi_ptr(tcg_ctx, statusptr, tcg_ctx->cpu_env, offset);
+    tcg_gen_addi_ptr(tcg_ctx, statusptr, uc->cpu_env, offset);
     return statusptr;
 }
 
@@ -1463,29 +1477,35 @@ static inline void gen_vfp_neg(DisasContext *s, int dp)
 
 static inline void gen_vfp_sqrt(DisasContext *s, int dp)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
+
     if (dp)
-        gen_helper_vfp_sqrtd(tcg_ctx, tcg_ctx->cpu_F0d, tcg_ctx->cpu_F0d, tcg_ctx->cpu_env);
+        gen_helper_vfp_sqrtd(tcg_ctx, tcg_ctx->cpu_F0d, tcg_ctx->cpu_F0d, uc->cpu_env);
     else
-        gen_helper_vfp_sqrts(tcg_ctx, tcg_ctx->cpu_F0s, tcg_ctx->cpu_F0s, tcg_ctx->cpu_env);
+        gen_helper_vfp_sqrts(tcg_ctx, tcg_ctx->cpu_F0s, tcg_ctx->cpu_F0s, uc->cpu_env);
 }
 
 static inline void gen_vfp_cmp(DisasContext *s, int dp)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
+
     if (dp)
-        gen_helper_vfp_cmpd(tcg_ctx, tcg_ctx->cpu_F0d, tcg_ctx->cpu_F1d, tcg_ctx->cpu_env);
+        gen_helper_vfp_cmpd(tcg_ctx, tcg_ctx->cpu_F0d, tcg_ctx->cpu_F1d, uc->cpu_env);
     else
-        gen_helper_vfp_cmps(tcg_ctx, tcg_ctx->cpu_F0s, tcg_ctx->cpu_F1s, tcg_ctx->cpu_env);
+        gen_helper_vfp_cmps(tcg_ctx, tcg_ctx->cpu_F0s, tcg_ctx->cpu_F1s, uc->cpu_env);
 }
 
 static inline void gen_vfp_cmpe(DisasContext *s, int dp)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
+
     if (dp)
-        gen_helper_vfp_cmped(tcg_ctx, tcg_ctx->cpu_F0d, tcg_ctx->cpu_F1d, tcg_ctx->cpu_env);
+        gen_helper_vfp_cmped(tcg_ctx, tcg_ctx->cpu_F0d, tcg_ctx->cpu_F1d, uc->cpu_env);
     else
-        gen_helper_vfp_cmpes(tcg_ctx, tcg_ctx->cpu_F0s, tcg_ctx->cpu_F1s, tcg_ctx->cpu_env);
+        gen_helper_vfp_cmpes(tcg_ctx, tcg_ctx->cpu_F0s, tcg_ctx->cpu_F1s, uc->cpu_env);
 }
 
 static inline void gen_vfp_F1_ld0(DisasContext *s, int dp)
@@ -1607,30 +1627,30 @@ neon_reg_offset (int reg, int n)
 static TCGv_i32 neon_load_reg(TCGContext *tcg_ctx, int reg, int pass)
 {
     TCGv_i32 tmp = tcg_temp_new_i32(tcg_ctx);
-    tcg_gen_ld_i32(tcg_ctx, tmp, tcg_ctx->cpu_env, neon_reg_offset(reg, pass));
+    tcg_gen_ld_i32(tcg_ctx, tmp, tcg_ctx->uc->cpu_env, neon_reg_offset(reg, pass));
     return tmp;
 }
 
 static void neon_store_reg(TCGContext *tcg_ctx, int reg, int pass, TCGv_i32 var)
 {
-    tcg_gen_st_i32(tcg_ctx, var, tcg_ctx->cpu_env, neon_reg_offset(reg, pass));
+    tcg_gen_st_i32(tcg_ctx, var, tcg_ctx->uc->cpu_env, neon_reg_offset(reg, pass));
     tcg_temp_free_i32(tcg_ctx, var);
 }
 
 static inline void neon_load_reg64(TCGContext *tcg_ctx, TCGv_i64 var, int reg)
 {
-    tcg_gen_ld_i64(tcg_ctx, var, tcg_ctx->cpu_env, vfp_reg_offset(1, reg));
+    tcg_gen_ld_i64(tcg_ctx, var, tcg_ctx->uc->cpu_env, vfp_reg_offset(1, reg));
 }
 
 static inline void neon_store_reg64(TCGContext *tcg_ctx, TCGv_i64 var, int reg)
 {
-    tcg_gen_st_i64(tcg_ctx, var, tcg_ctx->cpu_env, vfp_reg_offset(1, reg));
+    tcg_gen_st_i64(tcg_ctx, var, tcg_ctx->uc->cpu_env, vfp_reg_offset(1, reg));
 }
 
 static TCGv_ptr vfp_reg_ptr(TCGContext *tcg_ctx, bool dp, int reg)
 {
     TCGv_ptr ret = tcg_temp_new_ptr(tcg_ctx);
-    tcg_gen_addi_ptr(tcg_ctx, ret, tcg_ctx->cpu_env, vfp_reg_offset(dp, reg));
+    tcg_gen_addi_ptr(tcg_ctx, ret, tcg_ctx->uc->cpu_env, vfp_reg_offset(dp, reg));
     return ret;
 }
 
@@ -1641,57 +1661,69 @@ static TCGv_ptr vfp_reg_ptr(TCGContext *tcg_ctx, bool dp, int reg)
 
 static inline void gen_mov_F0_vreg(DisasContext *s, int dp, int reg)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
+
     if (dp)
-        tcg_gen_ld_f64(tcg_ctx, tcg_ctx->cpu_F0d, tcg_ctx->cpu_env, vfp_reg_offset(dp, reg));
+        tcg_gen_ld_f64(tcg_ctx, tcg_ctx->cpu_F0d, uc->cpu_env, vfp_reg_offset(dp, reg));
     else
-        tcg_gen_ld_f32(tcg_ctx, tcg_ctx->cpu_F0s, tcg_ctx->cpu_env, vfp_reg_offset(dp, reg));
+        tcg_gen_ld_f32(tcg_ctx, tcg_ctx->cpu_F0s, uc->cpu_env, vfp_reg_offset(dp, reg));
 }
 
 static inline void gen_mov_F1_vreg(DisasContext *s, int dp, int reg)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
+
     if (dp)
-        tcg_gen_ld_f64(tcg_ctx, tcg_ctx->cpu_F1d, tcg_ctx->cpu_env, vfp_reg_offset(dp, reg));
+        tcg_gen_ld_f64(tcg_ctx, tcg_ctx->cpu_F1d, uc->cpu_env, vfp_reg_offset(dp, reg));
     else
-        tcg_gen_ld_f32(tcg_ctx, tcg_ctx->cpu_F1s, tcg_ctx->cpu_env, vfp_reg_offset(dp, reg));
+        tcg_gen_ld_f32(tcg_ctx, tcg_ctx->cpu_F1s, uc->cpu_env, vfp_reg_offset(dp, reg));
 }
 
 static inline void gen_mov_vreg_F0(DisasContext *s, int dp, int reg)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
+
     if (dp)
-        tcg_gen_st_f64(tcg_ctx, tcg_ctx->cpu_F0d, tcg_ctx->cpu_env, vfp_reg_offset(dp, reg));
+        tcg_gen_st_f64(tcg_ctx, tcg_ctx->cpu_F0d, uc->cpu_env, vfp_reg_offset(dp, reg));
     else
-        tcg_gen_st_f32(tcg_ctx, tcg_ctx->cpu_F0s, tcg_ctx->cpu_env, vfp_reg_offset(dp, reg));
+        tcg_gen_st_f32(tcg_ctx, tcg_ctx->cpu_F0s, uc->cpu_env, vfp_reg_offset(dp, reg));
 }
 
 #define ARM_CP_RW_BIT   (1 << 20)
 
 static inline void iwmmxt_load_reg(DisasContext *s, TCGv_i64 var, int reg)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
-    tcg_gen_ld_i64(tcg_ctx, var, tcg_ctx->cpu_env, offsetof(CPUARMState, iwmmxt.regs[reg]));
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
+
+    tcg_gen_ld_i64(tcg_ctx, var, uc->cpu_env, offsetof(CPUARMState, iwmmxt.regs[reg]));
 }
 
 static inline void iwmmxt_store_reg(DisasContext *s, TCGv_i64 var, int reg)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
-    tcg_gen_st_i64(tcg_ctx, var, tcg_ctx->cpu_env, offsetof(CPUARMState, iwmmxt.regs[reg]));
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
+
+    tcg_gen_st_i64(tcg_ctx, var, uc->cpu_env, offsetof(CPUARMState, iwmmxt.regs[reg]));
 }
 
 static inline TCGv_i32 iwmmxt_load_creg(DisasContext *s, int reg)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv_i32 var = tcg_temp_new_i32(tcg_ctx);
-    tcg_gen_ld_i32(tcg_ctx, var, tcg_ctx->cpu_env, offsetof(CPUARMState, iwmmxt.cregs[reg]));
+    tcg_gen_ld_i32(tcg_ctx, var, uc->cpu_env, offsetof(CPUARMState, iwmmxt.cregs[reg]));
     return var;
 }
 
 static inline void iwmmxt_store_creg(DisasContext *s, int reg, TCGv_i32 var)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
-    tcg_gen_st_i32(tcg_ctx, var, tcg_ctx->cpu_env, offsetof(CPUARMState, iwmmxt.cregs[reg]));
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
+    tcg_gen_st_i32(tcg_ctx, var, uc->cpu_env, offsetof(CPUARMState, iwmmxt.cregs[reg]));
     tcg_temp_free_i32(tcg_ctx, var);
 }
 
@@ -1739,9 +1771,10 @@ static inline void gen_op_iwmmxt_##name##_M0_wRn(DisasContext *s, int rn) \
 #define IWMMXT_OP_ENV(name) \
 static inline void gen_op_iwmmxt_##name##_M0_wRn(DisasContext *s, int rn) \
 { \
-    TCGContext *tcg_ctx = s->uc->tcg_ctx; \
+    struct uc_struct *uc = s->uc; \
+    TCGContext *tcg_ctx = uc->tcg_ctx; \
     iwmmxt_load_reg(s, tcg_ctx->cpu_V1, rn); \
-    gen_helper_iwmmxt_##name(tcg_ctx, tcg_ctx->cpu_M0, tcg_ctx->cpu_env, tcg_ctx->cpu_M0, tcg_ctx->cpu_V1); \
+    gen_helper_iwmmxt_##name(tcg_ctx, tcg_ctx->cpu_M0, uc->cpu_env, tcg_ctx->cpu_M0, tcg_ctx->cpu_V1); \
 }
 
 #define IWMMXT_OP_ENV_SIZE(name) \
@@ -1752,8 +1785,9 @@ IWMMXT_OP_ENV(name##l)
 #define IWMMXT_OP_ENV1(name) \
 static inline void gen_op_iwmmxt_##name##_M0(DisasContext *s) \
 { \
-    TCGContext *tcg_ctx = s->uc->tcg_ctx; \
-    gen_helper_iwmmxt_##name(tcg_ctx, tcg_ctx->cpu_M0, tcg_ctx->cpu_env, tcg_ctx->cpu_M0); \
+    struct uc_struct *uc = s->uc; \
+    TCGContext *tcg_ctx = uc->tcg_ctx; \
+    gen_helper_iwmmxt_##name(tcg_ctx, tcg_ctx->cpu_M0, uc->cpu_env, tcg_ctx->cpu_M0); \
 }
 
 IWMMXT_OP(maddsq)
@@ -1908,7 +1942,8 @@ static inline int gen_iwmmxt_shift(DisasContext *s, uint32_t insn, uint32_t mask
    (ie. an undefined instruction).  */
 static int disas_iwmmxt_insn(DisasContext *s, uint32_t insn)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     int rd, wrd;
     int rdhi, rdlo, rd0, rd1, i;
     TCGv_i32 addr;
@@ -2553,13 +2588,13 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_t insn)
         }
         switch ((insn >> 22) & 3) {
         case 1:
-            gen_helper_iwmmxt_srlw(tcg_ctx, tcg_ctx->cpu_M0, tcg_ctx->cpu_env, tcg_ctx->cpu_M0, tmp);
+            gen_helper_iwmmxt_srlw(tcg_ctx, tcg_ctx->cpu_M0, uc->cpu_env, tcg_ctx->cpu_M0, tmp);
             break;
         case 2:
-            gen_helper_iwmmxt_srll(tcg_ctx, tcg_ctx->cpu_M0, tcg_ctx->cpu_env, tcg_ctx->cpu_M0, tmp);
+            gen_helper_iwmmxt_srll(tcg_ctx, tcg_ctx->cpu_M0, uc->cpu_env, tcg_ctx->cpu_M0, tmp);
             break;
         case 3:
-            gen_helper_iwmmxt_srlq(tcg_ctx, tcg_ctx->cpu_M0, tcg_ctx->cpu_env, tcg_ctx->cpu_M0, tmp);
+            gen_helper_iwmmxt_srlq(tcg_ctx, tcg_ctx->cpu_M0, uc->cpu_env, tcg_ctx->cpu_M0, tmp);
             break;
         }
         tcg_temp_free_i32(tcg_ctx, tmp);
@@ -2581,13 +2616,13 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_t insn)
         }
         switch ((insn >> 22) & 3) {
         case 1:
-            gen_helper_iwmmxt_sraw(tcg_ctx, tcg_ctx->cpu_M0, tcg_ctx->cpu_env, tcg_ctx->cpu_M0, tmp);
+            gen_helper_iwmmxt_sraw(tcg_ctx, tcg_ctx->cpu_M0, uc->cpu_env, tcg_ctx->cpu_M0, tmp);
             break;
         case 2:
-            gen_helper_iwmmxt_sral(tcg_ctx, tcg_ctx->cpu_M0, tcg_ctx->cpu_env, tcg_ctx->cpu_M0, tmp);
+            gen_helper_iwmmxt_sral(tcg_ctx, tcg_ctx->cpu_M0, uc->cpu_env, tcg_ctx->cpu_M0, tmp);
             break;
         case 3:
-            gen_helper_iwmmxt_sraq(tcg_ctx, tcg_ctx->cpu_M0, tcg_ctx->cpu_env, tcg_ctx->cpu_M0, tmp);
+            gen_helper_iwmmxt_sraq(tcg_ctx, tcg_ctx->cpu_M0, uc->cpu_env, tcg_ctx->cpu_M0, tmp);
             break;
         }
         tcg_temp_free_i32(tcg_ctx, tmp);
@@ -2609,13 +2644,13 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_t insn)
         }
         switch ((insn >> 22) & 3) {
         case 1:
-            gen_helper_iwmmxt_sllw(tcg_ctx, tcg_ctx->cpu_M0, tcg_ctx->cpu_env, tcg_ctx->cpu_M0, tmp);
+            gen_helper_iwmmxt_sllw(tcg_ctx, tcg_ctx->cpu_M0, uc->cpu_env, tcg_ctx->cpu_M0, tmp);
             break;
         case 2:
-            gen_helper_iwmmxt_slll(tcg_ctx, tcg_ctx->cpu_M0, tcg_ctx->cpu_env, tcg_ctx->cpu_M0, tmp);
+            gen_helper_iwmmxt_slll(tcg_ctx, tcg_ctx->cpu_M0, uc->cpu_env, tcg_ctx->cpu_M0, tmp);
             break;
         case 3:
-            gen_helper_iwmmxt_sllq(tcg_ctx, tcg_ctx->cpu_M0, tcg_ctx->cpu_env, tcg_ctx->cpu_M0, tmp);
+            gen_helper_iwmmxt_sllq(tcg_ctx, tcg_ctx->cpu_M0, uc->cpu_env, tcg_ctx->cpu_M0, tmp);
             break;
         }
         tcg_temp_free_i32(tcg_ctx, tmp);
@@ -2637,21 +2672,21 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_t insn)
                 tcg_temp_free_i32(tcg_ctx, tmp);
                 return 1;
             }
-            gen_helper_iwmmxt_rorw(tcg_ctx, tcg_ctx->cpu_M0, tcg_ctx->cpu_env, tcg_ctx->cpu_M0, tmp);
+            gen_helper_iwmmxt_rorw(tcg_ctx, tcg_ctx->cpu_M0, uc->cpu_env, tcg_ctx->cpu_M0, tmp);
             break;
         case 2:
             if (gen_iwmmxt_shift(s, insn, 0x1f, tmp)) {
                 tcg_temp_free_i32(tcg_ctx, tmp);
                 return 1;
             }
-            gen_helper_iwmmxt_rorl(tcg_ctx, tcg_ctx->cpu_M0, tcg_ctx->cpu_env, tcg_ctx->cpu_M0, tmp);
+            gen_helper_iwmmxt_rorl(tcg_ctx, tcg_ctx->cpu_M0, uc->cpu_env, tcg_ctx->cpu_M0, tmp);
             break;
         case 3:
             if (gen_iwmmxt_shift(s, insn, 0x3f, tmp)) {
                 tcg_temp_free_i32(tcg_ctx, tmp);
                 return 1;
             }
-            gen_helper_iwmmxt_rorq(tcg_ctx, tcg_ctx->cpu_M0, tcg_ctx->cpu_env, tcg_ctx->cpu_M0, tmp);
+            gen_helper_iwmmxt_rorq(tcg_ctx, tcg_ctx->cpu_M0, uc->cpu_env, tcg_ctx->cpu_M0, tmp);
             break;
         }
         tcg_temp_free_i32(tcg_ctx, tmp);
@@ -2785,7 +2820,7 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_t insn)
         rd0 = (insn >> 16) & 0xf;
         gen_op_iwmmxt_movq_M0_wRn(s, rd0);
         tmp = tcg_const_i32(tcg_ctx, ((insn >> 16) & 0xf0) | (insn & 0x0f));
-        gen_helper_iwmmxt_shufh(tcg_ctx, tcg_ctx->cpu_M0, tcg_ctx->cpu_env, tcg_ctx->cpu_M0, tmp);
+        gen_helper_iwmmxt_shufh(tcg_ctx, tcg_ctx->cpu_M0, uc->cpu_env, tcg_ctx->cpu_M0, tmp);
         tcg_temp_free_i32(tcg_ctx, tmp);
         gen_op_iwmmxt_movq_wRn_M0(s, wrd);
         gen_op_iwmmxt_set_mup(s);
@@ -3091,7 +3126,8 @@ static TCGv_i32 gen_load_and_replicate(DisasContext *s, TCGv_i32 addr, int size)
 static int handle_vsel(DisasContext *s, uint32_t insn, uint32_t rd, uint32_t rn, uint32_t rm,
                        uint32_t dp)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     uint32_t cc = extract32(insn, 20, 2);
 
     if (dp) {
@@ -3112,8 +3148,8 @@ static int handle_vsel(DisasContext *s, uint32_t insn, uint32_t rd, uint32_t rn,
         tcg_gen_ext_i32_i64(tcg_ctx, nf, tcg_ctx->cpu_NF);
         tcg_gen_ext_i32_i64(tcg_ctx, vf, tcg_ctx->cpu_VF);
 
-        tcg_gen_ld_f64(tcg_ctx, frn, tcg_ctx->cpu_env, vfp_reg_offset(dp, rn));
-        tcg_gen_ld_f64(tcg_ctx, frm, tcg_ctx->cpu_env, vfp_reg_offset(dp, rm));
+        tcg_gen_ld_f64(tcg_ctx, frn, uc->cpu_env, vfp_reg_offset(dp, rn));
+        tcg_gen_ld_f64(tcg_ctx, frm, uc->cpu_env, vfp_reg_offset(dp, rm));
         switch (cc) {
         case 0: /* eq: Z */
             tcg_gen_movcond_i64(tcg_ctx, TCG_COND_EQ, dest, zf, zero,
@@ -3140,7 +3176,7 @@ static int handle_vsel(DisasContext *s, uint32_t insn, uint32_t rd, uint32_t rn,
             tcg_temp_free_i64(tcg_ctx, tmp);
             break;
         }
-        tcg_gen_st_f64(tcg_ctx, dest, tcg_ctx->cpu_env, vfp_reg_offset(dp, rd));
+        tcg_gen_st_f64(tcg_ctx, dest, uc->cpu_env, vfp_reg_offset(dp, rd));
         tcg_temp_free_i64(tcg_ctx, frn);
         tcg_temp_free_i64(tcg_ctx, frm);
         tcg_temp_free_i64(tcg_ctx, dest);
@@ -3159,8 +3195,8 @@ static int handle_vsel(DisasContext *s, uint32_t insn, uint32_t rd, uint32_t rn,
         frn = tcg_temp_new_i32(tcg_ctx);
         frm = tcg_temp_new_i32(tcg_ctx);
         dest = tcg_temp_new_i32(tcg_ctx);
-        tcg_gen_ld_f32(tcg_ctx, frn, tcg_ctx->cpu_env, vfp_reg_offset(dp, rn));
-        tcg_gen_ld_f32(tcg_ctx, frm, tcg_ctx->cpu_env, vfp_reg_offset(dp, rm));
+        tcg_gen_ld_f32(tcg_ctx, frn, uc->cpu_env, vfp_reg_offset(dp, rn));
+        tcg_gen_ld_f32(tcg_ctx, frm, uc->cpu_env, vfp_reg_offset(dp, rm));
         switch (cc) {
         case 0: /* eq: Z */
             tcg_gen_movcond_i32(tcg_ctx, TCG_COND_EQ, dest, tcg_ctx->cpu_ZF, zero,
@@ -3187,7 +3223,7 @@ static int handle_vsel(DisasContext *s, uint32_t insn, uint32_t rd, uint32_t rn,
             tcg_temp_free_i32(tcg_ctx, tmp);
             break;
         }
-        tcg_gen_st_f32(tcg_ctx, dest, tcg_ctx->cpu_env, vfp_reg_offset(dp, rd));
+        tcg_gen_st_f32(tcg_ctx, dest, uc->cpu_env, vfp_reg_offset(dp, rd));
         tcg_temp_free_i32(tcg_ctx, frn);
         tcg_temp_free_i32(tcg_ctx, frm);
         tcg_temp_free_i32(tcg_ctx, dest);
@@ -3201,7 +3237,8 @@ static int handle_vsel(DisasContext *s, uint32_t insn, uint32_t rd, uint32_t rn,
 static int handle_vminmaxnm(DisasContext *s, uint32_t insn, uint32_t rd, uint32_t rn,
                             uint32_t rm, uint32_t dp)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     uint32_t vmin = extract32(insn, 6, 1);
     TCGv_ptr fpst = get_fpstatus_ptr(s, 0);
 
@@ -3212,14 +3249,14 @@ static int handle_vminmaxnm(DisasContext *s, uint32_t insn, uint32_t rd, uint32_
         frm = tcg_temp_new_i64(tcg_ctx);
         dest = tcg_temp_new_i64(tcg_ctx);
 
-        tcg_gen_ld_f64(tcg_ctx, frn, tcg_ctx->cpu_env, vfp_reg_offset(dp, rn));
-        tcg_gen_ld_f64(tcg_ctx, frm, tcg_ctx->cpu_env, vfp_reg_offset(dp, rm));
+        tcg_gen_ld_f64(tcg_ctx, frn, uc->cpu_env, vfp_reg_offset(dp, rn));
+        tcg_gen_ld_f64(tcg_ctx, frm, uc->cpu_env, vfp_reg_offset(dp, rm));
         if (vmin) {
             gen_helper_vfp_minnumd(tcg_ctx, dest, frn, frm, fpst);
         } else {
             gen_helper_vfp_maxnumd(tcg_ctx, dest, frn, frm, fpst);
         }
-        tcg_gen_st_f64(tcg_ctx, dest, tcg_ctx->cpu_env, vfp_reg_offset(dp, rd));
+        tcg_gen_st_f64(tcg_ctx, dest, uc->cpu_env, vfp_reg_offset(dp, rd));
         tcg_temp_free_i64(tcg_ctx, frn);
         tcg_temp_free_i64(tcg_ctx, frm);
         tcg_temp_free_i64(tcg_ctx, dest);
@@ -3230,14 +3267,14 @@ static int handle_vminmaxnm(DisasContext *s, uint32_t insn, uint32_t rd, uint32_
         frm = tcg_temp_new_i32(tcg_ctx);
         dest = tcg_temp_new_i32(tcg_ctx);
 
-        tcg_gen_ld_f32(tcg_ctx, frn, tcg_ctx->cpu_env, vfp_reg_offset(dp, rn));
-        tcg_gen_ld_f32(tcg_ctx, frm, tcg_ctx->cpu_env, vfp_reg_offset(dp, rm));
+        tcg_gen_ld_f32(tcg_ctx, frn, uc->cpu_env, vfp_reg_offset(dp, rn));
+        tcg_gen_ld_f32(tcg_ctx, frm, uc->cpu_env, vfp_reg_offset(dp, rm));
         if (vmin) {
             gen_helper_vfp_minnums(tcg_ctx, dest, frn, frm, fpst);
         } else {
             gen_helper_vfp_maxnums(tcg_ctx, dest, frn, frm, fpst);
         }
-        tcg_gen_st_f32(tcg_ctx, dest, tcg_ctx->cpu_env, vfp_reg_offset(dp, rd));
+        tcg_gen_st_f32(tcg_ctx, dest, uc->cpu_env, vfp_reg_offset(dp, rd));
         tcg_temp_free_i32(tcg_ctx, frn);
         tcg_temp_free_i32(tcg_ctx, frm);
         tcg_temp_free_i32(tcg_ctx, dest);
@@ -3250,7 +3287,8 @@ static int handle_vminmaxnm(DisasContext *s, uint32_t insn, uint32_t rd, uint32_
 static int handle_vrint(DisasContext *s, uint32_t insn, uint32_t rd, uint32_t rm, uint32_t dp,
                         int rounding)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv_ptr fpst = get_fpstatus_ptr(s, 0);
     TCGv_i32 tcg_rmode;
 
@@ -3262,9 +3300,9 @@ static int handle_vrint(DisasContext *s, uint32_t insn, uint32_t rd, uint32_t rm
         TCGv_i64 tcg_res;
         tcg_op = tcg_temp_new_i64(tcg_ctx);
         tcg_res = tcg_temp_new_i64(tcg_ctx);
-        tcg_gen_ld_f64(tcg_ctx, tcg_op, tcg_ctx->cpu_env, vfp_reg_offset(dp, rm));
+        tcg_gen_ld_f64(tcg_ctx, tcg_op, uc->cpu_env, vfp_reg_offset(dp, rm));
         gen_helper_rintd(tcg_ctx, tcg_res, tcg_op, fpst);
-        tcg_gen_st_f64(tcg_ctx, tcg_res, tcg_ctx->cpu_env, vfp_reg_offset(dp, rd));
+        tcg_gen_st_f64(tcg_ctx, tcg_res, uc->cpu_env, vfp_reg_offset(dp, rd));
         tcg_temp_free_i64(tcg_ctx, tcg_op);
         tcg_temp_free_i64(tcg_ctx, tcg_res);
     } else {
@@ -3272,9 +3310,9 @@ static int handle_vrint(DisasContext *s, uint32_t insn, uint32_t rd, uint32_t rm
         TCGv_i32 tcg_res;
         tcg_op = tcg_temp_new_i32(tcg_ctx);
         tcg_res = tcg_temp_new_i32(tcg_ctx);
-        tcg_gen_ld_f32(tcg_ctx, tcg_op, tcg_ctx->cpu_env, vfp_reg_offset(dp, rm));
+        tcg_gen_ld_f32(tcg_ctx, tcg_op, uc->cpu_env, vfp_reg_offset(dp, rm));
         gen_helper_rints(tcg_ctx, tcg_res, tcg_op, fpst);
-        tcg_gen_st_f32(tcg_ctx, tcg_res, tcg_ctx->cpu_env, vfp_reg_offset(dp, rd));
+        tcg_gen_st_f32(tcg_ctx, tcg_res, uc->cpu_env, vfp_reg_offset(dp, rd));
         tcg_temp_free_i32(tcg_ctx, tcg_op);
         tcg_temp_free_i32(tcg_ctx, tcg_res);
     }
@@ -3289,7 +3327,8 @@ static int handle_vrint(DisasContext *s, uint32_t insn, uint32_t rd, uint32_t rm
 static int handle_vcvt(DisasContext *s, uint32_t insn, uint32_t rd, uint32_t rm, uint32_t dp,
                        int rounding)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     bool is_signed = extract32(insn, 7, 1);
     TCGv_ptr fpst = get_fpstatus_ptr(s, 0);
     TCGv_i32 tcg_rmode, tcg_shift;
@@ -3309,14 +3348,14 @@ static int handle_vcvt(DisasContext *s, uint32_t insn, uint32_t rd, uint32_t rm,
         tcg_double = tcg_temp_new_i64(tcg_ctx);
         tcg_res = tcg_temp_new_i64(tcg_ctx);
         tcg_tmp = tcg_temp_new_i32(tcg_ctx);
-        tcg_gen_ld_f64(tcg_ctx, tcg_double, tcg_ctx->cpu_env, vfp_reg_offset(1, rm));
+        tcg_gen_ld_f64(tcg_ctx, tcg_double, uc->cpu_env, vfp_reg_offset(1, rm));
         if (is_signed) {
             gen_helper_vfp_tosld(tcg_ctx, tcg_res, tcg_double, tcg_shift, fpst);
         } else {
             gen_helper_vfp_tould(tcg_ctx, tcg_res, tcg_double, tcg_shift, fpst);
         }
         tcg_gen_extrl_i64_i32(tcg_ctx, tcg_tmp, tcg_res);
-        tcg_gen_st_f32(tcg_ctx, tcg_tmp, tcg_ctx->cpu_env, vfp_reg_offset(0, rd));
+        tcg_gen_st_f32(tcg_ctx, tcg_tmp, uc->cpu_env, vfp_reg_offset(0, rd));
         tcg_temp_free_i32(tcg_ctx, tcg_tmp);
         tcg_temp_free_i64(tcg_ctx, tcg_res);
         tcg_temp_free_i64(tcg_ctx, tcg_double);
@@ -3324,13 +3363,13 @@ static int handle_vcvt(DisasContext *s, uint32_t insn, uint32_t rd, uint32_t rm,
         TCGv_i32 tcg_single, tcg_res;
         tcg_single = tcg_temp_new_i32(tcg_ctx);
         tcg_res = tcg_temp_new_i32(tcg_ctx);
-        tcg_gen_ld_f32(tcg_ctx, tcg_single, tcg_ctx->cpu_env, vfp_reg_offset(0, rm));
+        tcg_gen_ld_f32(tcg_ctx, tcg_single, uc->cpu_env, vfp_reg_offset(0, rm));
         if (is_signed) {
             gen_helper_vfp_tosls(tcg_ctx, tcg_res, tcg_single, tcg_shift, fpst);
         } else {
             gen_helper_vfp_touls(tcg_ctx, tcg_res, tcg_single, tcg_shift, fpst);
         }
-        tcg_gen_st_f32(tcg_ctx, tcg_res, tcg_ctx->cpu_env, vfp_reg_offset(0, rd));
+        tcg_gen_st_f32(tcg_ctx, tcg_res, uc->cpu_env, vfp_reg_offset(0, rd));
         tcg_temp_free_i32(tcg_ctx, tcg_res);
         tcg_temp_free_i32(tcg_ctx, tcg_single);
     }
@@ -3394,7 +3433,8 @@ static int disas_vfp_v8_insn(DisasContext *s, uint32_t insn)
    (ie. an undefined instruction).  */
 static int disas_vfp_insn(DisasContext *s, uint32_t insn)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     uint32_t rd, rn, rm, op, i, n, offset, delta_d, delta_m, bank_mask;
     int dp, veclen;
     TCGv_i32 addr;
@@ -3547,12 +3587,12 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
                                 && arm_dc_feature(s, ARM_FEATURE_VFP3)) {
                                 return 1;
                             }
-                            tmp = load_cpu_field(s->uc, vfp.xregs[rn]);
+                            tmp = load_cpu_field(uc, vfp.xregs[rn]);
                             break;
                         case ARM_VFP_FPEXC:
                             if (IS_USER(s))
                                 return 1;
-                            tmp = load_cpu_field(s->uc, vfp.xregs[rn]);
+                            tmp = load_cpu_field(uc, vfp.xregs[rn]);
                             break;
                         case ARM_VFP_FPINST:
                         case ARM_VFP_FPINST2:
@@ -3561,15 +3601,15 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
                                 || arm_dc_feature(s, ARM_FEATURE_VFP3)) {
                                 return 1;
                             }
-                            tmp = load_cpu_field(s->uc, vfp.xregs[rn]);
+                            tmp = load_cpu_field(uc, vfp.xregs[rn]);
                             break;
                         case ARM_VFP_FPSCR:
                             if (rd == 15) {
-                                tmp = load_cpu_field(s->uc, vfp.xregs[ARM_VFP_FPSCR]);
+                                tmp = load_cpu_field(uc, vfp.xregs[ARM_VFP_FPSCR]);
                                 tcg_gen_andi_i32(tcg_ctx, tmp, tmp, 0xf0000000);
                             } else {
                                 tmp = tcg_temp_new_i32(tcg_ctx);
-                                gen_helper_vfp_get_fpscr(tcg_ctx, tmp, tcg_ctx->cpu_env);
+                                gen_helper_vfp_get_fpscr(tcg_ctx, tmp, uc->cpu_env);
                             }
                             break;
                         case ARM_VFP_MVFR2:
@@ -3583,7 +3623,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
                                 || !arm_dc_feature(s, ARM_FEATURE_MVFR)) {
                                 return 1;
                             }
-                            tmp = load_cpu_field(s->uc, vfp.xregs[rn]);
+                            tmp = load_cpu_field(uc, vfp.xregs[rn]);
                             break;
                         default:
                             return 1;
@@ -3612,7 +3652,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
                             break;
                         case ARM_VFP_FPSCR:
                             tmp = load_reg(s, rd);
-                            gen_helper_vfp_set_fpscr(tcg_ctx, tcg_ctx->cpu_env, tmp);
+                            gen_helper_vfp_set_fpscr(tcg_ctx, uc->cpu_env, tmp);
                             tcg_temp_free_i32(tcg_ctx, tmp);
                             gen_lookup_tb(s);
                             break;
@@ -3854,7 +3894,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
                             gen_helper_vfp_negd(tcg_ctx, tcg_ctx->cpu_F0d, tcg_ctx->cpu_F0d);
                         }
                         frd = tcg_temp_new_i64(tcg_ctx);
-                        tcg_gen_ld_f64(tcg_ctx, frd, tcg_ctx->cpu_env, vfp_reg_offset(dp, rd));
+                        tcg_gen_ld_f64(tcg_ctx, frd, uc->cpu_env, vfp_reg_offset(dp, rd));
                         if (op & 2) {
                             /* VFNMA, VFNMS */
                             gen_helper_vfp_negd(tcg_ctx, frd, frd);
@@ -3872,7 +3912,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
                             gen_helper_vfp_negs(tcg_ctx, tcg_ctx->cpu_F0s, tcg_ctx->cpu_F0s);
                         }
                         frd = tcg_temp_new_i32(tcg_ctx);
-                        tcg_gen_ld_f32(tcg_ctx, frd, tcg_ctx->cpu_env, vfp_reg_offset(dp, rd));
+                        tcg_gen_ld_f32(tcg_ctx, frd, uc->cpu_env, vfp_reg_offset(dp, rd));
                         if (op & 2) {
                             gen_helper_vfp_negs(tcg_ctx, frd, frd);
                         }
@@ -3925,10 +3965,10 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
                         tcg_gen_ext16u_i32(tcg_ctx, tmp, tmp);
                         if (dp) {
                             gen_helper_vfp_fcvt_f16_to_f64(tcg_ctx, tcg_ctx->cpu_F0d, tmp,
-                                                           tcg_ctx->cpu_env);
+                                                           uc->cpu_env);
                         } else {
                             gen_helper_vfp_fcvt_f16_to_f32(tcg_ctx, tcg_ctx->cpu_F0s, tmp,
-                                                           tcg_ctx->cpu_env);
+                                                           uc->cpu_env);
                         }
                         tcg_temp_free_i32(tcg_ctx, tmp);
                         break;
@@ -3937,10 +3977,10 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
                         tcg_gen_shri_i32(tcg_ctx, tmp, tmp, 16);
                         if (dp) {
                             gen_helper_vfp_fcvt_f16_to_f64(tcg_ctx, tcg_ctx->cpu_F0d, tmp,
-                                                           tcg_ctx->cpu_env);
+                                                           uc->cpu_env);
                         } else {
                             gen_helper_vfp_fcvt_f16_to_f32(tcg_ctx, tcg_ctx->cpu_F0s, tmp,
-                                                           tcg_ctx->cpu_env);
+                                                           uc->cpu_env);
                         }
                         tcg_temp_free_i32(tcg_ctx, tmp);
                         break;
@@ -3948,10 +3988,10 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
                         tmp = tcg_temp_new_i32(tcg_ctx);
                         if (dp) {
                             gen_helper_vfp_fcvt_f64_to_f16(tcg_ctx, tmp, tcg_ctx->cpu_F0d,
-                                                           tcg_ctx->cpu_env);
+                                                           uc->cpu_env);
                         } else {
                             gen_helper_vfp_fcvt_f32_to_f16(tcg_ctx, tmp, tcg_ctx->cpu_F0s,
-                                                           tcg_ctx->cpu_env);
+                                                           uc->cpu_env);
                         }
                         gen_mov_F0_vreg(s, 0, rd);
                         tmp2 = gen_vfp_mrs(s);
@@ -3964,10 +4004,10 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
                         tmp = tcg_temp_new_i32(tcg_ctx);
                         if (dp) {
                             gen_helper_vfp_fcvt_f64_to_f16(tcg_ctx, tmp, tcg_ctx->cpu_F0d,
-                                                           tcg_ctx->cpu_env);
+                                                           uc->cpu_env);
                         } else {
                             gen_helper_vfp_fcvt_f32_to_f16(tcg_ctx, tmp, tcg_ctx->cpu_F0s,
-                                                           tcg_ctx->cpu_env);
+                                                           uc->cpu_env);
                         }
                         tcg_gen_shli_i32(tcg_ctx, tmp, tmp, 16);
                         gen_mov_F0_vreg(s, 0, rd);
@@ -4030,9 +4070,9 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
                     }
                     case 15: /* single<->double conversion */
                         if (dp)
-                            gen_helper_vfp_fcvtsd(tcg_ctx, tcg_ctx->cpu_F0s, tcg_ctx->cpu_F0d, tcg_ctx->cpu_env);
+                            gen_helper_vfp_fcvtsd(tcg_ctx, tcg_ctx->cpu_F0s, tcg_ctx->cpu_F0d, uc->cpu_env);
                         else
-                            gen_helper_vfp_fcvtds(tcg_ctx, tcg_ctx->cpu_F0d, tcg_ctx->cpu_F0s, tcg_ctx->cpu_env);
+                            gen_helper_vfp_fcvtds(tcg_ctx, tcg_ctx->cpu_F0d, tcg_ctx->cpu_F0s, uc->cpu_env);
                         break;
                     case 16: /* fuito */
                         gen_vfp_uito(s, dp, 0);
@@ -4609,7 +4649,8 @@ undef:
 
 static void gen_msr_banked(DisasContext *s, int r, int sysm, int rn)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv_i32 tcg_reg, tcg_tgtmode, tcg_regno;
     int tgtmode = 0, regno = 0;
 
@@ -4623,7 +4664,7 @@ static void gen_msr_banked(DisasContext *s, int r, int sysm, int rn)
     tcg_reg = load_reg(s, rn);
     tcg_tgtmode = tcg_const_i32(tcg_ctx, tgtmode);
     tcg_regno = tcg_const_i32(tcg_ctx, regno);
-    gen_helper_msr_banked(tcg_ctx, tcg_ctx->cpu_env, tcg_reg, tcg_tgtmode, tcg_regno);
+    gen_helper_msr_banked(tcg_ctx, uc->cpu_env, tcg_reg, tcg_tgtmode, tcg_regno);
     tcg_temp_free_i32(tcg_ctx, tcg_tgtmode);
     tcg_temp_free_i32(tcg_ctx, tcg_regno);
     tcg_temp_free_i32(tcg_ctx, tcg_reg);
@@ -4632,7 +4673,8 @@ static void gen_msr_banked(DisasContext *s, int r, int sysm, int rn)
 
 static void gen_mrs_banked(DisasContext *s, int r, int sysm, int rn)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv_i32 tcg_reg, tcg_tgtmode, tcg_regno;
     int tgtmode = 0, regno = 0;
 
@@ -4646,7 +4688,7 @@ static void gen_mrs_banked(DisasContext *s, int r, int sysm, int rn)
     tcg_reg = tcg_temp_new_i32(tcg_ctx);
     tcg_tgtmode = tcg_const_i32(tcg_ctx, tgtmode);
     tcg_regno = tcg_const_i32(tcg_ctx, regno);
-    gen_helper_mrs_banked(tcg_ctx, tcg_reg, tcg_ctx->cpu_env, tcg_tgtmode, tcg_regno);
+    gen_helper_mrs_banked(tcg_ctx, tcg_reg, uc->cpu_env, tcg_tgtmode, tcg_regno);
     tcg_temp_free_i32(tcg_ctx, tcg_tgtmode);
     tcg_temp_free_i32(tcg_ctx, tcg_regno);
     store_reg(s, rn, tcg_reg);
@@ -4668,14 +4710,15 @@ static void store_pc_exc_ret(DisasContext *s, TCGv_i32 pc)
 /* Generate a v6 exception return.  Marks both values as dead.  */
 static void gen_rfe(DisasContext *s, TCGv_i32 pc, TCGv_i32 cpsr)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
 
     store_pc_exc_ret(s, pc);
     /* The cpsr_write_eret helper will mask the low bits of PC
      * appropriately depending on the new Thumb bit, so it must
      * be called after storing the new PC.
      */
-    gen_helper_cpsr_write_eret(tcg_ctx, tcg_ctx->cpu_env, cpsr);
+    gen_helper_cpsr_write_eret(tcg_ctx, uc->cpu_env, cpsr);
     tcg_temp_free_i32(tcg_ctx, cpsr);
     /* Must exit loop to check un-masked IRQs */
     s->base.is_jmp = DISAS_EXIT;
@@ -4760,22 +4803,22 @@ static inline void gen_neon_rsb(DisasContext *s, int size, TCGv_i32 t0, TCGv_i32
 #define GEN_NEON_INTEGER_OP_ENV(name) do { \
     switch ((size << 1) | u) { \
     case 0: \
-        gen_helper_neon_##name##_s8(tcg_ctx, tmp, tcg_ctx->cpu_env, tmp, tmp2); \
+        gen_helper_neon_##name##_s8(tcg_ctx, tmp, uc->cpu_env, tmp, tmp2); \
         break; \
     case 1: \
-        gen_helper_neon_##name##_u8(tcg_ctx, tmp, tcg_ctx->cpu_env, tmp, tmp2); \
+        gen_helper_neon_##name##_u8(tcg_ctx, tmp, uc->cpu_env, tmp, tmp2); \
         break; \
     case 2: \
-        gen_helper_neon_##name##_s16(tcg_ctx, tmp, tcg_ctx->cpu_env, tmp, tmp2); \
+        gen_helper_neon_##name##_s16(tcg_ctx, tmp, uc->cpu_env, tmp, tmp2); \
         break; \
     case 3: \
-        gen_helper_neon_##name##_u16(tcg_ctx, tmp, tcg_ctx->cpu_env, tmp, tmp2); \
+        gen_helper_neon_##name##_u16(tcg_ctx, tmp, uc->cpu_env, tmp, tmp2); \
         break; \
     case 4: \
-        gen_helper_neon_##name##_s32(tcg_ctx, tmp, tcg_ctx->cpu_env, tmp, tmp2); \
+        gen_helper_neon_##name##_s32(tcg_ctx, tmp, uc->cpu_env, tmp, tmp2); \
         break; \
     case 5: \
-        gen_helper_neon_##name##_u32(tcg_ctx, tmp, tcg_ctx->cpu_env, tmp, tmp2); \
+        gen_helper_neon_##name##_u32(tcg_ctx, tmp, uc->cpu_env, tmp, tmp2); \
         break; \
     default: return 1; \
     }} while (0)
@@ -4806,13 +4849,13 @@ static inline void gen_neon_rsb(DisasContext *s, int size, TCGv_i32 t0, TCGv_i32
 static TCGv_i32 neon_load_scratch(TCGContext *tcg_ctx, int scratch)
 {
     TCGv_i32 tmp = tcg_temp_new_i32(tcg_ctx);
-    tcg_gen_ld_i32(tcg_ctx, tmp, tcg_ctx->cpu_env, offsetof(CPUARMState, vfp.scratch[scratch]));
+    tcg_gen_ld_i32(tcg_ctx, tmp, tcg_ctx->uc->cpu_env, offsetof(CPUARMState, vfp.scratch[scratch]));
     return tmp;
 }
 
 static void neon_store_scratch(TCGContext *tcg_ctx, int scratch, TCGv_i32 var)
 {
-    tcg_gen_st_i32(tcg_ctx, var, tcg_ctx->cpu_env, offsetof(CPUARMState, vfp.scratch[scratch]));
+    tcg_gen_st_i32(tcg_ctx, var, tcg_ctx->uc->cpu_env, offsetof(CPUARMState, vfp.scratch[scratch]));
     tcg_temp_free_i32(tcg_ctx, var);
 }
 
@@ -4977,7 +5020,8 @@ static struct {
    instruction is invalid.  */
 static int disas_neon_ls_insn(DisasContext *s, uint32_t insn)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     int rd, rn, rm;
     int op;
     int nregs;
@@ -5162,11 +5206,11 @@ static int disas_neon_ls_insn(DisasContext *s, uint32_t insn)
             if (nregs == 1) {
                 /* VLD1 to all lanes: bit 5 indicates how many Dregs to write */
                 tmp = gen_load_and_replicate(s, addr, size);
-                tcg_gen_st_i32(tcg_ctx, tmp, tcg_ctx->cpu_env, neon_reg_offset(rd, 0));
-                tcg_gen_st_i32(tcg_ctx, tmp, tcg_ctx->cpu_env, neon_reg_offset(rd, 1));
+                tcg_gen_st_i32(tcg_ctx, tmp, uc->cpu_env, neon_reg_offset(rd, 0));
+                tcg_gen_st_i32(tcg_ctx, tmp, uc->cpu_env, neon_reg_offset(rd, 1));
                 if (insn & (1 << 5)) {
-                    tcg_gen_st_i32(tcg_ctx, tmp, tcg_ctx->cpu_env, neon_reg_offset(rd + 1, 0));
-                    tcg_gen_st_i32(tcg_ctx, tmp, tcg_ctx->cpu_env, neon_reg_offset(rd + 1, 1));
+                    tcg_gen_st_i32(tcg_ctx, tmp, uc->cpu_env, neon_reg_offset(rd + 1, 0));
+                    tcg_gen_st_i32(tcg_ctx, tmp, uc->cpu_env, neon_reg_offset(rd + 1, 1));
                 }
                 tcg_temp_free_i32(tcg_ctx, tmp);
             } else {
@@ -5174,8 +5218,8 @@ static int disas_neon_ls_insn(DisasContext *s, uint32_t insn)
                 stride = (insn & (1 << 5)) ? 2 : 1;
                 for (reg = 0; reg < nregs; reg++) {
                     tmp = gen_load_and_replicate(s, addr, size);
-                    tcg_gen_st_i32(tcg_ctx, tmp, tcg_ctx->cpu_env, neon_reg_offset(rd, 0));
-                    tcg_gen_st_i32(tcg_ctx, tmp, tcg_ctx->cpu_env, neon_reg_offset(rd, 1));
+                    tcg_gen_st_i32(tcg_ctx, tmp, uc->cpu_env, neon_reg_offset(rd, 0));
+                    tcg_gen_st_i32(tcg_ctx, tmp, uc->cpu_env, neon_reg_offset(rd, 1));
                     tcg_temp_free_i32(tcg_ctx, tmp);
                     tcg_gen_addi_i32(tcg_ctx, addr, addr, 1 << size);
                     rd += stride;
@@ -5325,33 +5369,39 @@ static inline void gen_neon_narrow(DisasContext *s, int size, TCGv_i32 dest, TCG
 
 static inline void gen_neon_narrow_sats(DisasContext *s, int size, TCGv_i32 dest, TCGv_i64 src)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
+
     switch (size) {
-    case 0: gen_helper_neon_narrow_sat_s8(tcg_ctx, dest, tcg_ctx->cpu_env, src); break;
-    case 1: gen_helper_neon_narrow_sat_s16(tcg_ctx, dest, tcg_ctx->cpu_env, src); break;
-    case 2: gen_helper_neon_narrow_sat_s32(tcg_ctx, dest, tcg_ctx->cpu_env, src); break;
+    case 0: gen_helper_neon_narrow_sat_s8(tcg_ctx, dest, uc->cpu_env, src); break;
+    case 1: gen_helper_neon_narrow_sat_s16(tcg_ctx, dest, uc->cpu_env, src); break;
+    case 2: gen_helper_neon_narrow_sat_s32(tcg_ctx, dest, uc->cpu_env, src); break;
     default: abort();
     }
 }
 
 static inline void gen_neon_narrow_satu(DisasContext *s, int size, TCGv_i32 dest, TCGv_i64 src)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
+
     switch (size) {
-    case 0: gen_helper_neon_narrow_sat_u8(tcg_ctx, dest, tcg_ctx->cpu_env, src); break;
-    case 1: gen_helper_neon_narrow_sat_u16(tcg_ctx, dest, tcg_ctx->cpu_env, src); break;
-    case 2: gen_helper_neon_narrow_sat_u32(tcg_ctx, dest, tcg_ctx->cpu_env, src); break;
+    case 0: gen_helper_neon_narrow_sat_u8(tcg_ctx, dest, uc->cpu_env, src); break;
+    case 1: gen_helper_neon_narrow_sat_u16(tcg_ctx, dest, uc->cpu_env, src); break;
+    case 2: gen_helper_neon_narrow_sat_u32(tcg_ctx, dest, uc->cpu_env, src); break;
     default: abort();
     }
 }
 
 static inline void gen_neon_unarrow_sats(DisasContext *s, int size, TCGv_i32 dest, TCGv_i64 src)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
+
     switch (size) {
-    case 0: gen_helper_neon_unarrow_sat8(tcg_ctx, dest, tcg_ctx->cpu_env, src); break;
-    case 1: gen_helper_neon_unarrow_sat16(tcg_ctx, dest, tcg_ctx->cpu_env, src); break;
-    case 2: gen_helper_neon_unarrow_sat32(tcg_ctx, dest, tcg_ctx->cpu_env, src); break;
+    case 0: gen_helper_neon_unarrow_sat8(tcg_ctx, dest, uc->cpu_env, src); break;
+    case 1: gen_helper_neon_unarrow_sat16(tcg_ctx, dest, uc->cpu_env, src); break;
+    case 2: gen_helper_neon_unarrow_sat32(tcg_ctx, dest, uc->cpu_env, src); break;
     default: abort();
     }
 }
@@ -5449,10 +5499,12 @@ static inline void gen_neon_negl(DisasContext *s, TCGv_i64 var, int size)
 
 static inline void gen_neon_addl_saturate(DisasContext *s, TCGv_i64 op0, TCGv_i64 op1, int size)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
+
     switch (size) {
-    case 1: gen_helper_neon_addl_saturate_s32(tcg_ctx, op0, tcg_ctx->cpu_env, op0, op1); break;
-    case 2: gen_helper_neon_addl_saturate_s64(tcg_ctx, op0, tcg_ctx->cpu_env, op0, op1); break;
+    case 1: gen_helper_neon_addl_saturate_s32(tcg_ctx, op0, uc->cpu_env, op0, op1); break;
+    case 2: gen_helper_neon_addl_saturate_s64(tcg_ctx, op0, uc->cpu_env, op0, op1); break;
     default: abort();
     }
 }
@@ -5756,13 +5808,14 @@ static const uint8_t neon_2rm_sizes[] = {
 static int do_v81_helper(DisasContext *s, gen_helper_gvec_3_ptr *fn,
                          int q, int rd, int rn, int rm)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
 
     if (arm_dc_feature(s, ARM_FEATURE_V8_RDM)) {
         int opr_sz = (1 + q) * 8;
         tcg_gen_gvec_3_ptr(tcg_ctx, vfp_reg_offset(1, rd),
                            vfp_reg_offset(1, rn),
-                           vfp_reg_offset(1, rm), tcg_ctx->cpu_env,
+                           vfp_reg_offset(1, rm), uc->cpu_env,
                            opr_sz, opr_sz, 0, fn);
         return 0;
     }
@@ -5776,7 +5829,8 @@ static int do_v81_helper(DisasContext *s, gen_helper_gvec_3_ptr *fn,
 
 static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     int op;
     int q;
     int rd, rn, rm;
@@ -5908,19 +5962,19 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
                 switch (op) {
                 case NEON_3R_VQADD:
                     if (u) {
-                        gen_helper_neon_qadd_u64(tcg_ctx, tcg_ctx->cpu_V0, tcg_ctx->cpu_env,
+                        gen_helper_neon_qadd_u64(tcg_ctx, tcg_ctx->cpu_V0, uc->cpu_env,
                                                  tcg_ctx->cpu_V0, tcg_ctx->cpu_V1);
                     } else {
-                        gen_helper_neon_qadd_s64(tcg_ctx, tcg_ctx->cpu_V0, tcg_ctx->cpu_env,
+                        gen_helper_neon_qadd_s64(tcg_ctx, tcg_ctx->cpu_V0, uc->cpu_env,
                                                  tcg_ctx->cpu_V0, tcg_ctx->cpu_V1);
                     }
                     break;
                 case NEON_3R_VQSUB:
                     if (u) {
-                        gen_helper_neon_qsub_u64(tcg_ctx, tcg_ctx->cpu_V0, tcg_ctx->cpu_env,
+                        gen_helper_neon_qsub_u64(tcg_ctx, tcg_ctx->cpu_V0, uc->cpu_env,
                                                  tcg_ctx->cpu_V0, tcg_ctx->cpu_V1);
                     } else {
-                        gen_helper_neon_qsub_s64(tcg_ctx, tcg_ctx->cpu_V0, tcg_ctx->cpu_env,
+                        gen_helper_neon_qsub_s64(tcg_ctx, tcg_ctx->cpu_V0, uc->cpu_env,
                                                  tcg_ctx->cpu_V0, tcg_ctx->cpu_V1);
                     }
                     break;
@@ -5933,10 +5987,10 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
                     break;
                 case NEON_3R_VQSHL:
                     if (u) {
-                        gen_helper_neon_qshl_u64(tcg_ctx, tcg_ctx->cpu_V0, tcg_ctx->cpu_env,
+                        gen_helper_neon_qshl_u64(tcg_ctx, tcg_ctx->cpu_V0, uc->cpu_env,
                                                  tcg_ctx->cpu_V1, tcg_ctx->cpu_V0);
                     } else {
-                        gen_helper_neon_qshl_s64(tcg_ctx, tcg_ctx->cpu_V0, tcg_ctx->cpu_env,
+                        gen_helper_neon_qshl_s64(tcg_ctx, tcg_ctx->cpu_V0, uc->cpu_env,
                                                  tcg_ctx->cpu_V1, tcg_ctx->cpu_V0);
                     }
                     break;
@@ -5949,10 +6003,10 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
                     break;
                 case NEON_3R_VQRSHL:
                     if (u) {
-                        gen_helper_neon_qrshl_u64(tcg_ctx, tcg_ctx->cpu_V0, tcg_ctx->cpu_env,
+                        gen_helper_neon_qrshl_u64(tcg_ctx, tcg_ctx->cpu_V0, uc->cpu_env,
                                                   tcg_ctx->cpu_V1, tcg_ctx->cpu_V0);
                     } else {
-                        gen_helper_neon_qrshl_s64(tcg_ctx, tcg_ctx->cpu_V0, tcg_ctx->cpu_env,
+                        gen_helper_neon_qrshl_s64(tcg_ctx, tcg_ctx->cpu_V0, uc->cpu_env,
                                                   tcg_ctx->cpu_V1, tcg_ctx->cpu_V0);
                     }
                     break;
@@ -6197,20 +6251,20 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
             if (!u) { /* VQDMULH */
                 switch (size) {
                 case 1:
-                    gen_helper_neon_qdmulh_s16(tcg_ctx, tmp, tcg_ctx->cpu_env, tmp, tmp2);
+                    gen_helper_neon_qdmulh_s16(tcg_ctx, tmp, uc->cpu_env, tmp, tmp2);
                     break;
                 case 2:
-                    gen_helper_neon_qdmulh_s32(tcg_ctx, tmp, tcg_ctx->cpu_env, tmp, tmp2);
+                    gen_helper_neon_qdmulh_s32(tcg_ctx, tmp, uc->cpu_env, tmp, tmp2);
                     break;
                 default: abort();
                 }
             } else { /* VQRDMULH */
                 switch (size) {
                 case 1:
-                    gen_helper_neon_qrdmulh_s16(tcg_ctx, tmp, tcg_ctx->cpu_env, tmp, tmp2);
+                    gen_helper_neon_qrdmulh_s16(tcg_ctx, tmp, uc->cpu_env, tmp, tmp2);
                     break;
                 case 2:
-                    gen_helper_neon_qrdmulh_s32(tcg_ctx, tmp, tcg_ctx->cpu_env, tmp, tmp2);
+                    gen_helper_neon_qrdmulh_s32(tcg_ctx, tmp, uc->cpu_env, tmp, tmp2);
                     break;
                 default: abort();
                 }
@@ -6309,9 +6363,9 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
                 tcg_temp_free_ptr(tcg_ctx, fpstatus);
             } else {
                 if (size == 0) {
-                    gen_helper_recps_f32(tcg_ctx, tmp, tmp, tmp2, tcg_ctx->cpu_env);
+                    gen_helper_recps_f32(tcg_ctx, tmp, tmp, tmp2, uc->cpu_env);
                 } else {
-                    gen_helper_rsqrts_f32(tcg_ctx, tmp, tmp, tmp2, tcg_ctx->cpu_env);
+                    gen_helper_rsqrts_f32(tcg_ctx, tmp, tmp, tmp2, uc->cpu_env);
               }
             }
             break;
@@ -6429,15 +6483,15 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
                             gen_helper_neon_shl_u64(tcg_ctx, tcg_ctx->cpu_V0, tcg_ctx->cpu_V0, tcg_ctx->cpu_V1);
                             break;
                         case 6: /* VQSHLU */
-                            gen_helper_neon_qshlu_s64(tcg_ctx, tcg_ctx->cpu_V0, tcg_ctx->cpu_env,
+                            gen_helper_neon_qshlu_s64(tcg_ctx, tcg_ctx->cpu_V0, uc->cpu_env,
                                                       tcg_ctx->cpu_V0, tcg_ctx->cpu_V1);
                             break;
                         case 7: /* VQSHL */
                             if (u) {
-                                gen_helper_neon_qshl_u64(tcg_ctx, tcg_ctx->cpu_V0, tcg_ctx->cpu_env,
+                                gen_helper_neon_qshl_u64(tcg_ctx, tcg_ctx->cpu_V0, uc->cpu_env,
                                                          tcg_ctx->cpu_V0, tcg_ctx->cpu_V1);
                             } else {
-                                gen_helper_neon_qshl_s64(tcg_ctx, tcg_ctx->cpu_V0, tcg_ctx->cpu_env,
+                                gen_helper_neon_qshl_s64(tcg_ctx, tcg_ctx->cpu_V0, uc->cpu_env,
                                                          tcg_ctx->cpu_V0, tcg_ctx->cpu_V1);
                             }
                             break;
@@ -6489,15 +6543,15 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
                         case 6: /* VQSHLU */
                             switch (size) {
                             case 0:
-                                gen_helper_neon_qshlu_s8(tcg_ctx, tmp, tcg_ctx->cpu_env,
+                                gen_helper_neon_qshlu_s8(tcg_ctx, tmp, uc->cpu_env,
                                                          tmp, tmp2);
                                 break;
                             case 1:
-                                gen_helper_neon_qshlu_s16(tcg_ctx, tmp, tcg_ctx->cpu_env,
+                                gen_helper_neon_qshlu_s16(tcg_ctx, tmp, uc->cpu_env,
                                                           tmp, tmp2);
                                 break;
                             case 2:
-                                gen_helper_neon_qshlu_s32(tcg_ctx, tmp, tcg_ctx->cpu_env,
+                                gen_helper_neon_qshlu_s32(tcg_ctx, tmp, uc->cpu_env,
                                                           tmp, tmp2);
                                 break;
                             default:
@@ -6681,7 +6735,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
                  */
                 shift = 32 - shift;
                 for (pass = 0; pass < (q ? 4 : 2); pass++) {
-                    tcg_gen_ld_f32(tcg_ctx, tcg_ctx->cpu_F0s, tcg_ctx->cpu_env, neon_reg_offset(rm, pass));
+                    tcg_gen_ld_f32(tcg_ctx, tcg_ctx->cpu_F0s, uc->cpu_env, neon_reg_offset(rm, pass));
                     if (!(op & 1)) {
                         if (u)
                             gen_vfp_ulto(s, 0, shift, 1);
@@ -6693,7 +6747,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
                         else
                             gen_vfp_tosl(s, 0, shift, 1);
                     }
-                    tcg_gen_st_f32(tcg_ctx, tcg_ctx->cpu_F0s, tcg_ctx->cpu_env, neon_reg_offset(rd, pass));
+                    tcg_gen_st_f32(tcg_ctx, tcg_ctx->cpu_F0s, uc->cpu_env, neon_reg_offset(rd, pass));
                 }
             } else {
                 return 1;
@@ -7038,15 +7092,15 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
                         tmp2 = neon_load_reg(tcg_ctx, rn, pass);
                         if (op == 12) {
                             if (size == 1) {
-                                gen_helper_neon_qdmulh_s16(tcg_ctx, tmp, tcg_ctx->cpu_env, tmp, tmp2);
+                                gen_helper_neon_qdmulh_s16(tcg_ctx, tmp, uc->cpu_env, tmp, tmp2);
                             } else {
-                                gen_helper_neon_qdmulh_s32(tcg_ctx, tmp, tcg_ctx->cpu_env, tmp, tmp2);
+                                gen_helper_neon_qdmulh_s32(tcg_ctx, tmp, uc->cpu_env, tmp, tmp2);
                             }
                         } else if (op == 13) {
                             if (size == 1) {
-                                gen_helper_neon_qrdmulh_s16(tcg_ctx, tmp, tcg_ctx->cpu_env, tmp, tmp2);
+                                gen_helper_neon_qrdmulh_s16(tcg_ctx, tmp, uc->cpu_env, tmp, tmp2);
                             } else {
-                                gen_helper_neon_qrdmulh_s32(tcg_ctx, tmp, tcg_ctx->cpu_env, tmp, tmp2);
+                                gen_helper_neon_qrdmulh_s32(tcg_ctx, tmp, uc->cpu_env, tmp, tmp2);
                             }
                         } else if (op & 1) {
                             TCGv_ptr fpstatus = get_fpstatus_ptr(s, 1);
@@ -7179,7 +7233,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
                         for (pass = 0; pass < (u ? 4 : 2); pass++) {
                             tmp = neon_load_reg(tcg_ctx, rn, pass);
                             tmp3 = neon_load_reg(tcg_ctx, rd, pass);
-                            fn(tcg_ctx, tmp, tcg_ctx->cpu_env, tmp, tmp2, tmp3);
+                            fn(tcg_ctx, tmp, uc->cpu_env, tmp, tmp2, tmp3);
                             tcg_temp_free_i32(tcg_ctx, tmp3);
                             neon_store_reg(tcg_ctx, rd, pass, tmp);
                         }
@@ -7370,18 +7424,18 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
                     }
                     tmp = tcg_temp_new_i32(tcg_ctx);
                     tmp2 = tcg_temp_new_i32(tcg_ctx);
-                    tcg_gen_ld_f32(tcg_ctx, tcg_ctx->cpu_F0s, tcg_ctx->cpu_env, neon_reg_offset(rm, 0));
-                    gen_helper_neon_fcvt_f32_to_f16(tcg_ctx, tmp, tcg_ctx->cpu_F0s, tcg_ctx->cpu_env);
-                    tcg_gen_ld_f32(tcg_ctx, tcg_ctx->cpu_F0s, tcg_ctx->cpu_env, neon_reg_offset(rm, 1));
-                    gen_helper_neon_fcvt_f32_to_f16(tcg_ctx, tmp2, tcg_ctx->cpu_F0s, tcg_ctx->cpu_env);
+                    tcg_gen_ld_f32(tcg_ctx, tcg_ctx->cpu_F0s, uc->cpu_env, neon_reg_offset(rm, 0));
+                    gen_helper_neon_fcvt_f32_to_f16(tcg_ctx, tmp, tcg_ctx->cpu_F0s, uc->cpu_env);
+                    tcg_gen_ld_f32(tcg_ctx, tcg_ctx->cpu_F0s, uc->cpu_env, neon_reg_offset(rm, 1));
+                    gen_helper_neon_fcvt_f32_to_f16(tcg_ctx, tmp2, tcg_ctx->cpu_F0s, uc->cpu_env);
                     tcg_gen_shli_i32(tcg_ctx, tmp2, tmp2, 16);
                     tcg_gen_or_i32(tcg_ctx, tmp2, tmp2, tmp);
-                    tcg_gen_ld_f32(tcg_ctx, tcg_ctx->cpu_F0s, tcg_ctx->cpu_env, neon_reg_offset(rm, 2));
-                    gen_helper_neon_fcvt_f32_to_f16(tcg_ctx, tmp, tcg_ctx->cpu_F0s, tcg_ctx->cpu_env);
-                    tcg_gen_ld_f32(tcg_ctx, tcg_ctx->cpu_F0s, tcg_ctx->cpu_env, neon_reg_offset(rm, 3));
+                    tcg_gen_ld_f32(tcg_ctx, tcg_ctx->cpu_F0s, uc->cpu_env, neon_reg_offset(rm, 2));
+                    gen_helper_neon_fcvt_f32_to_f16(tcg_ctx, tmp, tcg_ctx->cpu_F0s, uc->cpu_env);
+                    tcg_gen_ld_f32(tcg_ctx, tcg_ctx->cpu_F0s, uc->cpu_env, neon_reg_offset(rm, 3));
                     neon_store_reg(tcg_ctx, rd, 0, tmp2);
                     tmp2 = tcg_temp_new_i32(tcg_ctx);
-                    gen_helper_neon_fcvt_f32_to_f16(tcg_ctx, tmp2, tcg_ctx->cpu_F0s, tcg_ctx->cpu_env);
+                    gen_helper_neon_fcvt_f32_to_f16(tcg_ctx, tmp2, tcg_ctx->cpu_F0s, uc->cpu_env);
                     tcg_gen_shli_i32(tcg_ctx, tmp2, tmp2, 16);
                     tcg_gen_or_i32(tcg_ctx, tmp2, tmp2, tmp);
                     neon_store_reg(tcg_ctx, rd, 1, tmp2);
@@ -7396,18 +7450,18 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
                     tmp = neon_load_reg(tcg_ctx, rm, 0);
                     tmp2 = neon_load_reg(tcg_ctx, rm, 1);
                     tcg_gen_ext16u_i32(tcg_ctx, tmp3, tmp);
-                    gen_helper_neon_fcvt_f16_to_f32(tcg_ctx, tcg_ctx->cpu_F0s, tmp3, tcg_ctx->cpu_env);
-                    tcg_gen_st_f32(tcg_ctx, tcg_ctx->cpu_F0s, tcg_ctx->cpu_env, neon_reg_offset(rd, 0));
+                    gen_helper_neon_fcvt_f16_to_f32(tcg_ctx, tcg_ctx->cpu_F0s, tmp3, uc->cpu_env);
+                    tcg_gen_st_f32(tcg_ctx, tcg_ctx->cpu_F0s, uc->cpu_env, neon_reg_offset(rd, 0));
                     tcg_gen_shri_i32(tcg_ctx, tmp3, tmp, 16);
-                    gen_helper_neon_fcvt_f16_to_f32(tcg_ctx, tcg_ctx->cpu_F0s, tmp3, tcg_ctx->cpu_env);
-                    tcg_gen_st_f32(tcg_ctx, tcg_ctx->cpu_F0s, tcg_ctx->cpu_env, neon_reg_offset(rd, 1));
+                    gen_helper_neon_fcvt_f16_to_f32(tcg_ctx, tcg_ctx->cpu_F0s, tmp3, uc->cpu_env);
+                    tcg_gen_st_f32(tcg_ctx, tcg_ctx->cpu_F0s, uc->cpu_env, neon_reg_offset(rd, 1));
                     tcg_temp_free_i32(tcg_ctx, tmp);
                     tcg_gen_ext16u_i32(tcg_ctx, tmp3, tmp2);
-                    gen_helper_neon_fcvt_f16_to_f32(tcg_ctx, tcg_ctx->cpu_F0s, tmp3, tcg_ctx->cpu_env);
-                    tcg_gen_st_f32(tcg_ctx, tcg_ctx->cpu_F0s, tcg_ctx->cpu_env, neon_reg_offset(rd, 2));
+                    gen_helper_neon_fcvt_f16_to_f32(tcg_ctx, tcg_ctx->cpu_F0s, tmp3, uc->cpu_env);
+                    tcg_gen_st_f32(tcg_ctx, tcg_ctx->cpu_F0s, uc->cpu_env, neon_reg_offset(rd, 2));
                     tcg_gen_shri_i32(tcg_ctx, tmp3, tmp2, 16);
-                    gen_helper_neon_fcvt_f16_to_f32(tcg_ctx, tcg_ctx->cpu_F0s, tmp3, tcg_ctx->cpu_env);
-                    tcg_gen_st_f32(tcg_ctx, tcg_ctx->cpu_F0s, tcg_ctx->cpu_env, neon_reg_offset(rd, 3));
+                    gen_helper_neon_fcvt_f16_to_f32(tcg_ctx, tcg_ctx->cpu_F0s, tmp3, uc->cpu_env);
+                    tcg_gen_st_f32(tcg_ctx, tcg_ctx->cpu_F0s, uc->cpu_env, neon_reg_offset(rd, 3));
                     tcg_temp_free_i32(tcg_ctx, tmp2);
                     tcg_temp_free_i32(tcg_ctx, tmp3);
                     break;
@@ -7472,7 +7526,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
                 elementwise:
                     for (pass = 0; pass < (q ? 4 : 2); pass++) {
                         if (neon_2rm_is_float_op(op)) {
-                            tcg_gen_ld_f32(tcg_ctx, tcg_ctx->cpu_F0s, tcg_ctx->cpu_env,
+                            tcg_gen_ld_f32(tcg_ctx, tcg_ctx->cpu_F0s, uc->cpu_env,
                                            neon_reg_offset(rm, pass));
                             tmp = NULL;
                         } else {
@@ -7514,13 +7568,13 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
                         case NEON_2RM_VQABS:
                             switch (size) {
                             case 0:
-                                gen_helper_neon_qabs_s8(tcg_ctx, tmp, tcg_ctx->cpu_env, tmp);
+                                gen_helper_neon_qabs_s8(tcg_ctx, tmp, uc->cpu_env, tmp);
                                 break;
                             case 1:
-                                gen_helper_neon_qabs_s16(tcg_ctx, tmp, tcg_ctx->cpu_env, tmp);
+                                gen_helper_neon_qabs_s16(tcg_ctx, tmp, uc->cpu_env, tmp);
                                 break;
                             case 2:
-                                gen_helper_neon_qabs_s32(tcg_ctx, tmp, tcg_ctx->cpu_env, tmp);
+                                gen_helper_neon_qabs_s32(tcg_ctx, tmp, uc->cpu_env, tmp);
                                 break;
                             default: abort();
                             }
@@ -7528,13 +7582,13 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
                         case NEON_2RM_VQNEG:
                             switch (size) {
                             case 0:
-                                gen_helper_neon_qneg_s8(tcg_ctx, tmp, tcg_ctx->cpu_env, tmp);
+                                gen_helper_neon_qneg_s8(tcg_ctx, tmp, uc->cpu_env, tmp);
                                 break;
                             case 1:
-                                gen_helper_neon_qneg_s16(tcg_ctx, tmp, tcg_ctx->cpu_env, tmp);
+                                gen_helper_neon_qneg_s16(tcg_ctx, tmp, uc->cpu_env, tmp);
                                 break;
                             case 2:
-                                gen_helper_neon_qneg_s32(tcg_ctx, tmp, tcg_ctx->cpu_env, tmp);
+                                gen_helper_neon_qneg_s32(tcg_ctx, tmp, uc->cpu_env, tmp);
                                 break;
                             default: abort();
                             }
@@ -7670,10 +7724,10 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
 
                             tcg_rmode = tcg_const_i32(tcg_ctx, arm_rmode_to_sf(rmode));
                             gen_helper_set_neon_rmode(tcg_ctx, tcg_rmode, tcg_rmode,
-                                                      tcg_ctx->cpu_env);
+                                                      uc->cpu_env);
                             gen_helper_rints(tcg_ctx, tcg_ctx->cpu_F0s, tcg_ctx->cpu_F0s, fpstatus);
                             gen_helper_set_neon_rmode(tcg_ctx, tcg_rmode, tcg_rmode,
-                                                      tcg_ctx->cpu_env);
+                                                      uc->cpu_env);
                             tcg_temp_free_ptr(tcg_ctx, fpstatus);
                             tcg_temp_free_i32(tcg_ctx, tcg_rmode);
                             break;
@@ -7702,7 +7756,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
                             tcg_shift = tcg_const_i32(tcg_ctx, 0);
                             tcg_rmode = tcg_const_i32(tcg_ctx, arm_rmode_to_sf(rmode));
                             gen_helper_set_neon_rmode(tcg_ctx, tcg_rmode, tcg_rmode,
-                                                      tcg_ctx->cpu_env);
+                                                      uc->cpu_env);
 
                             if (is_signed) {
                                 gen_helper_vfp_tosls(tcg_ctx, tcg_ctx->cpu_F0s, tcg_ctx->cpu_F0s,
@@ -7713,7 +7767,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
                             }
 
                             gen_helper_set_neon_rmode(tcg_ctx, tcg_rmode, tcg_rmode,
-                                                      tcg_ctx->cpu_env);
+                                                      uc->cpu_env);
                             tcg_temp_free_i32(tcg_ctx, tcg_rmode);
                             tcg_temp_free_i32(tcg_ctx, tcg_shift);
                             tcg_temp_free_ptr(tcg_ctx, fpst);
@@ -7766,7 +7820,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
                             abort();
                         }
                         if (neon_2rm_is_float_op(op)) {
-                            tcg_gen_st_f32(tcg_ctx, tcg_ctx->cpu_F0s, tcg_ctx->cpu_env,
+                            tcg_gen_st_f32(tcg_ctx, tcg_ctx->cpu_F0s, uc->cpu_env,
                                            neon_reg_offset(rd, pass));
                         } else {
                             neon_store_reg(tcg_ctx, rd, pass, tmp);
@@ -7963,7 +8017,8 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn)
 {
     int cpnum, is64, crn, crm, opc1, opc2, isread, rt, rt2;
     const ARMCPRegInfo *ri;
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
 
     cpnum = (insn >> 8) & 0xf;
 
@@ -8064,7 +8119,7 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn)
             tmpptr = tcg_const_ptr(tcg_ctx, ri);
             tcg_syn = tcg_const_i32(tcg_ctx, syndrome);
             tcg_isread = tcg_const_i32(tcg_ctx, isread);
-            gen_helper_access_check_cp_reg(tcg_ctx, tcg_ctx->cpu_env, tmpptr, tcg_syn,
+            gen_helper_access_check_cp_reg(tcg_ctx, uc->cpu_env, tmpptr, tcg_syn,
                                            tcg_isread);
             tcg_temp_free_ptr(tcg_ctx, tmpptr);
             tcg_temp_free_i32(tcg_ctx, tcg_syn);
@@ -8104,11 +8159,11 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn)
                     TCGv_ptr tmpptr;
                     tmp64 = tcg_temp_new_i64(tcg_ctx);
                     tmpptr = tcg_const_ptr(tcg_ctx, ri);
-                    gen_helper_get_cp_reg64(tcg_ctx, tmp64, tcg_ctx->cpu_env, tmpptr);
+                    gen_helper_get_cp_reg64(tcg_ctx, tmp64, uc->cpu_env, tmpptr);
                     tcg_temp_free_ptr(tcg_ctx, tmpptr);
                 } else {
                     tmp64 = tcg_temp_new_i64(tcg_ctx);
-                    tcg_gen_ld_i64(tcg_ctx, tmp64, tcg_ctx->cpu_env, ri->fieldoffset);
+                    tcg_gen_ld_i64(tcg_ctx, tmp64, uc->cpu_env, ri->fieldoffset);
                 }
                 tmp = tcg_temp_new_i32(tcg_ctx);
                 tcg_gen_extrl_i64_i32(tcg_ctx, tmp, tmp64);
@@ -8126,10 +8181,10 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn)
                     TCGv_ptr tmpptr;
                     tmp = tcg_temp_new_i32(tcg_ctx);
                     tmpptr = tcg_const_ptr(tcg_ctx, ri);
-                    gen_helper_get_cp_reg(tcg_ctx, tmp, tcg_ctx->cpu_env, tmpptr);
+                    gen_helper_get_cp_reg(tcg_ctx, tmp, uc->cpu_env, tmpptr);
                     tcg_temp_free_ptr(tcg_ctx, tmpptr);
                 } else {
-                    tmp = load_cpu_offset(s->uc, ri->fieldoffset);
+                    tmp = load_cpu_offset(uc, ri->fieldoffset);
                 }
                 if (rt == 15) {
                     /* Destination register of r15 for 32 bit loads sets
@@ -8158,10 +8213,10 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn)
                 tcg_temp_free_i32(tcg_ctx, tmphi);
                 if (ri->writefn) {
                     TCGv_ptr tmpptr = tcg_const_ptr(tcg_ctx, ri);
-                    gen_helper_set_cp_reg64(tcg_ctx, tcg_ctx->cpu_env, tmpptr, tmp64);
+                    gen_helper_set_cp_reg64(tcg_ctx, uc->cpu_env, tmpptr, tmp64);
                     tcg_temp_free_ptr(tcg_ctx, tmpptr);
                 } else {
-                    tcg_gen_st_i64(tcg_ctx, tmp64, tcg_ctx->cpu_env, ri->fieldoffset);
+                    tcg_gen_st_i64(tcg_ctx, tmp64, uc->cpu_env, ri->fieldoffset);
                 }
                 tcg_temp_free_i64(tcg_ctx, tmp64);
             } else {
@@ -8170,7 +8225,7 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn)
                     TCGv_ptr tmpptr;
                     tmp = load_reg(s, rt);
                     tmpptr = tcg_const_ptr(tcg_ctx, ri);
-                    gen_helper_set_cp_reg(tcg_ctx, tcg_ctx->cpu_env, tmpptr, tmp);
+                    gen_helper_set_cp_reg(tcg_ctx, uc->cpu_env, tmpptr, tmp);
                     tcg_temp_free_ptr(tcg_ctx, tmpptr);
                     tcg_temp_free_i32(tcg_ctx, tmp);
                 } else {
@@ -8419,7 +8474,8 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
 static void gen_srs(DisasContext *s,
                     uint32_t mode, uint32_t amode, bool writeback)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     int32_t offset;
     TCGv_i32 addr, tmp;
     bool undef = false;
@@ -8483,7 +8539,7 @@ static void gen_srs(DisasContext *s,
     /* get_r13_banked() will raise an exception if called from System mode */
     gen_set_condexec(s);
     gen_set_pc_im(s, s->pc - 4);
-    gen_helper_get_r13_banked(tcg_ctx, addr, tcg_ctx->cpu_env, tmp);
+    gen_helper_get_r13_banked(tcg_ctx, addr, uc->cpu_env, tmp);
     tcg_temp_free_i32(tcg_ctx, tmp);
     switch (amode) {
     case 0: /* DA */
@@ -8505,7 +8561,7 @@ static void gen_srs(DisasContext *s,
     tmp = load_reg(s, 14);
     gen_aa32_st32(s, tmp, addr, get_mem_index(s));
     tcg_temp_free_i32(tcg_ctx, tmp);
-    tmp = load_cpu_field(s->uc, spsr);
+    tmp = load_cpu_field(uc, spsr);
     tcg_gen_addi_i32(tcg_ctx, addr, addr, 4);
     gen_aa32_st32(s, tmp, addr, get_mem_index(s));
     tcg_temp_free_i32(tcg_ctx, tmp);
@@ -8528,16 +8584,17 @@ static void gen_srs(DisasContext *s,
         }
         tcg_gen_addi_i32(tcg_ctx, addr, addr, offset);
         tmp = tcg_const_i32(tcg_ctx, mode);
-        gen_helper_set_r13_banked(tcg_ctx, tcg_ctx->cpu_env, tmp, addr);
+        gen_helper_set_r13_banked(tcg_ctx, uc->cpu_env, tmp, addr);
         tcg_temp_free_i32(tcg_ctx, tmp);
     }
     tcg_temp_free_i32(tcg_ctx, addr);
     s->base.is_jmp = DISAS_UPDATE;
 }
 
-static void disas_arm_insn(DisasContext *s, unsigned int insn)  // qq
+static void disas_arm_insn(DisasContext *s, unsigned int insn)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     unsigned int cond, val, op1, i, shift, rm, rs, rn, rd, sh;
     TCGv_i32 tmp;
     TCGv_i32 tmp2;
@@ -8555,8 +8612,8 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)  // qq
     }
 
     // Unicorn: trace this instruction on request
-    if (HOOK_EXISTS_BOUNDED(s->uc, UC_HOOK_CODE, s->pc - 4)) {
-        gen_uc_tracecode(tcg_ctx, 4, UC_HOOK_CODE_IDX, s->uc, s->pc - 4);
+    if (HOOK_EXISTS_BOUNDED(uc, UC_HOOK_CODE, s->pc - 4)) {
+        gen_uc_tracecode(tcg_ctx, 4, UC_HOOK_CODE_IDX, uc, s->pc - 4);
         // the callback might want to stop emulation immediately
         check_exit_request(tcg_ctx);
     }
@@ -8628,7 +8685,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)  // qq
             ARCH(6);
             /* setend */
             if (((insn >> 9) & 1) != !!(s->be_data == MO_BE)) {
-                gen_helper_setend(tcg_ctx, tcg_ctx->cpu_env);
+                gen_helper_setend(tcg_ctx, uc->cpu_env);
                 s->base.is_jmp = DISAS_UPDATE;
             }
             return;
@@ -8850,10 +8907,10 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)  // qq
                 if (op1 & 2) {
                     if (IS_USER(s))
                         goto illegal_op;
-                    tmp = load_cpu_field(s->uc, spsr);
+                    tmp = load_cpu_field(uc, spsr);
                 } else {
                     tmp = tcg_temp_new_i32(tcg_ctx);
-                    gen_helper_cpsr_read(tcg_ctx, tmp, tcg_ctx->cpu_env);
+                    gen_helper_cpsr_read(tcg_ctx, tmp, uc->cpu_env);
                 }
                 store_reg(s, rd, tmp);
             }
@@ -8939,11 +8996,11 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)  // qq
             tmp = load_reg(s, rm);
             tmp2 = load_reg(s, rn);
             if (op1 & 2)
-                gen_helper_double_saturate(tcg_ctx, tmp2, tcg_ctx->cpu_env, tmp2);
+                gen_helper_double_saturate(tcg_ctx, tmp2, uc->cpu_env, tmp2);
             if (op1 & 1)
-                gen_helper_sub_saturate(tcg_ctx, tmp, tcg_ctx->cpu_env, tmp, tmp2);
+                gen_helper_sub_saturate(tcg_ctx, tmp, uc->cpu_env, tmp, tmp2);
             else
-                gen_helper_add_saturate(tcg_ctx, tmp, tcg_ctx->cpu_env, tmp, tmp2);
+                gen_helper_add_saturate(tcg_ctx, tmp, uc->cpu_env, tmp, tmp2);
             tcg_temp_free_i32(tcg_ctx, tmp2);
             store_reg(s, rd, tmp);
             break;
@@ -9006,7 +9063,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)  // qq
                 tcg_temp_free_i64(tcg_ctx, tmp64);
                 if ((sh & 2) == 0) {
                     tmp2 = load_reg(s, rn);
-                    gen_helper_add_setq(tcg_ctx, tmp, tcg_ctx->cpu_env, tmp, tmp2);
+                    gen_helper_add_setq(tcg_ctx, tmp, uc->cpu_env, tmp, tmp2);
                     tcg_temp_free_i32(tcg_ctx, tmp2);
                 }
                 store_reg(s, rd, tmp);
@@ -9026,7 +9083,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)  // qq
                 } else {
                     if (op1 == 0) {
                         tmp2 = load_reg(s, rn);
-                        gen_helper_add_setq(tcg_ctx, tmp, tcg_ctx->cpu_env, tmp, tmp2);
+                        gen_helper_add_setq(tcg_ctx, tmp, uc->cpu_env, tmp, tmp2);
                         tcg_temp_free_i32(tcg_ctx, tmp2);
                     }
                     store_reg(s, rd, tmp);
@@ -9593,9 +9650,9 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)  // qq
                         sh = (insn >> 16) & 0x1f;
                         tmp2 = tcg_const_i32(tcg_ctx, sh);
                         if (insn & (1 << 22))
-                          gen_helper_usat(tcg_ctx, tmp, tcg_ctx->cpu_env, tmp, tmp2);
+                          gen_helper_usat(tcg_ctx, tmp, uc->cpu_env, tmp, tmp2);
                         else
-                          gen_helper_ssat(tcg_ctx, tmp, tcg_ctx->cpu_env, tmp, tmp2);
+                          gen_helper_ssat(tcg_ctx, tmp, uc->cpu_env, tmp, tmp2);
                         tcg_temp_free_i32(tcg_ctx, tmp2);
                         store_reg(s, rd, tmp);
                     } else if ((insn & 0x00300fe0) == 0x00200f20) {
@@ -9604,9 +9661,9 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)  // qq
                         sh = (insn >> 16) & 0x1f;
                         tmp2 = tcg_const_i32(tcg_ctx, sh);
                         if (insn & (1 << 22))
-                          gen_helper_usat16(tcg_ctx, tmp, tcg_ctx->cpu_env, tmp, tmp2);
+                          gen_helper_usat16(tcg_ctx, tmp, uc->cpu_env, tmp, tmp2);
                         else
-                          gen_helper_ssat16(tcg_ctx, tmp, tcg_ctx->cpu_env, tmp, tmp2);
+                          gen_helper_ssat16(tcg_ctx, tmp, uc->cpu_env, tmp, tmp2);
                         tcg_temp_free_i32(tcg_ctx, tmp2);
                         store_reg(s, rd, tmp);
                     } else if ((insn & 0x00700fe0) == 0x00000fa0) {
@@ -9614,7 +9671,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)  // qq
                         tmp = load_reg(s, rn);
                         tmp2 = load_reg(s, rm);
                         tmp3 = tcg_temp_new_i32(tcg_ctx);
-                        tcg_gen_ld_i32(tcg_ctx, tmp3, tcg_ctx->cpu_env, offsetof(CPUARMState, GE));
+                        tcg_gen_ld_i32(tcg_ctx, tmp3, uc->cpu_env, offsetof(CPUARMState, GE));
                         gen_helper_sel_flags(tcg_ctx, tmp, tmp3, tmp, tmp2);
                         tcg_temp_free_i32(tcg_ctx, tmp3);
                         tcg_temp_free_i32(tcg_ctx, tmp2);
@@ -9738,13 +9795,13 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)  // qq
                                  * signed operation, in which case we must set
                                  * the Q flag.
                                  */
-                                gen_helper_add_setq(tcg_ctx, tmp, tcg_ctx->cpu_env, tmp, tmp2);
+                                gen_helper_add_setq(tcg_ctx, tmp, uc->cpu_env, tmp, tmp2);
                             }
                             tcg_temp_free_i32(tcg_ctx, tmp2);
                             if (rd != 15)
                               {
                                 tmp2 = load_reg(s, rd);
-                                gen_helper_add_setq(tcg_ctx, tmp, tcg_ctx->cpu_env, tmp, tmp2);
+                                gen_helper_add_setq(tcg_ctx, tmp, uc->cpu_env, tmp, tmp2);
                                 tcg_temp_free_i32(tcg_ctx, tmp2);
                               }
                             store_reg(s, rn, tmp);
@@ -9948,7 +10005,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)  // qq
                             gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
                             if (user) {
                                 tmp2 = tcg_const_i32(tcg_ctx, i);
-                                gen_helper_set_user_reg(tcg_ctx, tcg_ctx->cpu_env, tmp2, tmp);
+                                gen_helper_set_user_reg(tcg_ctx, uc->cpu_env, tmp2, tmp);
                                 tcg_temp_free_i32(tcg_ctx, tmp2);
                                 tcg_temp_free_i32(tcg_ctx, tmp);
                             } else if (i == rn) {
@@ -9969,7 +10026,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)  // qq
                             } else if (user) {
                                 tmp = tcg_temp_new_i32(tcg_ctx);
                                 tmp2 = tcg_const_i32(tcg_ctx, i);
-                                gen_helper_get_user_reg(tcg_ctx, tmp, tcg_ctx->cpu_env, tmp2);
+                                gen_helper_get_user_reg(tcg_ctx, tmp, uc->cpu_env, tmp2);
                                 tcg_temp_free_i32(tcg_ctx, tmp2);
                             } else {
                                 tmp = load_reg(s, i);
@@ -10011,8 +10068,8 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)  // qq
                 }
                 if (exc_return) {
                     /* Restore CPSR from SPSR.  */
-                    tmp = load_cpu_field(s->uc, spsr);
-                    gen_helper_cpsr_write_eret(tcg_ctx, tcg_ctx->cpu_env, tmp);
+                    tmp = load_cpu_field(uc, spsr);
+                    gen_helper_cpsr_write_eret(tcg_ctx, uc->cpu_env, tmp);
                     tcg_temp_free_i32(tcg_ctx, tmp);
                     /* Must exit loop to check un-masked IRQs */
                     s->base.is_jmp = DISAS_EXIT;
@@ -10189,7 +10246,8 @@ gen_thumb2_data_op(DisasContext *s, int op, int conds, uint32_t shifter_out,
 /* Translate a 32-bit thumb instruction. */
 static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     uint32_t imm, shift, offset;
     uint32_t rd, rn, rm, rs;
     TCGv_i32 tmp;
@@ -10322,7 +10380,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
                         addr = load_reg(s, rn);
                         op = tcg_const_i32(tcg_ctx, extract32(insn, 6, 2));
                         ttresp = tcg_temp_new_i32(tcg_ctx);
-                        gen_helper_v7m_tt(tcg_ctx, ttresp, tcg_ctx->cpu_env, addr, op);
+                        gen_helper_v7m_tt(tcg_ctx, ttresp, uc->cpu_env, addr, op);
                         tcg_temp_free_i32(tcg_ctx, addr);
                         tcg_temp_free_i32(tcg_ctx, op);
                         store_reg(s, rd, ttresp);
@@ -10672,11 +10730,11 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
                 tmp = load_reg(s, rn);
                 tmp2 = load_reg(s, rm);
                 if (op & 1)
-                    gen_helper_double_saturate(tcg_ctx, tmp, tcg_ctx->cpu_env, tmp);
+                    gen_helper_double_saturate(tcg_ctx, tmp, uc->cpu_env, tmp);
                 if (op & 2)
-                    gen_helper_sub_saturate(tcg_ctx, tmp, tcg_ctx->cpu_env, tmp2, tmp);
+                    gen_helper_sub_saturate(tcg_ctx, tmp, uc->cpu_env, tmp2, tmp);
                 else
-                    gen_helper_add_saturate(tcg_ctx, tmp, tcg_ctx->cpu_env, tmp, tmp2);
+                    gen_helper_add_saturate(tcg_ctx, tmp, uc->cpu_env, tmp, tmp2);
                 tcg_temp_free_i32(tcg_ctx, tmp2);
             } else {
                 switch (op) {
@@ -10721,7 +10779,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
                 case 0x10: /* sel */
                     tmp2 = load_reg(s, rm);
                     tmp3 = tcg_temp_new_i32(tcg_ctx);
-                    tcg_gen_ld_i32(tcg_ctx, tmp3, tcg_ctx->cpu_env, offsetof(CPUARMState, GE));
+                    tcg_gen_ld_i32(tcg_ctx, tmp3, uc->cpu_env, offsetof(CPUARMState, GE));
                     gen_helper_sel_flags(tcg_ctx, tmp, tmp3, tmp, tmp2);
                     tcg_temp_free_i32(tcg_ctx, tmp3);
                     tcg_temp_free_i32(tcg_ctx, tmp2);
@@ -10798,7 +10856,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
                 tcg_temp_free_i32(tcg_ctx, tmp2);
                 if (rs != 15) {
                     tmp2 = load_reg(s, rs);
-                    gen_helper_add_setq(tcg_ctx, tmp, tcg_ctx->cpu_env, tmp, tmp2);
+                    gen_helper_add_setq(tcg_ctx, tmp, uc->cpu_env, tmp, tmp2);
                     tcg_temp_free_i32(tcg_ctx, tmp2);
                 }
                 break;
@@ -10815,13 +10873,13 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
                      * however it may overflow considered as a signed
                      * operation, in which case we must set the Q flag.
                      */
-                    gen_helper_add_setq(tcg_ctx, tmp, tcg_ctx->cpu_env, tmp, tmp2);
+                    gen_helper_add_setq(tcg_ctx, tmp, uc->cpu_env, tmp, tmp2);
                 }
                 tcg_temp_free_i32(tcg_ctx, tmp2);
                 if (rs != 15)
                   {
                     tmp2 = load_reg(s, rs);
-                    gen_helper_add_setq(tcg_ctx, tmp, tcg_ctx->cpu_env, tmp, tmp2);
+                    gen_helper_add_setq(tcg_ctx, tmp, uc->cpu_env, tmp, tmp2);
                     tcg_temp_free_i32(tcg_ctx, tmp2);
                   }
                 break;
@@ -10838,7 +10896,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
                 if (rs != 15)
                   {
                     tmp2 = load_reg(s, rs);
-                    gen_helper_add_setq(tcg_ctx, tmp, tcg_ctx->cpu_env, tmp, tmp2);
+                    gen_helper_add_setq(tcg_ctx, tmp, uc->cpu_env, tmp, tmp2);
                     tcg_temp_free_i32(tcg_ctx, tmp2);
                   }
                 break;
@@ -11054,7 +11112,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
                             tmp = load_reg(s, rn);
                             /* the constant is the mask and SYSm fields */
                             addr = tcg_const_i32(tcg_ctx, insn & 0xfff);
-                            gen_helper_v7m_msr(tcg_ctx, tcg_ctx->cpu_env, addr, tmp);
+                            gen_helper_v7m_msr(tcg_ctx, uc->cpu_env, addr, tmp);
                             tcg_temp_free_i32(tcg_ctx, addr);
                             tcg_temp_free_i32(tcg_ctx, tmp);
                             gen_lookup_tb(s);
@@ -11177,10 +11235,10 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
                         tmp = tcg_temp_new_i32(tcg_ctx);
                         if (arm_dc_feature(s, ARM_FEATURE_M)) {
                             addr = tcg_const_i32(tcg_ctx, insn & 0xff);
-                            gen_helper_v7m_mrs(tcg_ctx, tmp, tcg_ctx->cpu_env, addr);
+                            gen_helper_v7m_mrs(tcg_ctx, tmp, uc->cpu_env, addr);
                             tcg_temp_free_i32(tcg_ctx, addr);
                         } else {
-                            gen_helper_cpsr_read(tcg_ctx, tmp, tcg_ctx->cpu_env);
+                            gen_helper_cpsr_read(tcg_ctx, tmp, uc->cpu_env);
                         }
                         store_reg(s, rd, tmp);
                         break;
@@ -11206,7 +11264,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
                             goto illegal_op;
                         }
 
-                        tmp = load_cpu_field(s->uc, spsr);
+                        tmp = load_cpu_field(uc, spsr);
                         store_reg(s, rd, tmp);
                         break;
                     }
@@ -11294,9 +11352,9 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
                                     tcg_temp_free_i32(tcg_ctx, tmp2);
                                     goto illegal_op;
                                 }
-                                gen_helper_usat16(tcg_ctx, tmp, tcg_ctx->cpu_env, tmp, tmp2);
+                                gen_helper_usat16(tcg_ctx, tmp, uc->cpu_env, tmp, tmp2);
                             } else {
-                                gen_helper_usat(tcg_ctx, tmp, tcg_ctx->cpu_env, tmp, tmp2);
+                                gen_helper_usat(tcg_ctx, tmp, uc->cpu_env, tmp, tmp2);
                             }
                         } else {
                             /* Signed.  */
@@ -11306,9 +11364,9 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
                                     tcg_temp_free_i32(tcg_ctx, tmp2);
                                     goto illegal_op;
                                 }
-                                gen_helper_ssat16(tcg_ctx, tmp, tcg_ctx->cpu_env, tmp, tmp2);
+                                gen_helper_ssat16(tcg_ctx, tmp, uc->cpu_env, tmp, tmp2);
                             } else {
-                                gen_helper_ssat(tcg_ctx, tmp, tcg_ctx->cpu_env, tmp, tmp2);
+                                gen_helper_ssat(tcg_ctx, tmp, uc->cpu_env, tmp, tmp2);
                             }
                         }
                         tcg_temp_free_i32(tcg_ctx, tmp2);
@@ -11583,7 +11641,8 @@ illegal_op:
 
 static void disas_thumb_insn(DisasContext *s, uint32_t insn)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     uint32_t val, op, rm, rn, rd, shift, cond;
     int32_t offset;
     int i;
@@ -11599,18 +11658,18 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
     }
 
     // Unicorn: trace this instruction on request
-    if (HOOK_EXISTS_BOUNDED(s->uc, UC_HOOK_CODE, s->pc)) {
+    if (HOOK_EXISTS_BOUNDED(uc, UC_HOOK_CODE, s->pc)) {
         // determine instruction size (Thumb/Thumb2)
         switch(insn & 0xf800) {
             // Thumb2: 32-bit
             case 0xe800:
             case 0xf000:
             case 0xf800:
-                gen_uc_tracecode(tcg_ctx, 4, UC_HOOK_CODE_IDX, s->uc, s->pc);
+                gen_uc_tracecode(tcg_ctx, 4, UC_HOOK_CODE_IDX, uc, s->pc);
                 break;
             // Thumb: 16-bit
             default:
-                gen_uc_tracecode(tcg_ctx, 2, UC_HOOK_CODE_IDX, s->uc, s->pc);
+                gen_uc_tracecode(tcg_ctx, 2, UC_HOOK_CODE_IDX, uc, s->pc);
                 break;
         }
         // the callback might want to stop emulation immediately
@@ -11826,7 +11885,7 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
             if (s->condexec_mask) {
                 gen_shl(s, tmp2, tmp2, tmp);
             } else {
-                gen_helper_shl_cc(tcg_ctx, tmp2, tcg_ctx->cpu_env, tmp2, tmp);
+                gen_helper_shl_cc(tcg_ctx, tmp2, uc->cpu_env, tmp2, tmp);
                 gen_logic_CC(s, tmp2);
             }
             break;
@@ -11834,7 +11893,7 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
             if (s->condexec_mask) {
                 gen_shr(s, tmp2, tmp2, tmp);
             } else {
-                gen_helper_shr_cc(tcg_ctx, tmp2, tcg_ctx->cpu_env, tmp2, tmp);
+                gen_helper_shr_cc(tcg_ctx, tmp2, uc->cpu_env, tmp2, tmp);
                 gen_logic_CC(s, tmp2);
             }
             break;
@@ -11842,7 +11901,7 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
             if (s->condexec_mask) {
                 gen_sar(s, tmp2, tmp2, tmp);
             } else {
-                gen_helper_sar_cc(tcg_ctx, tmp2, tcg_ctx->cpu_env, tmp2, tmp);
+                gen_helper_sar_cc(tcg_ctx, tmp2, uc->cpu_env, tmp2, tmp);
                 gen_logic_CC(s, tmp2);
             }
             break;
@@ -11865,7 +11924,7 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
                 tcg_gen_andi_i32(tcg_ctx, tmp, tmp, 0x1f);
                 tcg_gen_rotr_i32(tcg_ctx, tmp2, tmp2, tmp);
             } else {
-                gen_helper_ror_cc(tcg_ctx, tmp2, tcg_ctx->cpu_env, tmp2, tmp);
+                gen_helper_ror_cc(tcg_ctx, tmp2, uc->cpu_env, tmp2, tmp);
                 gen_logic_CC(s, tmp2);
             }
             break;
@@ -12235,7 +12294,7 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
                 /* setend */
                 ARCH(6);
                 if (((insn >> 3) & 1) != !!(s->be_data == MO_BE)) {
-                    gen_helper_setend(tcg_ctx, tcg_ctx->cpu_env);
+                    gen_helper_setend(tcg_ctx, uc->cpu_env);
                     s->base.is_jmp = DISAS_UPDATE;
                 }
                 break;
@@ -12250,13 +12309,13 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
                     /* FAULTMASK */
                     if (insn & 1) {
                         addr = tcg_const_i32(tcg_ctx, 19);
-                        gen_helper_v7m_msr(tcg_ctx, tcg_ctx->cpu_env, addr, tmp);
+                        gen_helper_v7m_msr(tcg_ctx, uc->cpu_env, addr, tmp);
                         tcg_temp_free_i32(tcg_ctx, addr);
                     }
                     /* PRIMASK */
                     if (insn & 2) {
                         addr = tcg_const_i32(tcg_ctx, 16);
-                        gen_helper_v7m_msr(tcg_ctx, tcg_ctx->cpu_env, addr, tmp);
+                        gen_helper_v7m_msr(tcg_ctx, uc->cpu_env, addr, tmp);
                         tcg_temp_free_i32(tcg_ctx, addr);
                     }
                     tcg_temp_free_i32(tcg_ctx, tmp);
@@ -12563,12 +12622,13 @@ static bool arm_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,
                                     const CPUBreakpoint *bp)
 {
     DisasContext *dc = container_of(dcbase, DisasContext, base);
-    TCGContext *tcg_ctx = cpu->uc->tcg_ctx;
+    struct uc_struct *uc = cpu->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
 
     if (bp->flags & BP_CPU) {
         gen_set_condexec(dc);
         gen_set_pc_im(dc, dc->pc);
-        gen_helper_check_breakpoints(tcg_ctx, tcg_ctx->cpu_env);
+        gen_helper_check_breakpoints(tcg_ctx, uc->cpu_env);
         /* End the TB early; it's likely not going to be executed */
         dc->base.is_jmp = DISAS_TOO_MANY;
     } else {
@@ -12775,7 +12835,8 @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
 static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
 {
     DisasContext *dc = container_of(dcbase, DisasContext, base);
-    TCGContext *tcg_ctx = cpu->uc->tcg_ctx;
+    struct uc_struct *uc = cpu->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
 
     if (tb_cflags(dc->base.tb) & CF_LAST_IO && dc->condjmp) {
         /* FIXME: This can theoretically happen with self-modifying code. */
@@ -12853,7 +12914,7 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
             TCGv_i32 tmp = tcg_const_i32(tcg_ctx, (dc->thumb &&
                                           !(dc->insn & (1U << 31))) ? 2 : 4);
 
-            gen_helper_wfi(tcg_ctx, tcg_ctx->cpu_env, tmp);
+            gen_helper_wfi(tcg_ctx, uc->cpu_env, tmp);
             tcg_temp_free_i32(tcg_ctx, tmp);
             /* The helper doesn't necessarily throw an exception, but we
              * must go back to the main loop to check for interrupts anyway.
@@ -12862,10 +12923,10 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
             break;
         }
         case DISAS_WFE:
-            gen_helper_wfe(tcg_ctx, tcg_ctx->cpu_env);
+            gen_helper_wfe(tcg_ctx, uc->cpu_env);
             break;
         case DISAS_YIELD:
-            gen_helper_yield(tcg_ctx, tcg_ctx->cpu_env);
+            gen_helper_yield(tcg_ctx, uc->cpu_env);
             break;
         case DISAS_SWI:
             gen_exception(dc, EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb),
diff --git a/qemu/target/i386/translate.c b/qemu/target/i386/translate.c
index 65327539..e5ff101d 100644
--- a/qemu/target/i386/translate.c
+++ b/qemu/target/i386/translate.c
@@ -466,7 +466,7 @@ static void gen_add_A0_im(DisasContext *s, int val)
 
 static inline void gen_op_jmp_v(TCGContext *s, TCGv dest)
 {
-    tcg_gen_st_tl(s, dest, s->cpu_env, offsetof(CPUX86State, eip));
+    tcg_gen_st_tl(s, dest, s->uc->cpu_env, offsetof(CPUX86State, eip));
 }
 
 static inline void gen_op_add_reg_im(TCGContext *s, TCGMemOp size, int reg, int32_t val)
@@ -604,7 +604,7 @@ static inline void gen_op_movl_T0_Dshift(TCGContext *s, TCGMemOp ot)
 {
     TCGv cpu_T0 = s->cpu_T0;
 
-    tcg_gen_ld32s_tl(s, cpu_T0, s->cpu_env, offsetof(CPUX86State, df));
+    tcg_gen_ld32s_tl(s, cpu_T0, s->uc->cpu_env, offsetof(CPUX86State, df));
     tcg_gen_shli_tl(s, cpu_T0, cpu_T0, ot);
 };
 
@@ -671,15 +671,17 @@ static inline void gen_op_jz_ecx(TCGContext *s, TCGMemOp size, TCGLabel *label1)
 
 static void gen_helper_in_func(TCGContext *s, TCGMemOp ot, TCGv v, TCGv_i32 n)
 {
+    TCGv_env cpu_env = s->uc->cpu_env;
+
     switch (ot) {
     case MO_8:
-        gen_helper_inb(s, v, s->cpu_env, n);
+        gen_helper_inb(s, v, cpu_env, n);
         break;
     case MO_16:
-        gen_helper_inw(s, v, s->cpu_env, n);
+        gen_helper_inw(s, v, cpu_env, n);
         break;
     case MO_32:
-        gen_helper_inl(s, v, s->cpu_env, n);
+        gen_helper_inl(s, v, cpu_env, n);
         break;
     default:
         tcg_abort();
@@ -688,15 +690,17 @@ static void gen_helper_in_func(TCGContext *s, TCGMemOp ot, TCGv v, TCGv_i32 n)
 
 static void gen_helper_out_func(TCGContext *s, TCGMemOp ot, TCGv_i32 v, TCGv_i32 n)
 {
+    TCGv_env cpu_env = s->uc->cpu_env;
+
     switch (ot) {
     case MO_8:
-        gen_helper_outb(s, s->cpu_env, v, n);
+        gen_helper_outb(s, cpu_env, v, n);
         break;
     case MO_16:
-        gen_helper_outw(s, s->cpu_env, v, n);
+        gen_helper_outw(s, cpu_env, v, n);
         break;
     case MO_32:
-        gen_helper_outl(s, s->cpu_env, v, n);
+        gen_helper_outl(s, cpu_env, v, n);
         break;
     default:
         tcg_abort();
@@ -707,6 +711,7 @@ static void gen_check_io(DisasContext *s, TCGMemOp ot, target_ulong cur_eip,
                          uint32_t svm_flags)
 {
     target_ulong next_eip;
+    struct uc_struct *uc = s->uc;
     TCGContext *tcg_ctx = s->uc->tcg_ctx;
     TCGv_i32 cpu_tmp2_i32 = tcg_ctx->cpu_tmp2_i32;
     TCGv cpu_T0 = tcg_ctx->cpu_T0;
@@ -718,13 +723,13 @@ static void gen_check_io(DisasContext *s, TCGMemOp ot, target_ulong cur_eip,
         tcg_gen_trunc_tl_i32(tcg_ctx, cpu_tmp2_i32, cpu_T0);
         switch (ot) {
         case MO_8:
-            gen_helper_check_iob(tcg_ctx, tcg_ctx->cpu_env, cpu_tmp2_i32);
+            gen_helper_check_iob(tcg_ctx, uc->cpu_env, cpu_tmp2_i32);
             break;
         case MO_16:
-            gen_helper_check_iow(tcg_ctx, tcg_ctx->cpu_env, cpu_tmp2_i32);
+            gen_helper_check_iow(tcg_ctx, uc->cpu_env, cpu_tmp2_i32);
             break;
         case MO_32:
-            gen_helper_check_iol(tcg_ctx, tcg_ctx->cpu_env, cpu_tmp2_i32);
+            gen_helper_check_iol(tcg_ctx, uc->cpu_env, cpu_tmp2_i32);
             break;
         default:
             tcg_abort();
@@ -736,7 +741,7 @@ static void gen_check_io(DisasContext *s, TCGMemOp ot, target_ulong cur_eip,
         svm_flags |= (1 << (4 + ot));
         next_eip = s->pc - s->cs_base;
         tcg_gen_trunc_tl_i32(tcg_ctx, cpu_tmp2_i32, cpu_T0);
-        gen_helper_svm_check_io(tcg_ctx, tcg_ctx->cpu_env, cpu_tmp2_i32,
+        gen_helper_svm_check_io(tcg_ctx, uc->cpu_env, cpu_tmp2_i32,
                                 tcg_const_i32(tcg_ctx, svm_flags),
                                 tcg_const_i32(tcg_ctx, next_eip - cur_eip));
     }
@@ -1285,13 +1290,14 @@ static inline void gen_cmps(DisasContext *s, TCGMemOp ot)
 
 static void gen_bpt_io(DisasContext *s, TCGv_i32 t_port, int ot)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
 
     if (s->flags & HF_IOBPT_MASK) {
         TCGv_i32 t_size = tcg_const_i32(tcg_ctx, 1 << ot);
         TCGv t_next = tcg_const_tl(tcg_ctx, s->pc - s->cs_base);
 
-        gen_helper_bpt_io(tcg_ctx, tcg_ctx->cpu_env, t_port, t_size, t_next);
+        gen_helper_bpt_io(tcg_ctx, uc->cpu_env, t_port, t_size, t_next);
         tcg_temp_free_i32(tcg_ctx, t_size);
         tcg_temp_free(tcg_ctx, t_next);
     }
@@ -1387,30 +1393,32 @@ GEN_REPZ2(cmps)
 
 static void gen_helper_fp_arith_ST0_FT0(TCGContext *s, int op)
 {
+    TCGv_env cpu_env = s->uc->cpu_env;
+
     switch (op) {
     case 0:
-        gen_helper_fadd_ST0_FT0(s, s->cpu_env);
+        gen_helper_fadd_ST0_FT0(s, cpu_env);
         break;
     case 1:
-        gen_helper_fmul_ST0_FT0(s, s->cpu_env);
+        gen_helper_fmul_ST0_FT0(s, cpu_env);
         break;
     case 2:
-        gen_helper_fcom_ST0_FT0(s, s->cpu_env);
+        gen_helper_fcom_ST0_FT0(s, cpu_env);
         break;
     case 3:
-        gen_helper_fcom_ST0_FT0(s, s->cpu_env);
+        gen_helper_fcom_ST0_FT0(s, cpu_env);
         break;
     case 4:
-        gen_helper_fsub_ST0_FT0(s, s->cpu_env);
+        gen_helper_fsub_ST0_FT0(s, cpu_env);
         break;
     case 5:
-        gen_helper_fsubr_ST0_FT0(s, s->cpu_env);
+        gen_helper_fsubr_ST0_FT0(s, cpu_env);
         break;
     case 6:
-        gen_helper_fdiv_ST0_FT0(s, s->cpu_env);
+        gen_helper_fdiv_ST0_FT0(s, cpu_env);
         break;
     case 7:
-        gen_helper_fdivr_ST0_FT0(s, s->cpu_env);
+        gen_helper_fdivr_ST0_FT0(s, cpu_env);
         break;
     }
 }
@@ -1418,25 +1426,26 @@ static void gen_helper_fp_arith_ST0_FT0(TCGContext *s, int op)
 /* NOTE the exception in "r" op ordering */
 static void gen_helper_fp_arith_STN_ST0(TCGContext *s, int op, int opreg)
 {
+    TCGv_env cpu_env = s->uc->cpu_env;
     TCGv_i32 tmp = tcg_const_i32(s, opreg);
     switch (op) {
     case 0:
-        gen_helper_fadd_STN_ST0(s, s->cpu_env, tmp);
+        gen_helper_fadd_STN_ST0(s, cpu_env, tmp);
         break;
     case 1:
-        gen_helper_fmul_STN_ST0(s, s->cpu_env, tmp);
+        gen_helper_fmul_STN_ST0(s, cpu_env, tmp);
         break;
     case 4:
-        gen_helper_fsubr_STN_ST0(s, s->cpu_env, tmp);
+        gen_helper_fsubr_STN_ST0(s, cpu_env, tmp);
         break;
     case 5:
-        gen_helper_fsub_STN_ST0(s, s->cpu_env, tmp);
+        gen_helper_fsub_STN_ST0(s, cpu_env, tmp);
         break;
     case 6:
-        gen_helper_fdivr_STN_ST0(s, s->cpu_env, tmp);
+        gen_helper_fdivr_STN_ST0(s, cpu_env, tmp);
         break;
     case 7:
-        gen_helper_fdiv_STN_ST0(s, s->cpu_env, tmp);
+        gen_helper_fdiv_STN_ST0(s, cpu_env, tmp);
         break;
     }
 }
@@ -1905,7 +1914,8 @@ static void gen_rot_rm_im(DisasContext *s, TCGMemOp ot, int op1, int op2,
 static void gen_rotc_rm_T1(DisasContext *s, TCGMemOp ot, int op1,
                            int is_right)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv cpu_A0 = tcg_ctx->cpu_A0;
     TCGv cpu_T0 = tcg_ctx->cpu_T0;
     TCGv cpu_T1 = tcg_ctx->cpu_T1;
@@ -1922,17 +1932,17 @@ static void gen_rotc_rm_T1(DisasContext *s, TCGMemOp ot, int op1,
     if (is_right) {
         switch (ot) {
         case MO_8:
-            gen_helper_rcrb(tcg_ctx, cpu_T0, tcg_ctx->cpu_env, cpu_T0, cpu_T1);
+            gen_helper_rcrb(tcg_ctx, cpu_T0, uc->cpu_env, cpu_T0, cpu_T1);
             break;
         case MO_16:
-            gen_helper_rcrw(tcg_ctx, cpu_T0, tcg_ctx->cpu_env, cpu_T0, cpu_T1);
+            gen_helper_rcrw(tcg_ctx, cpu_T0, uc->cpu_env, cpu_T0, cpu_T1);
             break;
         case MO_32:
-            gen_helper_rcrl(tcg_ctx, cpu_T0, tcg_ctx->cpu_env, cpu_T0, cpu_T1);
+            gen_helper_rcrl(tcg_ctx, cpu_T0, uc->cpu_env, cpu_T0, cpu_T1);
             break;
 #ifdef TARGET_X86_64
         case MO_64:
-            gen_helper_rcrq(tcg_ctx, cpu_T0, tcg_ctx->cpu_env, cpu_T0, cpu_T1);
+            gen_helper_rcrq(tcg_ctx, cpu_T0, uc->cpu_env, cpu_T0, cpu_T1);
             break;
 #endif
         default:
@@ -1941,17 +1951,17 @@ static void gen_rotc_rm_T1(DisasContext *s, TCGMemOp ot, int op1,
     } else {
         switch (ot) {
         case MO_8:
-            gen_helper_rclb(tcg_ctx, cpu_T0, tcg_ctx->cpu_env, cpu_T0, cpu_T1);
+            gen_helper_rclb(tcg_ctx, cpu_T0, uc->cpu_env, cpu_T0, cpu_T1);
             break;
         case MO_16:
-            gen_helper_rclw(tcg_ctx, cpu_T0, tcg_ctx->cpu_env, cpu_T0, cpu_T1);
+            gen_helper_rclw(tcg_ctx, cpu_T0, uc->cpu_env, cpu_T0, cpu_T1);
             break;
         case MO_32:
-            gen_helper_rcll(tcg_ctx, cpu_T0, tcg_ctx->cpu_env, cpu_T0, cpu_T1);
+            gen_helper_rcll(tcg_ctx, cpu_T0, uc->cpu_env, cpu_T0, cpu_T1);
             break;
 #ifdef TARGET_X86_64
         case MO_64:
-            gen_helper_rclq(tcg_ctx, cpu_T0, tcg_ctx->cpu_env, cpu_T0, cpu_T1);
+            gen_helper_rclq(tcg_ctx, cpu_T0, uc->cpu_env, cpu_T0, cpu_T1);
             break;
 #endif
         default:
@@ -2352,7 +2362,8 @@ static void gen_nop_modrm(CPUX86State *env, DisasContext *s, int modrm)
 static void gen_bndck(CPUX86State *env, DisasContext *s, int modrm,
                       TCGCond cond, TCGv_i64 bndv)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv_i64 cpu_tmp1_i64 = tcg_ctx->cpu_tmp1_i64;
     TCGv_i32 cpu_tmp2_i32 = tcg_ctx->cpu_tmp2_i32;
 
@@ -2364,7 +2375,7 @@ static void gen_bndck(CPUX86State *env, DisasContext *s, int modrm,
     }
     tcg_gen_setcond_i64(tcg_ctx, cond, cpu_tmp1_i64, cpu_tmp1_i64, bndv);
     tcg_gen_extrl_i64_i32(tcg_ctx, cpu_tmp2_i32, cpu_tmp1_i64);
-    gen_helper_bndck(tcg_ctx, tcg_ctx->cpu_env, cpu_tmp2_i32);
+    gen_helper_bndck(tcg_ctx, uc->cpu_env, cpu_tmp2_i32);
 }
 
 /* used for LEA and MOV AX, mem */
@@ -2538,7 +2549,7 @@ static inline void gen_op_movl_T0_seg(TCGContext *s, int seg_reg)
 {
     TCGv cpu_T0 = s->cpu_T0;
 
-    tcg_gen_ld32u_tl(s, cpu_T0, s->cpu_env,
+    tcg_gen_ld32u_tl(s, cpu_T0, s->uc->cpu_env,
                      offsetof(CPUX86State,segs[seg_reg].selector));
 }
 
@@ -2548,7 +2559,7 @@ static inline void gen_op_movl_seg_T0_vm(TCGContext *s, int seg_reg)
     TCGv *cpu_seg_base = s->cpu_seg_base;
 
     tcg_gen_ext16u_tl(s, cpu_T0, cpu_T0);
-    tcg_gen_st32_tl(s, cpu_T0, s->cpu_env,
+    tcg_gen_st32_tl(s, cpu_T0, s->uc->cpu_env,
                     offsetof(CPUX86State,segs[seg_reg].selector));
     tcg_gen_shli_tl(s, cpu_seg_base[seg_reg], cpu_T0, 4);
 }
@@ -2557,13 +2568,14 @@ static inline void gen_op_movl_seg_T0_vm(TCGContext *s, int seg_reg)
    call this function with seg_reg == R_CS */
 static void gen_movl_seg_T0(DisasContext *s, int seg_reg)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv_i32 cpu_tmp2_i32 = tcg_ctx->cpu_tmp2_i32;
     TCGv cpu_T0 = tcg_ctx->cpu_T0;
 
     if (s->pe && !s->vm86) {
         tcg_gen_trunc_tl_i32(tcg_ctx, cpu_tmp2_i32, cpu_T0);
-        gen_helper_load_seg(tcg_ctx, tcg_ctx->cpu_env, tcg_const_i32(tcg_ctx, seg_reg), cpu_tmp2_i32);
+        gen_helper_load_seg(tcg_ctx, uc->cpu_env, tcg_const_i32(tcg_ctx, seg_reg), cpu_tmp2_i32);
         /* abort translation because the addseg value may change or
            because ss32 may change. For R_SS, translation must always
            stop as a special handling must be done to disable hardware
@@ -2588,14 +2600,15 @@ static inline void
 gen_svm_check_intercept_param(DisasContext *s, target_ulong pc_start,
                               uint32_t type, uint64_t param)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
 
     /* no SVM activated; fast case */
     if (likely(!(s->flags & HF_SVMI_MASK)))
         return;
     gen_update_cc_op(s);
     gen_jmp_im(s, pc_start - s->cs_base);
-    gen_helper_svm_check_intercept_param(tcg_ctx, tcg_ctx->cpu_env, tcg_const_i32(tcg_ctx, type),
+    gen_helper_svm_check_intercept_param(tcg_ctx, uc->cpu_env, tcg_const_i32(tcg_ctx, type),
                                          tcg_const_i64(tcg_ctx, param));
 }
 
@@ -2776,11 +2789,12 @@ static void gen_leave(DisasContext *s)
 
 static void gen_exception(DisasContext *s, int trapno, target_ulong cur_eip)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
 
     gen_update_cc_op(s);
     gen_jmp_im(s, cur_eip);
-    gen_helper_raise_exception(tcg_ctx, tcg_ctx->cpu_env, tcg_const_i32(tcg_ctx, trapno));
+    gen_helper_raise_exception(tcg_ctx, uc->cpu_env, tcg_const_i32(tcg_ctx, trapno));
     s->base.is_jmp = DISAS_NORETURN;
 }
 
@@ -2813,30 +2827,33 @@ static void gen_unknown_opcode(CPUX86State *env, DisasContext *s)
 static void gen_interrupt(DisasContext *s, int intno,
                           target_ulong cur_eip, target_ulong next_eip)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
 
     gen_update_cc_op(s);
     // Unicorn: skip to the next instruction after our interrupt callback
     gen_jmp_im(s, cur_eip);
-    gen_helper_raise_interrupt(tcg_ctx, tcg_ctx->cpu_env, tcg_const_i32(tcg_ctx, intno),
+    gen_helper_raise_interrupt(tcg_ctx, uc->cpu_env, tcg_const_i32(tcg_ctx, intno),
                                tcg_const_i32(tcg_ctx, next_eip - cur_eip));
     s->base.is_jmp = DISAS_NORETURN;
 }
 
 static void gen_debug(DisasContext *s, target_ulong cur_eip)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
 
     gen_update_cc_op(s);
     gen_jmp_im(s, cur_eip);
-    gen_helper_debug(tcg_ctx, tcg_ctx->cpu_env);
+    gen_helper_debug(tcg_ctx, uc->cpu_env);
     s->base.is_jmp = DISAS_NORETURN;
 }
 
 static void gen_set_hflag(DisasContext *s, uint32_t mask)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
-    TCGv_ptr cpu_env = tcg_ctx->cpu_env;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
+    TCGv_ptr cpu_env = uc->cpu_env;
 
     if ((s->flags & mask) == 0) {
         TCGv_i32 t = tcg_temp_new_i32(tcg_ctx);
@@ -2850,8 +2867,9 @@ static void gen_set_hflag(DisasContext *s, uint32_t mask)
 
 static void gen_reset_hflag(DisasContext *s, uint32_t mask)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
-    TCGv_ptr cpu_env = tcg_ctx->cpu_env;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
+    TCGv_ptr cpu_env = uc->cpu_env;
 
     if (s->flags & mask) {
         TCGv_i32 t = tcg_temp_new_i32(tcg_ctx);
@@ -2866,8 +2884,9 @@ static void gen_reset_hflag(DisasContext *s, uint32_t mask)
 /* Clear BND registers during legacy branches.  */
 static void gen_bnd_jmp(DisasContext *s)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
-    TCGv_ptr cpu_env = tcg_ctx->cpu_env;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
+    TCGv_ptr cpu_env = uc->cpu_env;
 
     /* Clear the registers only if BND prefix is missing, MPX is enabled,
        and if the BNDREGs are known to be in use (non-zero) already.
@@ -2886,7 +2905,8 @@ static void gen_bnd_jmp(DisasContext *s)
 static void
 do_gen_eob_worker(DisasContext *s, bool inhibit, bool recheck_tf, bool jr)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
 
     gen_update_cc_op(s);
 
@@ -2898,15 +2918,15 @@ do_gen_eob_worker(DisasContext *s, bool inhibit, bool recheck_tf, bool jr)
     }
 
     if (s->base.tb->flags & HF_RF_MASK) {
-        gen_helper_reset_rf(tcg_ctx, tcg_ctx->cpu_env);
+        gen_helper_reset_rf(tcg_ctx, uc->cpu_env);
     }
     if (s->base.singlestep_enabled) {
-        gen_helper_debug(tcg_ctx, tcg_ctx->cpu_env);
+        gen_helper_debug(tcg_ctx, uc->cpu_env);
     } else if (recheck_tf) {
-        gen_helper_rechecking_single_step(tcg_ctx, tcg_ctx->cpu_env);
+        gen_helper_rechecking_single_step(tcg_ctx, uc->cpu_env);
         tcg_gen_exit_tb(tcg_ctx, 0);
     } else if (s->tf) {
-        gen_helper_single_step(tcg_ctx, tcg_ctx->cpu_env);
+        gen_helper_single_step(tcg_ctx, uc->cpu_env);
     } else if (jr) {
         tcg_gen_lookup_and_goto_ptr(tcg_ctx);
     } else {
@@ -2961,84 +2981,93 @@ static void gen_jmp(DisasContext *s, target_ulong eip)
 
 static inline void gen_ldq_env_A0(DisasContext *s, int offset)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv_i64 cpu_tmp1_i64 = tcg_ctx->cpu_tmp1_i64;
     TCGv cpu_A0 = tcg_ctx->cpu_A0;
 
-    tcg_gen_qemu_ld_i64(s->uc, cpu_tmp1_i64, cpu_A0, s->mem_index, MO_LEQ);
-    tcg_gen_st_i64(tcg_ctx, cpu_tmp1_i64, tcg_ctx->cpu_env, offset);
+    tcg_gen_qemu_ld_i64(uc, cpu_tmp1_i64, cpu_A0, s->mem_index, MO_LEQ);
+    tcg_gen_st_i64(tcg_ctx, cpu_tmp1_i64, uc->cpu_env, offset);
 }
 
 static inline void gen_stq_env_A0(DisasContext *s, int offset)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv_i64 cpu_tmp1_i64 = tcg_ctx->cpu_tmp1_i64;
     TCGv cpu_A0 = tcg_ctx->cpu_A0;
 
-    tcg_gen_ld_i64(tcg_ctx, cpu_tmp1_i64, tcg_ctx->cpu_env, offset);
-    tcg_gen_qemu_st_i64(s->uc, cpu_tmp1_i64, cpu_A0, s->mem_index, MO_LEQ);
+    tcg_gen_ld_i64(tcg_ctx, cpu_tmp1_i64, uc->cpu_env, offset);
+    tcg_gen_qemu_st_i64(uc, cpu_tmp1_i64, cpu_A0, s->mem_index, MO_LEQ);
 }
 
 static inline void gen_ldo_env_A0(DisasContext *s, int offset)
 {
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     int mem_index = s->mem_index;
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
     TCGv_i64 cpu_tmp1_i64 = tcg_ctx->cpu_tmp1_i64;
     TCGv cpu_A0 = tcg_ctx->cpu_A0;
     TCGv cpu_tmp0 = tcg_ctx->cpu_tmp0;
 
-    tcg_gen_qemu_ld_i64(s->uc, cpu_tmp1_i64, cpu_A0, mem_index, MO_LEQ);
-    tcg_gen_st_i64(tcg_ctx, cpu_tmp1_i64, tcg_ctx->cpu_env, offset + offsetof(ZMMReg, ZMM_Q(0)));
+    tcg_gen_qemu_ld_i64(uc, cpu_tmp1_i64, cpu_A0, mem_index, MO_LEQ);
+    tcg_gen_st_i64(tcg_ctx, cpu_tmp1_i64, uc->cpu_env, offset + offsetof(ZMMReg, ZMM_Q(0)));
     tcg_gen_addi_tl(tcg_ctx, cpu_tmp0, cpu_A0, 8);
-    tcg_gen_qemu_ld_i64(s->uc, cpu_tmp1_i64, cpu_tmp0, mem_index, MO_LEQ);
-    tcg_gen_st_i64(tcg_ctx, cpu_tmp1_i64, tcg_ctx->cpu_env, offset + offsetof(ZMMReg, ZMM_Q(1)));
+    tcg_gen_qemu_ld_i64(uc, cpu_tmp1_i64, cpu_tmp0, mem_index, MO_LEQ);
+    tcg_gen_st_i64(tcg_ctx, cpu_tmp1_i64, uc->cpu_env, offset + offsetof(ZMMReg, ZMM_Q(1)));
 }
 
 static inline void gen_sto_env_A0(DisasContext *s, int offset)
 {
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     int mem_index = s->mem_index;
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
     TCGv_i64 cpu_tmp1_i64 = tcg_ctx->cpu_tmp1_i64;
     TCGv cpu_A0 = tcg_ctx->cpu_A0;
     TCGv cpu_tmp0 = tcg_ctx->cpu_tmp0;
 
-    tcg_gen_ld_i64(tcg_ctx, cpu_tmp1_i64, tcg_ctx->cpu_env, offset + offsetof(ZMMReg, ZMM_Q(0)));
-    tcg_gen_qemu_st_i64(s->uc, cpu_tmp1_i64, cpu_A0, mem_index, MO_LEQ);
+    tcg_gen_ld_i64(tcg_ctx, cpu_tmp1_i64, uc->cpu_env, offset + offsetof(ZMMReg, ZMM_Q(0)));
+    tcg_gen_qemu_st_i64(uc, cpu_tmp1_i64, cpu_A0, mem_index, MO_LEQ);
     tcg_gen_addi_tl(tcg_ctx, cpu_tmp0, cpu_A0, 8);
-    tcg_gen_ld_i64(tcg_ctx, cpu_tmp1_i64, tcg_ctx->cpu_env, offset + offsetof(ZMMReg, ZMM_Q(1)));
-    tcg_gen_qemu_st_i64(s->uc, cpu_tmp1_i64, cpu_tmp0, mem_index, MO_LEQ);
+    tcg_gen_ld_i64(tcg_ctx, cpu_tmp1_i64, uc->cpu_env, offset + offsetof(ZMMReg, ZMM_Q(1)));
+    tcg_gen_qemu_st_i64(uc, cpu_tmp1_i64, cpu_tmp0, mem_index, MO_LEQ);
 }
 
 static inline void gen_op_movo(TCGContext *s, int d_offset, int s_offset)
 {
+    TCGv_env cpu_env = s->uc->cpu_env;
     TCGv_i64 cpu_tmp1_i64 = s->cpu_tmp1_i64;
 
-    tcg_gen_ld_i64(s, cpu_tmp1_i64, s->cpu_env, s_offset);
-    tcg_gen_st_i64(s, cpu_tmp1_i64, s->cpu_env, d_offset);
-    tcg_gen_ld_i64(s, cpu_tmp1_i64, s->cpu_env, s_offset + 8);
-    tcg_gen_st_i64(s, cpu_tmp1_i64, s->cpu_env, d_offset + 8);
+    tcg_gen_ld_i64(s, cpu_tmp1_i64, cpu_env, s_offset);
+    tcg_gen_st_i64(s, cpu_tmp1_i64, cpu_env, d_offset);
+    tcg_gen_ld_i64(s, cpu_tmp1_i64, cpu_env, s_offset + 8);
+    tcg_gen_st_i64(s, cpu_tmp1_i64, cpu_env, d_offset + 8);
 }
 
 static inline void gen_op_movq(TCGContext *s, int d_offset, int s_offset)
 {
+    TCGv_env cpu_env = s->uc->cpu_env;
     TCGv_i64 cpu_tmp1_i64 = s->cpu_tmp1_i64;
 
-    tcg_gen_ld_i64(s, cpu_tmp1_i64, s->cpu_env, s_offset);
-    tcg_gen_st_i64(s, cpu_tmp1_i64, s->cpu_env, d_offset);
+    tcg_gen_ld_i64(s, cpu_tmp1_i64, cpu_env, s_offset);
+    tcg_gen_st_i64(s, cpu_tmp1_i64, cpu_env, d_offset);
 }
 
 static inline void gen_op_movl(TCGContext *s, int d_offset, int s_offset)
 {
-    tcg_gen_ld_i32(s, s->cpu_tmp2_i32, s->cpu_env, s_offset);
-    tcg_gen_st_i32(s, s->cpu_tmp2_i32, s->cpu_env, d_offset);
+    TCGv_env cpu_env = s->uc->cpu_env;
+
+    tcg_gen_ld_i32(s, s->cpu_tmp2_i32, cpu_env, s_offset);
+    tcg_gen_st_i32(s, s->cpu_tmp2_i32, cpu_env, d_offset);
 }
 
 static inline void gen_op_movq_env_0(TCGContext *s, int d_offset)
 {
+    TCGv_env cpu_env = s->uc->cpu_env;
     TCGv_i64 cpu_tmp1_i64 = s->cpu_tmp1_i64;
 
     tcg_gen_movi_i64(s, cpu_tmp1_i64, 0);
-    tcg_gen_st_i64(s, cpu_tmp1_i64, s->cpu_env, d_offset);
+    tcg_gen_st_i64(s, cpu_tmp1_i64, cpu_env, d_offset);
 }
 
 typedef void (*SSEFunc_i_ep)(TCGContext *s, TCGv_i32 val, TCGv_ptr env, TCGv_ptr reg);
@@ -3571,8 +3600,9 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
     SSEFunc_0_ppi sse_fn_ppi;
     SSEFunc_0_eppt sse_fn_eppt;
     TCGMemOp ot;
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
-    TCGv_ptr cpu_env = tcg_ctx->cpu_env;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
+    TCGv_ptr cpu_env = uc->cpu_env;
     TCGv_ptr cpu_ptr0 = tcg_ctx->cpu_ptr0;
     TCGv_ptr cpu_ptr1 = tcg_ctx->cpu_ptr1;
     TCGv_i32 cpu_tmp2_i32 = tcg_ctx->cpu_tmp2_i32;
@@ -4251,13 +4281,13 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
                         break;
                     case 0x21: case 0x31: /* pmovsxbd, pmovzxbd */
                     case 0x24: case 0x34: /* pmovsxwq, pmovzxwq */
-                        tcg_gen_qemu_ld_i32(s->uc, cpu_tmp2_i32, cpu_A0,
+                        tcg_gen_qemu_ld_i32(uc, cpu_tmp2_i32, cpu_A0,
                                             s->mem_index, MO_LEUL);
                         tcg_gen_st_i32(tcg_ctx, cpu_tmp2_i32, cpu_env, op2_offset +
                                         offsetof(ZMMReg, ZMM_L(0)));
                         break;
                     case 0x22: case 0x32: /* pmovsxbq, pmovzxbq */
-                        tcg_gen_qemu_ld_tl(s->uc, cpu_tmp0, cpu_A0,
+                        tcg_gen_qemu_ld_tl(uc, cpu_tmp0, cpu_A0,
                                            s->mem_index, MO_LEUW);
                         tcg_gen_st16_tl(tcg_ctx, cpu_tmp0, cpu_env, op2_offset +
                                         offsetof(ZMMReg, ZMM_W(0)));
@@ -4346,11 +4376,11 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
 
                 gen_lea_modrm(env, s, modrm);
                 if ((b & 1) == 0) {
-                    tcg_gen_qemu_ld_tl(s->uc, cpu_T0, cpu_A0,
+                    tcg_gen_qemu_ld_tl(uc, cpu_T0, cpu_A0,
                                        s->mem_index, ot | MO_BE);
                     gen_op_mov_reg_v(tcg_ctx, ot, reg, cpu_T0);
                 } else {
-                    tcg_gen_qemu_st_tl(s->uc, cpu_regs[reg], cpu_A0,
+                    tcg_gen_qemu_st_tl(uc, cpu_regs[reg], cpu_A0,
                                        s->mem_index, ot | MO_BE);
                 }
                 break;
@@ -4689,7 +4719,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
                     if (mod == 3) {
                         gen_op_mov_reg_v(tcg_ctx, ot, rm, cpu_T0);
                     } else {
-                        tcg_gen_qemu_st_tl(s->uc, cpu_T0, cpu_A0,
+                        tcg_gen_qemu_st_tl(uc, cpu_T0, cpu_A0,
                                            s->mem_index, MO_UB);
                     }
                     break;
@@ -4699,7 +4729,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
                     if (mod == 3) {
                         gen_op_mov_reg_v(tcg_ctx, ot, rm, cpu_T0);
                     } else {
-                        tcg_gen_qemu_st_tl(s->uc, cpu_T0, cpu_A0,
+                        tcg_gen_qemu_st_tl(uc, cpu_T0, cpu_A0,
                                            s->mem_index, MO_LEUW);
                     }
                     break;
@@ -4711,7 +4741,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
                         if (mod == 3) {
                             tcg_gen_extu_i32_tl(tcg_ctx, cpu_regs[rm], cpu_tmp2_i32);
                         } else {
-                            tcg_gen_qemu_st_i32(s->uc, cpu_tmp2_i32, cpu_A0,
+                            tcg_gen_qemu_st_i32(uc, cpu_tmp2_i32, cpu_A0,
                                                 s->mem_index, MO_LEUL);
                         }
                     } else { /* pextrq */
@@ -4722,7 +4752,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
                         if (mod == 3) {
                             tcg_gen_mov_i64(tcg_ctx, cpu_regs[rm], cpu_tmp1_i64);
                         } else {
-                            tcg_gen_qemu_st_i64(s->uc, cpu_tmp1_i64, cpu_A0,
+                            tcg_gen_qemu_st_i64(uc, cpu_tmp1_i64, cpu_A0,
                                                 s->mem_index, MO_LEQ);
                         }
 #else
@@ -4736,7 +4766,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
                     if (mod == 3) {
                         gen_op_mov_reg_v(tcg_ctx, ot, rm, cpu_T0);
                     } else {
-                        tcg_gen_qemu_st_tl(s->uc, cpu_T0, cpu_A0,
+                        tcg_gen_qemu_st_tl(uc, cpu_T0, cpu_A0,
                                            s->mem_index, MO_LEUL);
                     }
                     break;
@@ -4744,7 +4774,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
                     if (mod == 3) {
                         gen_op_mov_v_reg(tcg_ctx, MO_32, cpu_T0, rm);
                     } else {
-                        tcg_gen_qemu_ld_tl(s->uc, cpu_T0, cpu_A0,
+                        tcg_gen_qemu_ld_tl(uc, cpu_T0, cpu_A0,
                                            s->mem_index, MO_UB);
                     }
                     tcg_gen_st8_tl(tcg_ctx, cpu_T0, cpu_env, offsetof(CPUX86State,
@@ -4756,7 +4786,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
                                         offsetof(CPUX86State,xmm_regs[rm]
                                                 .ZMM_L((val >> 6) & 3)));
                     } else {
-                        tcg_gen_qemu_ld_i32(s->uc, cpu_tmp2_i32, cpu_A0,
+                        tcg_gen_qemu_ld_i32(uc, cpu_tmp2_i32, cpu_A0,
                                             s->mem_index, MO_LEUL);
                     }
                     tcg_gen_st_i32(tcg_ctx, cpu_tmp2_i32, cpu_env,
@@ -4784,7 +4814,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
                         if (mod == 3) {
                             tcg_gen_trunc_tl_i32(tcg_ctx, cpu_tmp2_i32, cpu_regs[rm]);
                         } else {
-                            tcg_gen_qemu_ld_i32(s->uc, cpu_tmp2_i32, cpu_A0,
+                            tcg_gen_qemu_ld_i32(uc, cpu_tmp2_i32, cpu_A0,
                                                 s->mem_index, MO_LEUL);
                         }
                         tcg_gen_st_i32(tcg_ctx, cpu_tmp2_i32, cpu_env,
@@ -4795,7 +4825,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
                         if (mod == 3) {
                             gen_op_mov_v_reg(tcg_ctx, ot, cpu_tmp1_i64, rm);
                         } else {
-                            tcg_gen_qemu_ld_i64(s->uc, cpu_tmp1_i64, cpu_A0,
+                            tcg_gen_qemu_ld_i64(uc, cpu_tmp1_i64, cpu_A0,
                                                 s->mem_index, MO_LEQ);
                         }
                         tcg_gen_st_i64(tcg_ctx, cpu_tmp1_i64, cpu_env,
@@ -5014,7 +5044,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
 static void sync_eflags(DisasContext *s, TCGContext *tcg_ctx)
 {
     TCGv cpu_T0 = tcg_ctx->cpu_T0;
-    TCGv_ptr cpu_env = tcg_ctx->cpu_env;
+    TCGv_ptr cpu_env = tcg_ctx->uc->cpu_env;
 
     gen_update_cc_op(s);
     gen_helper_read_eflags(tcg_ctx, cpu_T0, cpu_env);
@@ -5025,7 +5055,7 @@ static void sync_eflags(DisasContext *s, TCGContext *tcg_ctx)
 static void restore_eflags(DisasContext *s, TCGContext *tcg_ctx)
 {
     TCGv cpu_T0 = tcg_ctx->cpu_T0;
-    TCGv_ptr cpu_env = tcg_ctx->cpu_env;
+    TCGv_ptr cpu_env = tcg_ctx->uc->cpu_env;
 
     tcg_gen_ld_tl(tcg_ctx, cpu_T0, cpu_env, offsetof(CPUX86State, eflags));
     gen_helper_write_eflags(tcg_ctx, cpu_env, cpu_T0, 
@@ -5046,8 +5076,9 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
     target_ulong next_eip, tval;
     int rex_w, rex_r;
     target_ulong pc_start = s->base.pc_next;
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
-    TCGv_ptr cpu_env = tcg_ctx->cpu_env;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
+    TCGv_ptr cpu_env = uc->cpu_env;
     TCGv_i32 cpu_tmp2_i32 = tcg_ctx->cpu_tmp2_i32;
     TCGv_i32 cpu_tmp3_i32 = tcg_ctx->cpu_tmp3_i32;
     TCGv_i64 cpu_tmp1_i64 = tcg_ctx->cpu_tmp1_i64;
@@ -5691,7 +5722,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
                                       tcg_const_i32(tcg_ctx, dflag - 1),
                                       tcg_const_i32(tcg_ctx, s->pc - s->cs_base));
             }
-            tcg_gen_ld_tl(tcg_ctx, cpu_tmp4, tcg_ctx->cpu_env, offsetof(CPUX86State, eip));
+            tcg_gen_ld_tl(tcg_ctx, cpu_tmp4, cpu_env, offsetof(CPUX86State, eip));
             gen_jr(s, cpu_tmp4);
             break;
         case 4: /* jmp Ev */
@@ -5715,7 +5746,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
                 gen_op_movl_seg_T0_vm(tcg_ctx, R_CS);
                 gen_op_jmp_v(tcg_ctx, cpu_T1);
             }
-            tcg_gen_ld_tl(tcg_ctx, cpu_tmp4, tcg_ctx->cpu_env, offsetof(CPUX86State, eip));
+            tcg_gen_ld_tl(tcg_ctx, cpu_tmp4, cpu_env, offsetof(CPUX86State, eip));
             gen_jr(s, cpu_tmp4);
             break;
         case 6: /* push Ev */
@@ -6445,23 +6476,23 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
 
                     switch(op >> 4) {
                     case 0:
-                        tcg_gen_qemu_ld_i32(s->uc, cpu_tmp2_i32, cpu_A0,
+                        tcg_gen_qemu_ld_i32(uc, cpu_tmp2_i32, cpu_A0,
                                             s->mem_index, MO_LEUL);
                         gen_helper_flds_FT0(tcg_ctx, cpu_env, cpu_tmp2_i32);
                         break;
                     case 1:
-                        tcg_gen_qemu_ld_i32(s->uc, cpu_tmp2_i32, cpu_A0,
+                        tcg_gen_qemu_ld_i32(uc, cpu_tmp2_i32, cpu_A0,
                                             s->mem_index, MO_LEUL);
                         gen_helper_fildl_FT0(tcg_ctx, cpu_env, cpu_tmp2_i32);
                         break;
                     case 2:
-                        tcg_gen_qemu_ld_i64(s->uc, cpu_tmp1_i64, cpu_A0,
+                        tcg_gen_qemu_ld_i64(uc, cpu_tmp1_i64, cpu_A0,
                                             s->mem_index, MO_LEQ);
                         gen_helper_fldl_FT0(tcg_ctx, cpu_env, cpu_tmp1_i64);
                         break;
                     case 3:
                     default:
-                        tcg_gen_qemu_ld_i32(s->uc, cpu_tmp2_i32, cpu_A0,
+                        tcg_gen_qemu_ld_i32(uc, cpu_tmp2_i32, cpu_A0,
                                             s->mem_index, MO_LESW);
                         gen_helper_fildl_FT0(tcg_ctx, cpu_env, cpu_tmp2_i32);
                         break;
@@ -6484,23 +6515,23 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
                 case 0:
                     switch(op >> 4) {
                     case 0:
-                        tcg_gen_qemu_ld_i32(s->uc, cpu_tmp2_i32, cpu_A0,
+                        tcg_gen_qemu_ld_i32(uc, cpu_tmp2_i32, cpu_A0,
                                             s->mem_index, MO_LEUL);
                         gen_helper_flds_ST0(tcg_ctx, cpu_env, cpu_tmp2_i32);
                         break;
                     case 1:
-                        tcg_gen_qemu_ld_i32(s->uc, cpu_tmp2_i32, cpu_A0,
+                        tcg_gen_qemu_ld_i32(uc, cpu_tmp2_i32, cpu_A0,
                                             s->mem_index, MO_LEUL);
                         gen_helper_fildl_ST0(tcg_ctx, cpu_env, cpu_tmp2_i32);
                         break;
                     case 2:
-                        tcg_gen_qemu_ld_i64(s->uc, cpu_tmp1_i64, cpu_A0,
+                        tcg_gen_qemu_ld_i64(uc, cpu_tmp1_i64, cpu_A0,
                                             s->mem_index, MO_LEQ);
                         gen_helper_fldl_ST0(tcg_ctx, cpu_env, cpu_tmp1_i64);
                         break;
                     case 3:
                     default:
-                        tcg_gen_qemu_ld_i32(s->uc, cpu_tmp2_i32, cpu_A0,
+                        tcg_gen_qemu_ld_i32(uc, cpu_tmp2_i32, cpu_A0,
                                             s->mem_index, MO_LESW);
                         gen_helper_fildl_ST0(tcg_ctx, cpu_env, cpu_tmp2_i32);
                         break;
@@ -6511,18 +6542,18 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
                     switch(op >> 4) {
                     case 1:
                         gen_helper_fisttl_ST0(tcg_ctx, cpu_tmp2_i32, cpu_env);
-                        tcg_gen_qemu_st_i32(s->uc, cpu_tmp2_i32, cpu_A0,
+                        tcg_gen_qemu_st_i32(uc, cpu_tmp2_i32, cpu_A0,
                                             s->mem_index, MO_LEUL);
                         break;
                     case 2:
                         gen_helper_fisttll_ST0(tcg_ctx, cpu_tmp1_i64, cpu_env);
-                        tcg_gen_qemu_st_i64(s->uc, cpu_tmp1_i64, cpu_A0,
+                        tcg_gen_qemu_st_i64(uc, cpu_tmp1_i64, cpu_A0,
                                             s->mem_index, MO_LEQ);
                         break;
                     case 3:
                     default:
                         gen_helper_fistt_ST0(tcg_ctx, cpu_tmp2_i32, cpu_env);
-                        tcg_gen_qemu_st_i32(s->uc, cpu_tmp2_i32, cpu_A0,
+                        tcg_gen_qemu_st_i32(uc, cpu_tmp2_i32, cpu_A0,
                                             s->mem_index, MO_LEUW);
                         break;
                     }
@@ -6532,23 +6563,23 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
                     switch(op >> 4) {
                     case 0:
                         gen_helper_fsts_ST0(tcg_ctx, cpu_tmp2_i32, cpu_env);
-                        tcg_gen_qemu_st_i32(s->uc, cpu_tmp2_i32, cpu_A0,
+                        tcg_gen_qemu_st_i32(uc, cpu_tmp2_i32, cpu_A0,
                                             s->mem_index, MO_LEUL);
                         break;
                     case 1:
                         gen_helper_fistl_ST0(tcg_ctx, cpu_tmp2_i32, cpu_env);
-                        tcg_gen_qemu_st_i32(s->uc, cpu_tmp2_i32, cpu_A0,
+                        tcg_gen_qemu_st_i32(uc, cpu_tmp2_i32, cpu_A0,
                                             s->mem_index, MO_LEUL);
                         break;
                     case 2:
                         gen_helper_fstl_ST0(tcg_ctx, cpu_tmp1_i64, cpu_env);
-                        tcg_gen_qemu_st_i64(s->uc, cpu_tmp1_i64, cpu_A0,
+                        tcg_gen_qemu_st_i64(uc, cpu_tmp1_i64, cpu_A0,
                                             s->mem_index, MO_LEQ);
                         break;
                     case 3:
                     default:
                         gen_helper_fist_ST0(tcg_ctx, cpu_tmp2_i32, cpu_env);
-                        tcg_gen_qemu_st_i32(s->uc, cpu_tmp2_i32, cpu_A0,
+                        tcg_gen_qemu_st_i32(uc, cpu_tmp2_i32, cpu_A0,
                                             s->mem_index, MO_LEUW);
                         break;
                     }
@@ -6563,7 +6594,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
             }
             else if(op == 0x0d) /* fldcw mem */
             {
-                tcg_gen_qemu_ld_i32(s->uc, cpu_tmp2_i32, cpu_A0,
+                tcg_gen_qemu_ld_i32(uc, cpu_tmp2_i32, cpu_A0,
                                     s->mem_index, MO_LEUW);
                 gen_helper_fldcw(tcg_ctx, cpu_env, cpu_tmp2_i32);
             }
@@ -6574,7 +6605,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
             else if(op == 0x0f) /* fnstcw mem */
             {
                 gen_helper_fnstcw(tcg_ctx, cpu_tmp2_i32, cpu_env);
-                tcg_gen_qemu_st_i32(s->uc, cpu_tmp2_i32, cpu_A0,
+                tcg_gen_qemu_st_i32(uc, cpu_tmp2_i32, cpu_A0,
                                     s->mem_index, MO_LEUW);
             }
             else if(op == 0x1d) /* fldt mem */
@@ -6597,7 +6628,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
             else if(op == 0x2f) /* fnstsw mem */
             {
                 gen_helper_fnstsw(tcg_ctx, cpu_tmp2_i32, cpu_env);
-                tcg_gen_qemu_st_i32(s->uc, cpu_tmp2_i32, cpu_A0,
+                tcg_gen_qemu_st_i32(uc, cpu_tmp2_i32, cpu_A0,
                                     s->mem_index, MO_LEUW);
             }
             else if(op == 0x3c) /* fbld */
@@ -6611,13 +6642,13 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
             }
             else if(op == 0x3d) /* fildll */
             {
-                tcg_gen_qemu_ld_i64(s->uc, cpu_tmp1_i64, cpu_A0, s->mem_index, MO_LEQ);
+                tcg_gen_qemu_ld_i64(uc, cpu_tmp1_i64, cpu_A0, s->mem_index, MO_LEQ);
                 gen_helper_fildll_ST0(tcg_ctx, cpu_env, cpu_tmp1_i64);
             }
             else if(op == 0x3f) /* fistpll */
             {
                 gen_helper_fistll_ST0(tcg_ctx, cpu_tmp1_i64, cpu_env);
-                tcg_gen_qemu_st_i64(s->uc, cpu_tmp1_i64, cpu_A0, s->mem_index, MO_LEQ);
+                tcg_gen_qemu_st_i64(uc, cpu_tmp1_i64, cpu_A0, s->mem_index, MO_LEQ);
                 gen_helper_fpop(tcg_ctx, cpu_env);
             }
             else
@@ -7667,7 +7698,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
         break;
     case 0xfb: /* sti */
         if (s->vm86 ? s->iopl == 3 : s->cpl <= s->iopl) {
-            gen_helper_sti(tcg_ctx, tcg_ctx->cpu_env);
+            gen_helper_sti(tcg_ctx, cpu_env);
             /* interruptions are enabled only the first insn after sti */
             gen_jmp_im(s, s->pc - s->cs_base);
             gen_eob_inhibit_irq(s, true);
@@ -8418,16 +8449,16 @@ case 0x101:
                 } else {
                     gen_lea_modrm(env, s, modrm);
                     if (CODE64(s)) {
-                        tcg_gen_qemu_ld_i64(s->uc, tcg_ctx->cpu_bndl[reg], cpu_A0,
+                        tcg_gen_qemu_ld_i64(uc, tcg_ctx->cpu_bndl[reg], cpu_A0,
                                             s->mem_index, MO_LEQ);
                         tcg_gen_addi_tl(tcg_ctx, cpu_A0, cpu_A0, 8);
-                        tcg_gen_qemu_ld_i64(s->uc, tcg_ctx->cpu_bndu[reg], cpu_A0,
+                        tcg_gen_qemu_ld_i64(uc, tcg_ctx->cpu_bndu[reg], cpu_A0,
                                             s->mem_index, MO_LEQ);
                     } else {
-                        tcg_gen_qemu_ld_i64(s->uc, tcg_ctx->cpu_bndl[reg], cpu_A0,
+                        tcg_gen_qemu_ld_i64(uc, tcg_ctx->cpu_bndl[reg], cpu_A0,
                                             s->mem_index, MO_LEUL);
                         tcg_gen_addi_tl(tcg_ctx, cpu_A0, cpu_A0, 4);
-                        tcg_gen_qemu_ld_i64(s->uc, tcg_ctx->cpu_bndu[reg], cpu_A0,
+                        tcg_gen_qemu_ld_i64(uc, tcg_ctx->cpu_bndu[reg], cpu_A0,
                                             s->mem_index, MO_LEUL);
                     }
                     /* bnd registers are now in-use */
@@ -8525,16 +8556,16 @@ case 0x101:
                 } else {
                     gen_lea_modrm(env, s, modrm);
                     if (CODE64(s)) {
-                        tcg_gen_qemu_st_i64(s->uc, tcg_ctx->cpu_bndl[reg], cpu_A0,
+                        tcg_gen_qemu_st_i64(uc, tcg_ctx->cpu_bndl[reg], cpu_A0,
                                             s->mem_index, MO_LEQ);
                         tcg_gen_addi_tl(tcg_ctx, cpu_A0, cpu_A0, 8);
-                        tcg_gen_qemu_st_i64(s->uc, tcg_ctx->cpu_bndu[reg], cpu_A0,
+                        tcg_gen_qemu_st_i64(uc, tcg_ctx->cpu_bndu[reg], cpu_A0,
                                             s->mem_index, MO_LEQ);
                     } else {
-                        tcg_gen_qemu_st_i64(s->uc, tcg_ctx->cpu_bndl[reg], cpu_A0,
+                        tcg_gen_qemu_st_i64(uc, tcg_ctx->cpu_bndl[reg], cpu_A0,
                                             s->mem_index, MO_LEUL);
                         tcg_gen_addi_tl(tcg_ctx, cpu_A0, cpu_A0, 4);
-                        tcg_gen_qemu_st_i64(s->uc, tcg_ctx->cpu_bndu[reg], cpu_A0,
+                        tcg_gen_qemu_st_i64(uc, tcg_ctx->cpu_bndu[reg], cpu_A0,
                                             s->mem_index, MO_LEUL);
                     }
                 }
@@ -8666,13 +8697,13 @@ case 0x101:
                 gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_DR0 + reg);
                 gen_op_mov_v_reg(tcg_ctx, ot, cpu_T0, rm);
                 tcg_gen_movi_i32(tcg_ctx, cpu_tmp2_i32, reg);
-                gen_helper_set_dr(tcg_ctx, tcg_ctx->cpu_env, cpu_tmp2_i32, cpu_T0);
+                gen_helper_set_dr(tcg_ctx, cpu_env, cpu_tmp2_i32, cpu_T0);
                 gen_jmp_im(s, s->pc - s->cs_base);
                 gen_eob(s);
             } else {
                 gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_DR0 + reg);
                 tcg_gen_movi_i32(tcg_ctx, cpu_tmp2_i32, reg);
-                gen_helper_get_dr(tcg_ctx, cpu_T0, tcg_ctx->cpu_env, cpu_tmp2_i32);
+                gen_helper_get_dr(tcg_ctx, cpu_T0, cpu_env, cpu_tmp2_i32);
                 gen_op_mov_reg_v(tcg_ctx, ot, rm, cpu_T0);
             }
         }
@@ -8739,7 +8770,7 @@ case 0x101:
                 break;
             }
             gen_lea_modrm(env, s, modrm);
-            tcg_gen_qemu_ld_i32(s->uc, cpu_tmp2_i32, cpu_A0, s->mem_index, MO_LEUL);
+            tcg_gen_qemu_ld_i32(uc, cpu_tmp2_i32, cpu_A0, s->mem_index, MO_LEUL);
             gen_helper_ldmxcsr(tcg_ctx, cpu_env, cpu_tmp2_i32);
             break;
 
@@ -9099,41 +9130,38 @@ void tcg_x86_init(struct uc_struct *uc)
     int i;
     TCGContext *tcg_ctx = uc->tcg_ctx;
 
-    tcg_ctx->cpu_env = tcg_global_reg_new_ptr(uc->tcg_ctx, TCG_AREG0, "env");
-    tcg_ctx->tcg_env = tcg_ctx->cpu_env;
-
-    tcg_ctx->cpu_cc_op = tcg_global_mem_new_i32(uc->tcg_ctx, tcg_ctx->cpu_env,
+    tcg_ctx->cpu_cc_op = tcg_global_mem_new_i32(uc->tcg_ctx, uc->cpu_env,
                                        offsetof(CPUX86State, cc_op), "cc_op");
 
-    tcg_ctx->cpu_cc_dst = tcg_global_mem_new(uc->tcg_ctx, tcg_ctx->cpu_env,
+    tcg_ctx->cpu_cc_dst = tcg_global_mem_new(uc->tcg_ctx, uc->cpu_env,
                                              offsetof(CPUX86State, cc_dst), "cc_dst");
 
-    tcg_ctx->cpu_cc_src = tcg_global_mem_new(uc->tcg_ctx, tcg_ctx->cpu_env,
+    tcg_ctx->cpu_cc_src = tcg_global_mem_new(uc->tcg_ctx, uc->cpu_env,
                                              offsetof(CPUX86State, cc_src), "cc_src");
 
-    tcg_ctx->cpu_cc_src2 = tcg_global_mem_new(uc->tcg_ctx, tcg_ctx->cpu_env,
+    tcg_ctx->cpu_cc_src2 = tcg_global_mem_new(uc->tcg_ctx, uc->cpu_env,
                                               offsetof(CPUX86State, cc_src2), "cc_src2");
 
     for (i = 0; i < CPU_NB_REGS; ++i) {
-        tcg_ctx->cpu_regs[i] = tcg_global_mem_new(uc->tcg_ctx, tcg_ctx->cpu_env,
+        tcg_ctx->cpu_regs[i] = tcg_global_mem_new(uc->tcg_ctx, uc->cpu_env,
                 offsetof(CPUX86State, regs[i]),
                 reg_names[i]);
     }
 
     for (i = 0; i < 6; ++i) {
         tcg_ctx->cpu_seg_base[i]
-            = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env,
+            = tcg_global_mem_new(tcg_ctx, uc->cpu_env,
                                  offsetof(CPUX86State, segs[i].base),
                                  seg_base_names[i]);
     }
 
     for (i = 0; i < 4; ++i) {
         tcg_ctx->cpu_bndl[i]
-            = tcg_global_mem_new_i64(tcg_ctx, tcg_ctx->cpu_env,
+            = tcg_global_mem_new_i64(tcg_ctx, uc->cpu_env,
                                      offsetof(CPUX86State, bnd_regs[i].lb),
                                      bnd_regl_names[i]);
         tcg_ctx->cpu_bndu[i]
-            = tcg_global_mem_new_i64(tcg_ctx, tcg_ctx->cpu_env,
+            = tcg_global_mem_new_i64(tcg_ctx, uc->cpu_env,
                                      offsetof(CPUX86State, bnd_regs[i].ub),
                                      bnd_regu_names[i]);
     }
diff --git a/qemu/target/m68k/translate.c b/qemu/target/m68k/translate.c
index 4d5943b9..a590694b 100644
--- a/qemu/target/m68k/translate.c
+++ b/qemu/target/m68k/translate.c
@@ -48,18 +48,13 @@ void m68k_tcg_init(struct uc_struct *uc)
     char *p;
     int i;
 
-    tcg_ctx->cpu_env = tcg_global_reg_new_ptr(tcg_ctx, TCG_AREG0, "env");
-    tcg_ctx->tcg_env = tcg_ctx->cpu_env;
-
-#define DEFO32(name,  offset) tcg_ctx->QREG_##name = tcg_global_mem_new_i32(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPUM68KState, offset), #name);
-#define DEFO64(name,  offset) tcg_ctx->QREG_##name = tcg_global_mem_new_i64(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPUM68KState, offset), #name);
+#define DEFO32(name,  offset) tcg_ctx->QREG_##name = tcg_global_mem_new_i32(tcg_ctx, tcg_ctx->uc->cpu_env, offsetof(CPUM68KState, offset), #name);
+#define DEFO64(name,  offset) tcg_ctx->QREG_##name = tcg_global_mem_new_i64(tcg_ctx, tcg_ctx->uc->cpu_env, offsetof(CPUM68KState, offset), #name);
 #include "qregs.def"
 #undef DEFO32
 #undef DEFO64
 
-    // tcg_ctx->QREG_FP_RESULT = tcg_global_mem_new_i64(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPUM68KState, fp_result), "FP_RESULT");
-
-    tcg_ctx->cpu_halted = tcg_global_mem_new_i32(tcg_ctx, tcg_ctx->cpu_env,
+    tcg_ctx->cpu_halted = tcg_global_mem_new_i32(tcg_ctx, uc->cpu_env,
                                         0-offsetof(M68kCPU, env) +
                                         offsetof(CPUState, halted), "HALTED");
 
@@ -67,24 +62,24 @@ void m68k_tcg_init(struct uc_struct *uc)
 
     for (i = 0; i < 8; i++) {
         sprintf(p, "D%d", i);
-        tcg_ctx->cpu_dregs[i] = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env,
+        tcg_ctx->cpu_dregs[i] = tcg_global_mem_new(tcg_ctx, uc->cpu_env,
                 offsetof(CPUM68KState, dregs[i]), p);
         p += 3;
         sprintf(p, "A%d", i);
-        tcg_ctx->cpu_aregs[i] = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env,
+        tcg_ctx->cpu_aregs[i] = tcg_global_mem_new(tcg_ctx, uc->cpu_env,
                 offsetof(CPUM68KState, aregs[i]), p);
         p += 3;
     }
 
     for (i = 0; i < 4; i++) {
         sprintf(p, "ACC%d", i);
-        tcg_ctx->cpu_macc[i] = tcg_global_mem_new_i64(tcg_ctx, tcg_ctx->cpu_env,
+        tcg_ctx->cpu_macc[i] = tcg_global_mem_new_i64(tcg_ctx, uc->cpu_env,
                                          offsetof(CPUM68KState, macc[i]), p);
         p += 5;
     }
 
-    tcg_ctx->NULL_QREG = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env, -4, "NULL");
-    tcg_ctx->store_dummy = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env, -8, "NULL");
+    tcg_ctx->NULL_QREG = tcg_global_mem_new(tcg_ctx, uc->cpu_env, -4, "NULL");
+    tcg_ctx->store_dummy = tcg_global_mem_new(tcg_ctx, uc->cpu_env, -8, "NULL");
 
     uc->init_tcg = true;
 }
@@ -269,10 +264,11 @@ static void gen_jmp(DisasContext *s, TCGv dest)
 
 static void gen_raise_exception(DisasContext *s, int nr)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv_i32 tmp = tcg_const_i32(tcg_ctx, nr);
 
-    gen_helper_raise_exception(tcg_ctx, tcg_ctx->cpu_env, tmp);
+    gen_helper_raise_exception(tcg_ctx, uc->cpu_env, tmp);
     tcg_temp_free_i32(tcg_ctx, tmp);
 }
 
@@ -611,13 +607,13 @@ static void gen_flush_flags(DisasContext *s)
         break;
 
     case CC_OP_DYNAMIC:
-        gen_helper_flush_flags(tcg_ctx, tcg_ctx->cpu_env, tcg_ctx->QREG_CC_OP);
+        gen_helper_flush_flags(tcg_ctx, s->uc->cpu_env, tcg_ctx->QREG_CC_OP);
         s->cc_op_synced = 1;
         break;
 
     default:
         t0 = tcg_const_i32(tcg_ctx, s->cc_op);
-        gen_helper_flush_flags(tcg_ctx, tcg_ctx->cpu_env, t0);
+        gen_helper_flush_flags(tcg_ctx, s->uc->cpu_env, t0);
         tcg_temp_free(tcg_ctx, t0);
         s->cc_op_synced = 1;
         break;
@@ -940,19 +936,21 @@ static TCGv gen_ea(CPUM68KState *env, DisasContext *s, uint16_t insn,
 
 static TCGv_ptr gen_fp_ptr(DisasContext *s, int freg)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv_ptr fp = tcg_temp_new_ptr(tcg_ctx);
 
-    tcg_gen_addi_ptr(tcg_ctx, fp, tcg_ctx->cpu_env, offsetof(CPUM68KState, fregs[freg]));
+    tcg_gen_addi_ptr(tcg_ctx, fp, uc->cpu_env, offsetof(CPUM68KState, fregs[freg]));
     return fp;
 }
 
 static TCGv_ptr gen_fp_result_ptr(DisasContext *s)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv_ptr fp = tcg_temp_new_ptr(tcg_ctx);
 
-    tcg_gen_addi_ptr(tcg_ctx, fp, tcg_ctx->cpu_env, offsetof(CPUM68KState, fp_result));
+    tcg_gen_addi_ptr(tcg_ctx, fp, uc->cpu_env, offsetof(CPUM68KState, fp_result));
     return fp;
 }
 
@@ -976,7 +974,8 @@ static void gen_fp_move(DisasContext *s, TCGv_ptr dest, TCGv_ptr src)
 static void gen_load_fp(DisasContext *s, int opsize, TCGv addr, TCGv_ptr fp,
                         int index)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv tmp;
     TCGv_i64 t64;
 
@@ -985,23 +984,23 @@ static void gen_load_fp(DisasContext *s, int opsize, TCGv addr, TCGv_ptr fp,
     switch (opsize) {
     case OS_BYTE:
         tcg_gen_qemu_ld8s(s->uc, tmp, addr, index);
-        gen_helper_exts32(tcg_ctx, tcg_ctx->cpu_env, fp, tmp);
+        gen_helper_exts32(tcg_ctx, uc->cpu_env, fp, tmp);
         break;
     case OS_WORD:
         tcg_gen_qemu_ld16s(s->uc, tmp, addr, index);
-        gen_helper_exts32(tcg_ctx, tcg_ctx->cpu_env, fp, tmp);
+        gen_helper_exts32(tcg_ctx, uc->cpu_env, fp, tmp);
         break;
     case OS_LONG:
         tcg_gen_qemu_ld32u(s->uc, tmp, addr, index);
-        gen_helper_exts32(tcg_ctx, tcg_ctx->cpu_env, fp, tmp);
+        gen_helper_exts32(tcg_ctx, uc->cpu_env, fp, tmp);
         break;
     case OS_SINGLE:
         tcg_gen_qemu_ld32u(s->uc, tmp, addr, index);
-        gen_helper_extf32(tcg_ctx, tcg_ctx->cpu_env, fp, tmp);
+        gen_helper_extf32(tcg_ctx, uc->cpu_env, fp, tmp);
         break;
     case OS_DOUBLE:
         tcg_gen_qemu_ld64(s->uc, t64, addr, index);
-        gen_helper_extf64(tcg_ctx, tcg_ctx->cpu_env, fp, t64);
+        gen_helper_extf64(tcg_ctx, uc->cpu_env, fp, t64);
         break;
     case OS_EXTENDED:
         if (m68k_feature(s->env, M68K_FEATURE_CF_FPU)) {
@@ -1031,7 +1030,8 @@ static void gen_load_fp(DisasContext *s, int opsize, TCGv addr, TCGv_ptr fp,
 static void gen_store_fp(DisasContext *s, int opsize, TCGv addr, TCGv_ptr fp,
                          int index)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv tmp;
     TCGv_i64 t64;
 
@@ -1039,23 +1039,23 @@ static void gen_store_fp(DisasContext *s, int opsize, TCGv addr, TCGv_ptr fp,
     tmp = tcg_temp_new(tcg_ctx);
     switch (opsize) {
     case OS_BYTE:
-        gen_helper_reds32(tcg_ctx, tmp, tcg_ctx->cpu_env, fp);
+        gen_helper_reds32(tcg_ctx, tmp, uc->cpu_env, fp);
         tcg_gen_qemu_st8(s->uc, tmp, addr, index);
         break;
     case OS_WORD:
-        gen_helper_reds32(tcg_ctx, tmp, tcg_ctx->cpu_env, fp);
+        gen_helper_reds32(tcg_ctx, tmp, uc->cpu_env, fp);
         tcg_gen_qemu_st16(s->uc, tmp, addr, index);
         break;
     case OS_LONG:
-        gen_helper_reds32(tcg_ctx, tmp, tcg_ctx->cpu_env, fp);
+        gen_helper_reds32(tcg_ctx, tmp, uc->cpu_env, fp);
         tcg_gen_qemu_st32(s->uc, tmp, addr, index);
         break;
     case OS_SINGLE:
-        gen_helper_redf32(tcg_ctx, tmp, tcg_ctx->cpu_env, fp);
+        gen_helper_redf32(tcg_ctx, tmp, uc->cpu_env, fp);
         tcg_gen_qemu_st32(s->uc, tmp, addr, index);
         break;
     case OS_DOUBLE:
-        gen_helper_redf64(tcg_ctx, t64, tcg_ctx->cpu_env, fp);
+        gen_helper_redf64(tcg_ctx, t64, uc->cpu_env, fp);
         tcg_gen_qemu_st64(s->uc, t64, addr, index);
         break;
     case OS_EXTENDED:
@@ -1097,7 +1097,8 @@ static int gen_ea_mode_fp(CPUM68KState *env, DisasContext *s, int mode,
                           int reg0, int opsize, TCGv_ptr fp, ea_what what,
                           int index)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv reg, addr, tmp;
     TCGv_i64 t64;
 
@@ -1109,10 +1110,10 @@ static int gen_ea_mode_fp(CPUM68KState *env, DisasContext *s, int mode,
             case OS_BYTE:
             case OS_WORD:
             case OS_LONG:
-                gen_helper_reds32(tcg_ctx, reg, tcg_ctx->cpu_env, fp);
+                gen_helper_reds32(tcg_ctx, reg, uc->cpu_env, fp);
                 break;
             case OS_SINGLE:
-                gen_helper_redf32(tcg_ctx, reg, tcg_ctx->cpu_env, fp);
+                gen_helper_redf32(tcg_ctx, reg, uc->cpu_env, fp);
                 break;
             default:
                 g_assert_not_reached();
@@ -1122,17 +1123,17 @@ static int gen_ea_mode_fp(CPUM68KState *env, DisasContext *s, int mode,
             switch (opsize) {
             case OS_BYTE:
                 tcg_gen_ext8s_i32(tcg_ctx, tmp, reg);
-                gen_helper_exts32(tcg_ctx, tcg_ctx->cpu_env, fp, tmp);
+                gen_helper_exts32(tcg_ctx, uc->cpu_env, fp, tmp);
                 break;
             case OS_WORD:
                 tcg_gen_ext16s_i32(tcg_ctx, tmp, reg);
-                gen_helper_exts32(tcg_ctx, tcg_ctx->cpu_env, fp, tmp);
+                gen_helper_exts32(tcg_ctx, uc->cpu_env, fp, tmp);
                 break;
             case OS_LONG:
-                gen_helper_exts32(tcg_ctx, tcg_ctx->cpu_env, fp, reg);
+                gen_helper_exts32(tcg_ctx, uc->cpu_env, fp, reg);
                 break;
             case OS_SINGLE:
-                gen_helper_extf32(tcg_ctx, tcg_ctx->cpu_env, fp, reg);
+                gen_helper_extf32(tcg_ctx, uc->cpu_env, fp, reg);
                 break;
             default:
                 g_assert_not_reached();
@@ -1182,27 +1183,27 @@ static int gen_ea_mode_fp(CPUM68KState *env, DisasContext *s, int mode,
             switch (opsize) {
             case OS_BYTE:
                 tmp = tcg_const_i32(tcg_ctx, (int8_t)read_im8(env, s));
-                gen_helper_exts32(tcg_ctx, tcg_ctx->cpu_env, fp, tmp);
+                gen_helper_exts32(tcg_ctx, uc->cpu_env, fp, tmp);
                 tcg_temp_free(tcg_ctx, tmp);
                 break;
             case OS_WORD:
                 tmp = tcg_const_i32(tcg_ctx, (int16_t)read_im16(env, s));
-                gen_helper_exts32(tcg_ctx, tcg_ctx->cpu_env, fp, tmp);
+                gen_helper_exts32(tcg_ctx, uc->cpu_env, fp, tmp);
                 tcg_temp_free(tcg_ctx, tmp);
                 break;
             case OS_LONG:
                 tmp = tcg_const_i32(tcg_ctx, read_im32(env, s));
-                gen_helper_exts32(tcg_ctx, tcg_ctx->cpu_env, fp, tmp);
+                gen_helper_exts32(tcg_ctx, uc->cpu_env, fp, tmp);
                 tcg_temp_free(tcg_ctx, tmp);
                 break;
             case OS_SINGLE:
                 tmp = tcg_const_i32(tcg_ctx, read_im32(env, s));
-                gen_helper_extf32(tcg_ctx, tcg_ctx->cpu_env, fp, tmp);
+                gen_helper_extf32(tcg_ctx, uc->cpu_env, fp, tmp);
                 tcg_temp_free(tcg_ctx, tmp);
                 break;
             case OS_DOUBLE:
                 t64 = tcg_const_i64(tcg_ctx, read_im64(env, s));
-                gen_helper_extf64(tcg_ctx, tcg_ctx->cpu_env, fp, t64);
+                gen_helper_extf64(tcg_ctx, uc->cpu_env, fp, t64);
                 tcg_temp_free_i64(tcg_ctx, t64);
                 break;
             case OS_EXTENDED:
@@ -1597,7 +1598,8 @@ DISAS_INSN(mulw)
 
 DISAS_INSN(divw)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     int sign;
     TCGv src;
     TCGv destr;
@@ -1611,9 +1613,9 @@ DISAS_INSN(divw)
     SRC_EA(env, src, OS_WORD, sign, NULL);
     destr = tcg_const_i32(tcg_ctx, REG(insn, 9));
     if (sign) {
-        gen_helper_divsw(tcg_ctx, tcg_ctx->cpu_env, destr, src);
+        gen_helper_divsw(tcg_ctx, uc->cpu_env, destr, src);
     } else {
-        gen_helper_divuw(tcg_ctx, tcg_ctx->cpu_env, destr, src);
+        gen_helper_divuw(tcg_ctx, uc->cpu_env, destr, src);
     }
     tcg_temp_free(tcg_ctx, destr);
 
@@ -1622,7 +1624,8 @@ DISAS_INSN(divw)
 
 DISAS_INSN(divl)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv num, reg, den;
     int sign;
     uint16_t ext;
@@ -1643,9 +1646,9 @@ DISAS_INSN(divl)
         num = tcg_const_i32(tcg_ctx, REG(ext, 12));
         reg = tcg_const_i32(tcg_ctx, REG(ext, 0));
         if (sign) {
-            gen_helper_divsll(tcg_ctx, tcg_ctx->cpu_env, num, reg, den);
+            gen_helper_divsll(tcg_ctx, uc->cpu_env, num, reg, den);
         } else {
-            gen_helper_divull(tcg_ctx, tcg_ctx->cpu_env, num, reg, den);
+            gen_helper_divull(tcg_ctx, uc->cpu_env, num, reg, den);
         }
         tcg_temp_free(tcg_ctx, reg);
         tcg_temp_free(tcg_ctx, num);
@@ -1660,9 +1663,9 @@ DISAS_INSN(divl)
     num = tcg_const_i32(tcg_ctx, REG(ext, 12));
     reg = tcg_const_i32(tcg_ctx, REG(ext, 0));
     if (sign) {
-        gen_helper_divsl(tcg_ctx, tcg_ctx->cpu_env, num, reg, den);
+        gen_helper_divsl(tcg_ctx, uc->cpu_env, num, reg, den);
     } else {
-        gen_helper_divul(tcg_ctx, tcg_ctx->cpu_env, num, reg, den);
+        gen_helper_divul(tcg_ctx, uc->cpu_env, num, reg, den);
     }
     tcg_temp_free(tcg_ctx, reg);
     tcg_temp_free(tcg_ctx, num);
@@ -2251,12 +2254,13 @@ DISAS_INSN(bitop_im)
 
 static TCGv gen_get_ccr(DisasContext *s)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv dest;
 
     update_cc_op(s);
     dest = tcg_temp_new(tcg_ctx);
-    gen_helper_get_ccr(tcg_ctx, dest, tcg_ctx->cpu_env);
+    gen_helper_get_ccr(tcg_ctx, dest, uc->cpu_env);
     return dest;
 }
 
@@ -2275,7 +2279,9 @@ static TCGv gen_get_sr(DisasContext *s)
 
 static void gen_set_sr_im(DisasContext *s, uint16_t val, int ccr_only)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
+
     if (ccr_only) {
         tcg_gen_movi_i32(tcg_ctx, tcg_ctx->QREG_CC_C, val & CCF_C ? 1 : 0);
         tcg_gen_movi_i32(tcg_ctx, tcg_ctx->QREG_CC_V, val & CCF_V ? -1 : 0);
@@ -2284,7 +2290,7 @@ static void gen_set_sr_im(DisasContext *s, uint16_t val, int ccr_only)
         tcg_gen_movi_i32(tcg_ctx, tcg_ctx->QREG_CC_X, val & CCF_X ? 1 : 0);
     } else {
         TCGv sr = tcg_const_i32(tcg_ctx, val);
-        gen_helper_set_sr(tcg_ctx, tcg_ctx->cpu_env, sr);
+        gen_helper_set_sr(tcg_ctx, uc->cpu_env, sr);
         tcg_temp_free(tcg_ctx, sr);
     }
     set_cc_op(s, CC_OP_FLAGS);
@@ -2292,12 +2298,13 @@ static void gen_set_sr_im(DisasContext *s, uint16_t val, int ccr_only)
 
 static void gen_set_sr(DisasContext *s, TCGv val, int ccr_only)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
 
     if (ccr_only) {
-        gen_helper_set_ccr(tcg_ctx, tcg_ctx->cpu_env, val);
+        gen_helper_set_ccr(tcg_ctx, uc->cpu_env, val);
     } else {
-        gen_helper_set_sr(tcg_ctx, tcg_ctx->cpu_env, val);
+        gen_helper_set_sr(tcg_ctx, uc->cpu_env, val);
     }
     set_cc_op(s, CC_OP_FLAGS);
 }
@@ -2489,7 +2496,8 @@ DISAS_INSN(cas)
 
 DISAS_INSN(cas2w)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     uint16_t ext1, ext2;
     TCGv addr1, addr2;
     TCGv regs;
@@ -2528,9 +2536,9 @@ DISAS_INSN(cas2w)
                          (REG(ext2, 0) << 6) |
                          (REG(ext1, 0) << 9));
     if (tb_cflags(s->tb) & CF_PARALLEL) {
-        gen_helper_exit_atomic(tcg_ctx, tcg_ctx->cpu_env);
+        gen_helper_exit_atomic(tcg_ctx, uc->cpu_env);
     } else {
-        gen_helper_cas2w(tcg_ctx, tcg_ctx->cpu_env, regs, addr1, addr2);
+        gen_helper_cas2w(tcg_ctx, uc->cpu_env, regs, addr1, addr2);
     }
     tcg_temp_free(tcg_ctx, regs);
 
@@ -2541,7 +2549,8 @@ DISAS_INSN(cas2w)
 
 DISAS_INSN(cas2l)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     uint16_t ext1, ext2;
     TCGv addr1, addr2, regs;
 
@@ -2579,9 +2588,9 @@ DISAS_INSN(cas2l)
                          (REG(ext2, 0) << 6) |
                          (REG(ext1, 0) << 9));
     if (tb_cflags(s->tb) & CF_PARALLEL) {
-        gen_helper_cas2l_parallel(tcg_ctx, tcg_ctx->cpu_env, regs, addr1, addr2);
+        gen_helper_cas2l_parallel(tcg_ctx, uc->cpu_env, regs, addr1, addr2);
     } else {
-        gen_helper_cas2l(tcg_ctx, tcg_ctx->cpu_env, regs, addr1, addr2);
+        gen_helper_cas2l(tcg_ctx, uc->cpu_env, regs, addr1, addr2);
     }
     tcg_temp_free(tcg_ctx, regs);
 
@@ -2978,14 +2987,15 @@ DISAS_INSN(unlk)
 #if defined(CONFIG_SOFTMMU)
 DISAS_INSN(reset)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
 
     if (IS_USER(s)) {
         gen_exception(s, s->insn_pc, EXCP_PRIVILEGE);
         return;
     }
 
-    gen_helper_reset(tcg_ctx, tcg_ctx->cpu_env);
+    gen_helper_reset(tcg_ctx, uc->cpu_env);
 }
 #endif
 
@@ -4205,7 +4215,8 @@ DISAS_INSN(bfext_reg)
 
 DISAS_INSN(bfext_mem)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     int ext = read_im16(env, s);
     int is_sign = insn & 0x200;
     TCGv dest = DREG(ext, 12);
@@ -4229,11 +4240,11 @@ DISAS_INSN(bfext_mem)
     }
 
     if (is_sign) {
-        gen_helper_bfexts_mem(tcg_ctx, dest, tcg_ctx->cpu_env, addr, ofs, len);
+        gen_helper_bfexts_mem(tcg_ctx, dest, uc->cpu_env, addr, ofs, len);
         tcg_gen_mov_i32(tcg_ctx, tcg_ctx->QREG_CC_N, dest);
     } else {
         TCGv_i64 tmp = tcg_temp_new_i64(tcg_ctx);
-        gen_helper_bfextu_mem(tcg_ctx, tmp, tcg_ctx->cpu_env, addr, ofs, len);
+        gen_helper_bfextu_mem(tcg_ctx, tmp, uc->cpu_env, addr, ofs, len);
         tcg_gen_extr_i64_i32(tcg_ctx, dest, tcg_ctx->QREG_CC_N, tmp);
         tcg_temp_free_i64(tcg_ctx, tmp);
     }
@@ -4343,7 +4354,8 @@ DISAS_INSN(bfop_reg)
 
 DISAS_INSN(bfop_mem)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     int ext = read_im16(env, s);
     TCGv addr, len, ofs;
     TCGv_i64 t64;
@@ -4367,22 +4379,22 @@ DISAS_INSN(bfop_mem)
 
     switch (insn & 0x0f00) {
     case 0x0a00: /* bfchg */
-        gen_helper_bfchg_mem(tcg_ctx, tcg_ctx->QREG_CC_N, tcg_ctx->cpu_env, addr, ofs, len);
+        gen_helper_bfchg_mem(tcg_ctx, tcg_ctx->QREG_CC_N, uc->cpu_env, addr, ofs, len);
         break;
     case 0x0c00: /* bfclr */
-        gen_helper_bfclr_mem(tcg_ctx, tcg_ctx->QREG_CC_N, tcg_ctx->cpu_env, addr, ofs, len);
+        gen_helper_bfclr_mem(tcg_ctx, tcg_ctx->QREG_CC_N, uc->cpu_env, addr, ofs, len);
         break;
     case 0x0d00: /* bfffo */
         t64 = tcg_temp_new_i64(tcg_ctx);
-        gen_helper_bfffo_mem(tcg_ctx, t64, tcg_ctx->cpu_env, addr, ofs, len);
+        gen_helper_bfffo_mem(tcg_ctx, t64, uc->cpu_env, addr, ofs, len);
         tcg_gen_extr_i64_i32(tcg_ctx, DREG(ext, 12), tcg_ctx->QREG_CC_N, t64);
         tcg_temp_free_i64(tcg_ctx, t64);
         break;
     case 0x0e00: /* bfset */
-        gen_helper_bfset_mem(tcg_ctx, tcg_ctx->QREG_CC_N, tcg_ctx->cpu_env, addr, ofs, len);
+        gen_helper_bfset_mem(tcg_ctx, tcg_ctx->QREG_CC_N, uc->cpu_env, addr, ofs, len);
         break;
     case 0x0800: /* bftst */
-        gen_helper_bfexts_mem(tcg_ctx, tcg_ctx->QREG_CC_N, tcg_ctx->cpu_env, addr, ofs, len);
+        gen_helper_bfexts_mem(tcg_ctx, tcg_ctx->QREG_CC_N, uc->cpu_env, addr, ofs, len);
         break;
     default:
         g_assert_not_reached();
@@ -4474,7 +4486,8 @@ DISAS_INSN(bfins_reg)
 
 DISAS_INSN(bfins_mem)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     int ext = read_im16(env, s);
     TCGv src = DREG(ext, 12);
     TCGv addr, len, ofs;
@@ -4496,7 +4509,7 @@ DISAS_INSN(bfins_mem)
         ofs = tcg_const_i32(tcg_ctx, extract32(ext, 6, 5));
     }
 
-    gen_helper_bfins_mem(tcg_ctx, tcg_ctx->QREG_CC_N, tcg_ctx->cpu_env, addr, src, ofs, len);
+    gen_helper_bfins_mem(tcg_ctx, tcg_ctx->QREG_CC_N, uc->cpu_env, addr, src, ofs, len);
     set_cc_op(s, CC_OP_LOGIC);
 
     if (!(ext & 0x20)) {
@@ -4518,7 +4531,8 @@ DISAS_INSN(ff1)
 
 DISAS_INSN(chk)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv src, reg;
     int opsize;
 
@@ -4540,12 +4554,13 @@ DISAS_INSN(chk)
     reg = gen_extend(s, DREG(insn, 9), opsize, 1);
 
     gen_flush_flags(s);
-    gen_helper_chk(tcg_ctx, tcg_ctx->cpu_env, reg, src);
+    gen_helper_chk(tcg_ctx, uc->cpu_env, reg, src);
 }
 
 DISAS_INSN(chk2)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     uint16_t ext;
     TCGv addr1, addr2, bound1, bound2, reg;
     int opsize;
@@ -4588,7 +4603,7 @@ DISAS_INSN(chk2)
     }
 
     gen_flush_flags(s);
-    gen_helper_chk2(tcg_ctx, tcg_ctx->cpu_env, reg, bound1, bound2);
+    gen_helper_chk2(tcg_ctx, uc->cpu_env, reg, bound1, bound2);
     tcg_temp_free(tcg_ctx, reg);
     tcg_temp_free(tcg_ctx, bound1);
     tcg_temp_free(tcg_ctx, bound2);
@@ -4773,27 +4788,29 @@ DISAS_INSN(move_to_sr)
 
 DISAS_INSN(move_from_usp)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
 
     if (IS_USER(s)) {
         gen_exception(s, s->insn_pc, EXCP_PRIVILEGE);
         return;
     }
 
-    tcg_gen_ld_i32(tcg_ctx, AREG(insn, 0), tcg_ctx->cpu_env,
+    tcg_gen_ld_i32(tcg_ctx, AREG(insn, 0), uc->cpu_env,
                    offsetof(CPUM68KState, sp[M68K_USP]));
 }
 
 DISAS_INSN(move_to_usp)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
 
     if (IS_USER(s)) {
         gen_exception(s, s->insn_pc, EXCP_PRIVILEGE);
         return;
     }
 
-    tcg_gen_st_i32(tcg_ctx, AREG(insn, 0), tcg_ctx->cpu_env,
+    tcg_gen_st_i32(tcg_ctx, AREG(insn, 0), uc->cpu_env,
                    offsetof(CPUM68KState, sp[M68K_USP]));
 }
 
@@ -4835,7 +4852,8 @@ DISAS_INSN(rte)
 
 DISAS_INSN(cf_movec)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     uint16_t ext;
     TCGv reg;
 
@@ -4851,13 +4869,14 @@ DISAS_INSN(cf_movec)
     } else {
         reg = DREG(ext, 12);
     }
-    gen_helper_cf_movec_to(tcg_ctx, tcg_ctx->cpu_env, tcg_const_i32(tcg_ctx, ext & 0xfff), reg);
+    gen_helper_cf_movec_to(tcg_ctx, uc->cpu_env, tcg_const_i32(tcg_ctx, ext & 0xfff), reg);
     gen_lookup_tb(s);
 }
 
 DISAS_INSN(m68k_movec)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     uint16_t ext;
     TCGv reg;
 
@@ -4874,9 +4893,9 @@ DISAS_INSN(m68k_movec)
         reg = DREG(ext, 12);
     }
     if (insn & 1) {
-        gen_helper_m68k_movec_to(tcg_ctx, tcg_ctx->cpu_env, tcg_const_i32(tcg_ctx, ext & 0xfff), reg);
+        gen_helper_m68k_movec_to(tcg_ctx, uc->cpu_env, tcg_const_i32(tcg_ctx, ext & 0xfff), reg);
     } else {
-        gen_helper_m68k_movec_from(tcg_ctx, reg, tcg_ctx->cpu_env, tcg_const_i32(tcg_ctx, ext & 0xfff));
+        gen_helper_m68k_movec_from(tcg_ctx, reg, uc->cpu_env, tcg_const_i32(tcg_ctx, ext & 0xfff));
     }
     gen_lookup_tb(s);
 }
@@ -4920,7 +4939,8 @@ DISAS_INSN(cinv)
 #if defined(CONFIG_SOFTMMU)
 DISAS_INSN(pflush)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv opmode;
 
     if (IS_USER(s)) {
@@ -4929,13 +4949,14 @@ DISAS_INSN(pflush)
     }
 
     opmode = tcg_const_i32(tcg_ctx, (insn >> 3) & 3);
-    gen_helper_pflush(tcg_ctx, tcg_ctx->cpu_env, AREG(insn, 0), opmode);
+    gen_helper_pflush(tcg_ctx, uc->cpu_env, AREG(insn, 0), opmode);
     tcg_temp_free(tcg_ctx, opmode);
 }
 
 DISAS_INSN(ptest)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv is_read;
 
     if (IS_USER(s)) {
@@ -4943,7 +4964,7 @@ DISAS_INSN(ptest)
         return;
     }
     is_read = tcg_const_i32(tcg_ctx, (insn >> 5) & 1);
-    gen_helper_ptest(tcg_ctx, tcg_ctx->cpu_env, AREG(insn, 0), is_read);
+    gen_helper_ptest(tcg_ctx, uc->cpu_env, AREG(insn, 0), is_read);
     tcg_temp_free(tcg_ctx, is_read);
 }
 #endif
@@ -4973,33 +4994,35 @@ DISAS_INSN(trap)
 
 static void gen_load_fcr(DisasContext *s, TCGv res, int reg)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
 
     switch (reg) {
     case M68K_FPIAR:
         tcg_gen_movi_i32(tcg_ctx, res, 0);
         break;
     case M68K_FPSR:
-        tcg_gen_ld_i32(tcg_ctx, res, tcg_ctx->cpu_env, offsetof(CPUM68KState, fpsr));
+        tcg_gen_ld_i32(tcg_ctx, res, uc->cpu_env, offsetof(CPUM68KState, fpsr));
         break;
     case M68K_FPCR:
-        tcg_gen_ld_i32(tcg_ctx, res, tcg_ctx->cpu_env, offsetof(CPUM68KState, fpcr));
+        tcg_gen_ld_i32(tcg_ctx, res, uc->cpu_env, offsetof(CPUM68KState, fpcr));
         break;
     }
 }
 
 static void gen_store_fcr(DisasContext *s, TCGv val, int reg)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
 
     switch (reg) {
     case M68K_FPIAR:
         break;
     case M68K_FPSR:
-        tcg_gen_st_i32(tcg_ctx, val, tcg_ctx->cpu_env, offsetof(CPUM68KState, fpsr));
+        tcg_gen_st_i32(tcg_ctx, val, uc->cpu_env, offsetof(CPUM68KState, fpsr));
         break;
     case M68K_FPCR:
-        gen_helper_set_fpcr(tcg_ctx, tcg_ctx->cpu_env, val);
+        gen_helper_set_fpcr(tcg_ctx, uc->cpu_env, val);
         break;
     }
 }
@@ -5115,7 +5138,8 @@ static void gen_op_fmove_fcr(CPUM68KState *env, DisasContext *s,
 static void gen_op_fmovem(CPUM68KState *env, DisasContext *s,
                           uint32_t insn, uint32_t ext)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     int opsize;
     TCGv addr, tmp;
     int mode = (ext >> 11) & 0x3;
@@ -5147,23 +5171,23 @@ static void gen_op_fmovem(CPUM68KState *env, DisasContext *s,
          * only available to store register to memory
          */
         if (opsize == OS_EXTENDED) {
-            gen_helper_fmovemx_st_predec(tcg_ctx, tmp, tcg_ctx->cpu_env, addr, tmp);
+            gen_helper_fmovemx_st_predec(tcg_ctx, tmp, uc->cpu_env, addr, tmp);
         } else {
-            gen_helper_fmovemd_st_predec(tcg_ctx, tmp, tcg_ctx->cpu_env, addr, tmp);
+            gen_helper_fmovemd_st_predec(tcg_ctx, tmp, uc->cpu_env, addr, tmp);
         }
     } else {
         /* postincrement addressing mode */
         if (opsize == OS_EXTENDED) {
             if (is_load) {
-                gen_helper_fmovemx_ld_postinc(tcg_ctx, tmp, tcg_ctx->cpu_env, addr, tmp);
+                gen_helper_fmovemx_ld_postinc(tcg_ctx, tmp, uc->cpu_env, addr, tmp);
             } else {
-                gen_helper_fmovemx_st_postinc(tcg_ctx, tmp, tcg_ctx->cpu_env, addr, tmp);
+                gen_helper_fmovemx_st_postinc(tcg_ctx, tmp, uc->cpu_env, addr, tmp);
             }
         } else {
             if (is_load) {
-                gen_helper_fmovemd_ld_postinc(tcg_ctx, tmp, tcg_ctx->cpu_env, addr, tmp);
+                gen_helper_fmovemd_ld_postinc(tcg_ctx, tmp, uc->cpu_env, addr, tmp);
             } else {
-                gen_helper_fmovemd_st_postinc(tcg_ctx, tmp, tcg_ctx->cpu_env, addr, tmp);
+                gen_helper_fmovemd_st_postinc(tcg_ctx, tmp, uc->cpu_env, addr, tmp);
             }
         }
     }
@@ -5177,7 +5201,8 @@ static void gen_op_fmovem(CPUM68KState *env, DisasContext *s,
    immediately before the next FP instruction is executed.  */
 DISAS_INSN(fpu)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     uint16_t ext;
     int opmode;
     int opsize;
@@ -5195,7 +5220,7 @@ DISAS_INSN(fpu)
             /* fmovecr */
             TCGv rom_offset = tcg_const_i32(tcg_ctx, opmode);
             cpu_dest = gen_fp_ptr(s, REG(ext, 7));
-            gen_helper_fconst(tcg_ctx, tcg_ctx->cpu_env, cpu_dest, rom_offset);
+            gen_helper_fconst(tcg_ctx, uc->cpu_env, cpu_dest, rom_offset);
             tcg_temp_free_ptr(tcg_ctx, cpu_dest);
             tcg_temp_free(tcg_ctx, rom_offset);
             return;
@@ -5208,7 +5233,7 @@ DISAS_INSN(fpu)
                       EA_STORE, IS_USER(s)) == -1) {
             gen_addr_fault(s);
         }
-        gen_helper_ftst(tcg_ctx, tcg_ctx->cpu_env, cpu_src);
+        gen_helper_ftst(tcg_ctx, uc->cpu_env, cpu_src);
         tcg_temp_free_ptr(tcg_ctx, cpu_src);
         return;
     case 4: /* fmove to control register.  */
@@ -5243,133 +5268,133 @@ DISAS_INSN(fpu)
         gen_fp_move(s, cpu_dest, cpu_src);
         break;
     case 0x40: /* fsmove */
-        gen_helper_fsround(tcg_ctx, tcg_ctx->cpu_env, cpu_dest, cpu_src);
+        gen_helper_fsround(tcg_ctx, uc->cpu_env, cpu_dest, cpu_src);
         break;
     case 0x44: /* fdmove */
-        gen_helper_fdround(tcg_ctx, tcg_ctx->cpu_env, cpu_dest, cpu_src);
+        gen_helper_fdround(tcg_ctx, uc->cpu_env, cpu_dest, cpu_src);
         break;
     case 1: /* fint */
-        gen_helper_firound(tcg_ctx, tcg_ctx->cpu_env, cpu_dest, cpu_src);
+        gen_helper_firound(tcg_ctx, uc->cpu_env, cpu_dest, cpu_src);
         break;
     case 3: /* fintrz */
-        gen_helper_fitrunc(tcg_ctx, tcg_ctx->cpu_env, cpu_dest, cpu_src);
+        gen_helper_fitrunc(tcg_ctx, uc->cpu_env, cpu_dest, cpu_src);
         break;
     case 4: /* fsqrt */
-        gen_helper_fsqrt(tcg_ctx, tcg_ctx->cpu_env, cpu_dest, cpu_src);
+        gen_helper_fsqrt(tcg_ctx, uc->cpu_env, cpu_dest, cpu_src);
         break;
     case 0x41: /* fssqrt */
-        gen_helper_fssqrt(tcg_ctx, tcg_ctx->cpu_env, cpu_dest, cpu_src);
+        gen_helper_fssqrt(tcg_ctx, uc->cpu_env, cpu_dest, cpu_src);
         break;
     case 0x45: /* fdsqrt */
-        gen_helper_fdsqrt(tcg_ctx, tcg_ctx->cpu_env, cpu_dest, cpu_src);
+        gen_helper_fdsqrt(tcg_ctx, uc->cpu_env, cpu_dest, cpu_src);
         break;
     case 0x06: /* flognp1 */
-        gen_helper_flognp1(tcg_ctx, tcg_ctx->cpu_env, cpu_dest, cpu_src);
+        gen_helper_flognp1(tcg_ctx, uc->cpu_env, cpu_dest, cpu_src);
         break;
     case 0x10: /* fetox */
-        gen_helper_fetox(tcg_ctx, tcg_ctx->cpu_env, cpu_dest, cpu_src);
+        gen_helper_fetox(tcg_ctx, uc->cpu_env, cpu_dest, cpu_src);
         break;
     case 0x11: /* ftwotox */
-        gen_helper_ftwotox(tcg_ctx, tcg_ctx->cpu_env, cpu_dest, cpu_src);
+        gen_helper_ftwotox(tcg_ctx, uc->cpu_env, cpu_dest, cpu_src);
         break;
     case 0x12: /* ftentox */
-        gen_helper_ftentox(tcg_ctx, tcg_ctx->cpu_env, cpu_dest, cpu_src);
+        gen_helper_ftentox(tcg_ctx, uc->cpu_env, cpu_dest, cpu_src);
         break;
     case 0x14: /* flogn */
-        gen_helper_flogn(tcg_ctx, tcg_ctx->cpu_env, cpu_dest, cpu_src);
+        gen_helper_flogn(tcg_ctx, uc->cpu_env, cpu_dest, cpu_src);
         break;
     case 0x15: /* flog10 */
-        gen_helper_flog10(tcg_ctx, tcg_ctx->cpu_env, cpu_dest, cpu_src);
+        gen_helper_flog10(tcg_ctx, uc->cpu_env, cpu_dest, cpu_src);
         break;
     case 0x16: /* flog2 */
-        gen_helper_flog2(tcg_ctx, tcg_ctx->cpu_env, cpu_dest, cpu_src);
+        gen_helper_flog2(tcg_ctx, uc->cpu_env, cpu_dest, cpu_src);
         break;
     case 0x18: /* fabs */
-        gen_helper_fabs(tcg_ctx, tcg_ctx->cpu_env, cpu_dest, cpu_src);
+        gen_helper_fabs(tcg_ctx, uc->cpu_env, cpu_dest, cpu_src);
         break;
     case 0x58: /* fsabs */
-        gen_helper_fsabs(tcg_ctx, tcg_ctx->cpu_env, cpu_dest, cpu_src);
+        gen_helper_fsabs(tcg_ctx, uc->cpu_env, cpu_dest, cpu_src);
         break;
     case 0x5c: /* fdabs */
-        gen_helper_fdabs(tcg_ctx, tcg_ctx->cpu_env, cpu_dest, cpu_src);
+        gen_helper_fdabs(tcg_ctx, uc->cpu_env, cpu_dest, cpu_src);
         break;
     case 0x1a: /* fneg */
-        gen_helper_fneg(tcg_ctx, tcg_ctx->cpu_env, cpu_dest, cpu_src);
+        gen_helper_fneg(tcg_ctx, uc->cpu_env, cpu_dest, cpu_src);
         break;
     case 0x5a: /* fsneg */
-        gen_helper_fsneg(tcg_ctx, tcg_ctx->cpu_env, cpu_dest, cpu_src);
+        gen_helper_fsneg(tcg_ctx, uc->cpu_env, cpu_dest, cpu_src);
         break;
     case 0x5e: /* fdneg */
-        gen_helper_fdneg(tcg_ctx, tcg_ctx->cpu_env, cpu_dest, cpu_src);
+        gen_helper_fdneg(tcg_ctx, uc->cpu_env, cpu_dest, cpu_src);
         break;
     case 0x1e: /* fgetexp */
-        gen_helper_fgetexp(tcg_ctx, tcg_ctx->cpu_env, cpu_dest, cpu_src);
+        gen_helper_fgetexp(tcg_ctx, uc->cpu_env, cpu_dest, cpu_src);
         break;
     case 0x1f: /* fgetman */
-        gen_helper_fgetman(tcg_ctx, tcg_ctx->cpu_env, cpu_dest, cpu_src);
+        gen_helper_fgetman(tcg_ctx, uc->cpu_env, cpu_dest, cpu_src);
         break;
     case 0x20: /* fdiv */
-        gen_helper_fdiv(tcg_ctx, tcg_ctx->cpu_env, cpu_dest, cpu_src, cpu_dest);
+        gen_helper_fdiv(tcg_ctx, uc->cpu_env, cpu_dest, cpu_src, cpu_dest);
         break;
     case 0x60: /* fsdiv */
-        gen_helper_fsdiv(tcg_ctx, tcg_ctx->cpu_env, cpu_dest, cpu_src, cpu_dest);
+        gen_helper_fsdiv(tcg_ctx, uc->cpu_env, cpu_dest, cpu_src, cpu_dest);
         break;
     case 0x64: /* fddiv */
-        gen_helper_fddiv(tcg_ctx, tcg_ctx->cpu_env, cpu_dest, cpu_src, cpu_dest);
+        gen_helper_fddiv(tcg_ctx, uc->cpu_env, cpu_dest, cpu_src, cpu_dest);
         break;
     case 0x21: /* fmod */
-        gen_helper_fmod(tcg_ctx, tcg_ctx->cpu_env, cpu_dest, cpu_src, cpu_dest);
+        gen_helper_fmod(tcg_ctx, uc->cpu_env, cpu_dest, cpu_src, cpu_dest);
         break;
     case 0x22: /* fadd */
-        gen_helper_fadd(tcg_ctx, tcg_ctx->cpu_env, cpu_dest, cpu_src, cpu_dest);
+        gen_helper_fadd(tcg_ctx, uc->cpu_env, cpu_dest, cpu_src, cpu_dest);
         break;
     case 0x62: /* fsadd */
-        gen_helper_fsadd(tcg_ctx, tcg_ctx->cpu_env, cpu_dest, cpu_src, cpu_dest);
+        gen_helper_fsadd(tcg_ctx, uc->cpu_env, cpu_dest, cpu_src, cpu_dest);
         break;
     case 0x66: /* fdadd */
-        gen_helper_fdadd(tcg_ctx, tcg_ctx->cpu_env, cpu_dest, cpu_src, cpu_dest);
+        gen_helper_fdadd(tcg_ctx, uc->cpu_env, cpu_dest, cpu_src, cpu_dest);
         break;
     case 0x23: /* fmul */
-        gen_helper_fmul(tcg_ctx, tcg_ctx->cpu_env, cpu_dest, cpu_src, cpu_dest);
+        gen_helper_fmul(tcg_ctx, uc->cpu_env, cpu_dest, cpu_src, cpu_dest);
         break;
     case 0x63: /* fsmul */
-        gen_helper_fsmul(tcg_ctx, tcg_ctx->cpu_env, cpu_dest, cpu_src, cpu_dest);
+        gen_helper_fsmul(tcg_ctx, uc->cpu_env, cpu_dest, cpu_src, cpu_dest);
         break;
     case 0x67: /* fdmul */
-        gen_helper_fdmul(tcg_ctx, tcg_ctx->cpu_env, cpu_dest, cpu_src, cpu_dest);
+        gen_helper_fdmul(tcg_ctx, uc->cpu_env, cpu_dest, cpu_src, cpu_dest);
         break;
     case 0x24: /* fsgldiv */
-        gen_helper_fsgldiv(tcg_ctx, tcg_ctx->cpu_env, cpu_dest, cpu_src, cpu_dest);
+        gen_helper_fsgldiv(tcg_ctx, uc->cpu_env, cpu_dest, cpu_src, cpu_dest);
         break;
     case 0x25: /* frem */
-        gen_helper_frem(tcg_ctx, tcg_ctx->cpu_env, cpu_dest, cpu_src, cpu_dest);
+        gen_helper_frem(tcg_ctx, uc->cpu_env, cpu_dest, cpu_src, cpu_dest);
         break;
     case 0x26: /* fscale */
-        gen_helper_fscale(tcg_ctx, tcg_ctx->cpu_env, cpu_dest, cpu_src, cpu_dest);
+        gen_helper_fscale(tcg_ctx, uc->cpu_env, cpu_dest, cpu_src, cpu_dest);
         break;
     case 0x27: /* fsglmul */
-        gen_helper_fsglmul(tcg_ctx, tcg_ctx->cpu_env, cpu_dest, cpu_src, cpu_dest);
+        gen_helper_fsglmul(tcg_ctx, uc->cpu_env, cpu_dest, cpu_src, cpu_dest);
         break;
     case 0x28: /* fsub */
-        gen_helper_fsub(tcg_ctx, tcg_ctx->cpu_env, cpu_dest, cpu_src, cpu_dest);
+        gen_helper_fsub(tcg_ctx, uc->cpu_env, cpu_dest, cpu_src, cpu_dest);
         break;
     case 0x68: /* fssub */
-        gen_helper_fssub(tcg_ctx, tcg_ctx->cpu_env, cpu_dest, cpu_src, cpu_dest);
+        gen_helper_fssub(tcg_ctx, uc->cpu_env, cpu_dest, cpu_src, cpu_dest);
         break;
     case 0x6c: /* fdsub */
-        gen_helper_fdsub(tcg_ctx, tcg_ctx->cpu_env, cpu_dest, cpu_src, cpu_dest);
+        gen_helper_fdsub(tcg_ctx, uc->cpu_env, cpu_dest, cpu_src, cpu_dest);
         break;
     case 0x38: /* fcmp */
-        gen_helper_fcmp(tcg_ctx, tcg_ctx->cpu_env, cpu_src, cpu_dest);
+        gen_helper_fcmp(tcg_ctx, uc->cpu_env, cpu_src, cpu_dest);
         return;
     case 0x3a: /* ftst */
-        gen_helper_ftst(tcg_ctx, tcg_ctx->cpu_env, cpu_src);
+        gen_helper_ftst(tcg_ctx, uc->cpu_env, cpu_src);
         return;
     default:
         goto undef;
     }
     tcg_temp_free_ptr(tcg_ctx, cpu_src);
-    gen_helper_ftst(tcg_ctx, tcg_ctx->cpu_env, cpu_dest);
+    gen_helper_ftst(tcg_ctx, uc->cpu_env, cpu_dest);
     tcg_temp_free_ptr(tcg_ctx, cpu_dest);
     return;
 undef:
@@ -5643,7 +5668,8 @@ static void gen_mac_clear_flags(DisasContext *s)
 
 DISAS_INSN(mac)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv rx;
     TCGv ry;
     uint16_t ext;
@@ -5704,12 +5730,12 @@ DISAS_INSN(mac)
         ry = gen_mac_extract_word(s, ry, (ext & 0x40) != 0);
     }
     if (s->env->macsr & MACSR_FI) {
-        gen_helper_macmulf(tcg_ctx, s->mactmp, tcg_ctx->cpu_env, rx, ry);
+        gen_helper_macmulf(tcg_ctx, s->mactmp, uc->cpu_env, rx, ry);
     } else {
         if (s->env->macsr & MACSR_SU)
-            gen_helper_macmuls(tcg_ctx, s->mactmp, tcg_ctx->cpu_env, rx, ry);
+            gen_helper_macmuls(tcg_ctx, s->mactmp, uc->cpu_env, rx, ry);
         else
-            gen_helper_macmulu(tcg_ctx, s->mactmp, tcg_ctx->cpu_env, rx, ry);
+            gen_helper_macmulu(tcg_ctx, s->mactmp, uc->cpu_env, rx, ry);
         switch ((ext >> 9) & 3) {
         case 1:
             tcg_gen_shli_i64(tcg_ctx, s->mactmp, s->mactmp, 1);
@@ -5745,11 +5771,11 @@ DISAS_INSN(mac)
         tcg_gen_add_i64(tcg_ctx, MACREG(acc), MACREG(acc), s->mactmp);
 
     if (s->env->macsr & MACSR_FI)
-        gen_helper_macsatf(tcg_ctx, tcg_ctx->cpu_env, tcg_const_i32(tcg_ctx, acc));
+        gen_helper_macsatf(tcg_ctx, uc->cpu_env, tcg_const_i32(tcg_ctx, acc));
     else if (s->env->macsr & MACSR_SU)
-        gen_helper_macsats(tcg_ctx, tcg_ctx->cpu_env, tcg_const_i32(tcg_ctx, acc));
+        gen_helper_macsats(tcg_ctx, uc->cpu_env, tcg_const_i32(tcg_ctx, acc));
     else
-        gen_helper_macsatu(tcg_ctx, tcg_ctx->cpu_env, tcg_const_i32(tcg_ctx, acc));
+        gen_helper_macsatu(tcg_ctx, uc->cpu_env, tcg_const_i32(tcg_ctx, acc));
 
 #if 0
     /* Disabled because conditional branches clobber temporary vars.  */
@@ -5777,18 +5803,18 @@ DISAS_INSN(mac)
         else
             tcg_gen_add_i64(tcg_ctx, MACREG(acc), MACREG(acc), s->mactmp);
         if (s->env->macsr & MACSR_FI)
-            gen_helper_macsatf(tcg_ctx, tcg_ctx->cpu_env, tcg_const_i32(tcg_ctx, acc));
+            gen_helper_macsatf(tcg_ctx, uc->cpu_env, tcg_const_i32(tcg_ctx, acc));
         else if (s->env->macsr & MACSR_SU)
-            gen_helper_macsats(tcg_ctx, tcg_ctx->cpu_env, tcg_const_i32(tcg_ctx, acc));
+            gen_helper_macsats(tcg_ctx, uc->cpu_env, tcg_const_i32(tcg_ctx, acc));
         else
-            gen_helper_macsatu(tcg_ctx, tcg_ctx->cpu_env, tcg_const_i32(tcg_ctx, acc));
+            gen_helper_macsatu(tcg_ctx, uc->cpu_env, tcg_const_i32(tcg_ctx, acc));
 #if 0
         /* Disabled because conditional branches clobber temporary vars.  */
         if (l1 != -1)
             gen_set_label(tcg_ctx, l1);
 #endif
     }
-    gen_helper_mac_set_flags(tcg_ctx, tcg_ctx->cpu_env, tcg_const_i32(tcg_ctx, acc));
+    gen_helper_mac_set_flags(tcg_ctx, uc->cpu_env, tcg_const_i32(tcg_ctx, acc));
 
     if (insn & 0x30) {
         TCGv rw;
@@ -5809,7 +5835,8 @@ DISAS_INSN(mac)
 
 DISAS_INSN(from_mac)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv rx;
     TCGv_i64 acc;
     int accnum;
@@ -5818,7 +5845,7 @@ DISAS_INSN(from_mac)
     accnum = (insn >> 9) & 3;
     acc = MACREG(accnum);
     if (s->env->macsr & MACSR_FI) {
-        gen_helper_get_macf(tcg_ctx, rx, tcg_ctx->cpu_env, acc);
+        gen_helper_get_macf(tcg_ctx, rx, uc->cpu_env, acc);
     } else if ((s->env->macsr & MACSR_OMC) == 0) {
         tcg_gen_extrl_i64_i32(tcg_ctx, rx, acc);
     } else if (s->env->macsr & MACSR_SU) {
@@ -5834,15 +5861,16 @@ DISAS_INSN(from_mac)
 
 DISAS_INSN(move_mac)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     /* FIXME: This can be done without a helper.  */
     int src;
     TCGv dest;
     src = insn & 3;
     dest = tcg_const_i32(tcg_ctx, (insn >> 9) & 3);
-    gen_helper_mac_move(tcg_ctx, tcg_ctx->cpu_env, dest, tcg_const_i32(tcg_ctx, src));
+    gen_helper_mac_move(tcg_ctx, uc->cpu_env, dest, tcg_const_i32(tcg_ctx, src));
     gen_mac_clear_flags(s);
-    gen_helper_mac_set_flags(tcg_ctx, tcg_ctx->cpu_env, dest);
+    gen_helper_mac_set_flags(tcg_ctx, uc->cpu_env, dest);
 }
 
 DISAS_INSN(from_macsr)
@@ -5864,30 +5892,33 @@ DISAS_INSN(from_mask)
 
 DISAS_INSN(from_mext)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv reg;
     TCGv acc;
     reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
     acc = tcg_const_i32(tcg_ctx, (insn & 0x400) ? 2 : 0);
     if (s->env->macsr & MACSR_FI)
-        gen_helper_get_mac_extf(tcg_ctx, reg, tcg_ctx->cpu_env, acc);
+        gen_helper_get_mac_extf(tcg_ctx, reg, uc->cpu_env, acc);
     else
-        gen_helper_get_mac_exti(tcg_ctx, reg, tcg_ctx->cpu_env, acc);
+        gen_helper_get_mac_exti(tcg_ctx, reg, uc->cpu_env, acc);
 }
 
 DISAS_INSN(macsr_to_ccr)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv tmp = tcg_temp_new(tcg_ctx);
     tcg_gen_andi_i32(tcg_ctx, tmp, tcg_ctx->QREG_MACSR, 0xf);
-    gen_helper_set_sr(tcg_ctx, tcg_ctx->cpu_env, tmp);
+    gen_helper_set_sr(tcg_ctx, uc->cpu_env, tmp);
     tcg_temp_free(tcg_ctx, tmp);
     set_cc_op(s, CC_OP_FLAGS);
 }
 
 DISAS_INSN(to_mac)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv_i64 acc;
     TCGv val;
     int accnum;
@@ -5904,15 +5935,16 @@ DISAS_INSN(to_mac)
     }
     tcg_gen_andi_i32(tcg_ctx, tcg_ctx->QREG_MACSR, tcg_ctx->QREG_MACSR, ~(MACSR_PAV0 << accnum));
     gen_mac_clear_flags(s);
-    gen_helper_mac_set_flags(tcg_ctx, tcg_ctx->cpu_env, tcg_const_i32(tcg_ctx, accnum));
+    gen_helper_mac_set_flags(tcg_ctx, uc->cpu_env, tcg_const_i32(tcg_ctx, accnum));
 }
 
 DISAS_INSN(to_macsr)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv val;
     SRC_EA(env, val, OS_LONG, 0, NULL);
-    gen_helper_set_macsr(tcg_ctx, tcg_ctx->cpu_env, val);
+    gen_helper_set_macsr(tcg_ctx, uc->cpu_env, val);
     gen_lookup_tb(s);
 }
 
@@ -5926,17 +5958,18 @@ DISAS_INSN(to_mask)
 
 DISAS_INSN(to_mext)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv val;
     TCGv acc;
     SRC_EA(env, val, OS_LONG, 0, NULL);
     acc = tcg_const_i32(tcg_ctx, (insn & 0x400) ? 2 : 0);
     if (s->env->macsr & MACSR_FI)
-        gen_helper_set_mac_extf(tcg_ctx, tcg_ctx->cpu_env, val, acc);
+        gen_helper_set_mac_extf(tcg_ctx, uc->cpu_env, val, acc);
     else if (s->env->macsr & MACSR_SU)
-        gen_helper_set_mac_exts(tcg_ctx, tcg_ctx->cpu_env, val, acc);
+        gen_helper_set_mac_exts(tcg_ctx, uc->cpu_env, val, acc);
     else
-        gen_helper_set_mac_extu(tcg_ctx, tcg_ctx->cpu_env, val, acc);
+        gen_helper_set_mac_extu(tcg_ctx, uc->cpu_env, val, acc);
 }
 
 static void
@@ -6247,6 +6280,7 @@ static void disas_m68k_insn(CPUM68KState * env, DisasContext *s)
 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
 {
     CPUM68KState *env = cs->env_ptr;
+    struct uc_struct *uc = env->uc;
     DisasContext dc1, *dc = &dc1;
     target_ulong pc_start;
     int pc_offset;
@@ -6343,7 +6377,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
             update_cc_op(dc);
             tcg_gen_movi_i32(tcg_ctx, tcg_ctx->QREG_PC, dc->pc);
         }
-        gen_helper_raise_exception(tcg_ctx, tcg_ctx->cpu_env, tcg_const_i32(tcg_ctx, EXCP_DEBUG));
+        gen_helper_raise_exception(tcg_ctx, uc->cpu_env, tcg_const_i32(tcg_ctx, EXCP_DEBUG));
     } else {
         switch(dc->is_jmp) {
             case DISAS_NEXT:
diff --git a/qemu/target/mips/translate.c b/qemu/target/mips/translate.c
index e5cc4817..b1423e3f 100644
--- a/qemu/target/mips/translate.c
+++ b/qemu/target/mips/translate.c
@@ -1373,43 +1373,43 @@ enum {
 
 #define gen_helper_0e0i(tcg_ctx, name, arg) do {                           \
     TCGv_i32 helper_tmp = tcg_const_i32(tcg_ctx, arg);                     \
-    gen_helper_##name(tcg_ctx, tcg_ctx->cpu_env, helper_tmp);                       \
+    gen_helper_##name(tcg_ctx, tcg_ctx->uc->cpu_env, helper_tmp);          \
     tcg_temp_free_i32(tcg_ctx, helper_tmp);                                \
     } while(0)
 
 #define gen_helper_0e1i(tcg_ctx, name, arg1, arg2) do {                    \
     TCGv_i32 helper_tmp = tcg_const_i32(tcg_ctx, arg2);                    \
-    gen_helper_##name(tcg_ctx, tcg_ctx->cpu_env, arg1, helper_tmp);                 \
+    gen_helper_##name(tcg_ctx, tcg_ctx->uc->cpu_env, arg1, helper_tmp);    \
     tcg_temp_free_i32(tcg_ctx, helper_tmp);                                \
     } while(0)
 
 #define gen_helper_1e0i(tcg_ctx, name, ret, arg1) do {                     \
     TCGv_i32 helper_tmp = tcg_const_i32(tcg_ctx, arg1);                    \
-    gen_helper_##name(tcg_ctx, ret, tcg_ctx->cpu_env, helper_tmp);                  \
+    gen_helper_##name(tcg_ctx, ret, tcg_ctx->uc->cpu_env, helper_tmp);     \
     tcg_temp_free_i32(tcg_ctx, helper_tmp);                                \
     } while(0)
 
 #define gen_helper_1e1i(tcg_ctx, name, ret, arg1, arg2) do {               \
     TCGv_i32 helper_tmp = tcg_const_i32(tcg_ctx, arg2);                    \
-    gen_helper_##name(tcg_ctx, ret, tcg_ctx->cpu_env, arg1, helper_tmp);            \
+    gen_helper_##name(tcg_ctx, ret, tcg_ctx->uc->cpu_env, arg1, helper_tmp); \
     tcg_temp_free_i32(tcg_ctx, helper_tmp);                                \
     } while(0)
 
 #define gen_helper_0e2i(tcg_ctx, name, arg1, arg2, arg3) do {              \
     TCGv_i32 helper_tmp = tcg_const_i32(tcg_ctx, arg3);                    \
-    gen_helper_##name(tcg_ctx, tcg_ctx->cpu_env, arg1, arg2, helper_tmp);           \
+    gen_helper_##name(tcg_ctx, tcg_ctx->uc->cpu_env, arg1, arg2, helper_tmp); \
     tcg_temp_free_i32(tcg_ctx, helper_tmp);                                \
     } while(0)
 
 #define gen_helper_1e2i(tcg_ctx, name, ret, arg1, arg2, arg3) do {         \
     TCGv_i32 helper_tmp = tcg_const_i32(tcg_ctx, arg3);                    \
-    gen_helper_##name(tcg_ctx, ret, tcg_ctx->cpu_env, arg1, arg2, helper_tmp);      \
+    gen_helper_##name(tcg_ctx, ret, tcg_ctx->uc->cpu_env, arg1, arg2, helper_tmp); \
     tcg_temp_free_i32(tcg_ctx, helper_tmp);                                \
     } while(0)
 
 #define gen_helper_0e3i(tcg_ctx, name, arg1, arg2, arg3, arg4) do {        \
     TCGv_i32 helper_tmp = tcg_const_i32(tcg_ctx, arg4);                    \
-    gen_helper_##name(tcg_ctx, tcg_ctx->cpu_env, arg1, arg2, arg3, helper_tmp);     \
+    gen_helper_##name(tcg_ctx, tcg_ctx->uc->cpu_env, arg1, arg2, arg3, helper_tmp); \
     tcg_temp_free_i32(tcg_ctx, helper_tmp);                                \
     } while(0)
 
@@ -1534,7 +1534,8 @@ static inline void gen_store_gpr (TCGContext *tcg_ctx, TCGv t, int reg)
 /* Moves to/from shadow registers. */
 static inline void gen_load_srsgpr (DisasContext *s, int from, int to)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv t0 = tcg_temp_new(tcg_ctx);
 
     if (from == 0)
@@ -1543,12 +1544,12 @@ static inline void gen_load_srsgpr (DisasContext *s, int from, int to)
         TCGv_i32 t2 = tcg_temp_new_i32(tcg_ctx);
         TCGv_ptr addr = tcg_temp_new_ptr(tcg_ctx);
 
-        tcg_gen_ld_i32(tcg_ctx, t2, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_SRSCtl));
+        tcg_gen_ld_i32(tcg_ctx, t2, uc->cpu_env, offsetof(CPUMIPSState, CP0_SRSCtl));
         tcg_gen_shri_i32(tcg_ctx, t2, t2, CP0SRSCtl_PSS);
         tcg_gen_andi_i32(tcg_ctx, t2, t2, 0xf);
         tcg_gen_muli_i32(tcg_ctx, t2, t2, sizeof(target_ulong) * 32);
         tcg_gen_ext_i32_ptr(tcg_ctx, addr, t2);
-        tcg_gen_add_ptr(tcg_ctx, addr, tcg_ctx->cpu_env, addr);
+        tcg_gen_add_ptr(tcg_ctx, addr, uc->cpu_env, addr);
 
         tcg_gen_ld_tl(tcg_ctx, t0, addr, sizeof(target_ulong) * from);
         tcg_temp_free_ptr(tcg_ctx, addr);
@@ -1560,19 +1561,21 @@ static inline void gen_load_srsgpr (DisasContext *s, int from, int to)
 
 static inline void gen_store_srsgpr (DisasContext *s, int from, int to)
 {
-    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    struct uc_struct *uc = s->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
+
     if (to != 0) {
         TCGv t0 = tcg_temp_new(tcg_ctx);
         TCGv_i32 t2 = tcg_temp_new_i32(tcg_ctx);
         TCGv_ptr addr = tcg_temp_new_ptr(tcg_ctx);
 
         gen_load_gpr(s, t0, from);
-        tcg_gen_ld_i32(tcg_ctx, t2, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_SRSCtl));
+        tcg_gen_ld_i32(tcg_ctx, t2, uc->cpu_env, offsetof(CPUMIPSState, CP0_SRSCtl));
         tcg_gen_shri_i32(tcg_ctx, t2, t2, CP0SRSCtl_PSS);
         tcg_gen_andi_i32(tcg_ctx, t2, t2, 0xf);
         tcg_gen_muli_i32(tcg_ctx, t2, t2, sizeof(target_ulong) * 32);
         tcg_gen_ext_i32_ptr(tcg_ctx, addr, t2);
-        tcg_gen_add_ptr(tcg_ctx, addr, tcg_ctx->cpu_env, addr);
+        tcg_gen_add_ptr(tcg_ctx, addr, uc->cpu_env, addr);
 
         tcg_gen_st_tl(tcg_ctx, t0, addr, sizeof(target_ulong) * to);
         tcg_temp_free_ptr(tcg_ctx, addr);
@@ -1627,11 +1630,12 @@ static inline void restore_cpu_state(CPUMIPSState *env, DisasContext *ctx)
 
 static inline void generate_exception_err(DisasContext *ctx, int excp, int err)
 {
-    TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
+    struct uc_struct *uc = ctx->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv_i32 texcp = tcg_const_i32(tcg_ctx, excp);
     TCGv_i32 terr = tcg_const_i32(tcg_ctx, err);
     save_cpu_state(ctx, 1);
-    gen_helper_raise_exception_err(tcg_ctx, tcg_ctx->cpu_env, texcp, terr);
+    gen_helper_raise_exception_err(tcg_ctx, uc->cpu_env, texcp, terr);
     tcg_temp_free_i32(tcg_ctx, terr);
     tcg_temp_free_i32(tcg_ctx, texcp);
     ctx->bstate = BS_EXCP;
@@ -1963,7 +1967,8 @@ FOP_CONDS(abs, 1, ps, FMT_PS, 64)
 static inline void gen_r6_cmp_ ## fmt(DisasContext * ctx, int n,        \
                                       int ft, int fs, int fd)           \
 {                                                                       \
-    TCGContext *tcg_ctx = ctx->uc->tcg_ctx; \
+    struct uc_struct *uc = ctx->uc;                                     \
+    TCGContext *tcg_ctx = uc->tcg_ctx;                                  \
     TCGv_i ## bits fp0 = tcg_temp_new_i ## bits(tcg_ctx);               \
     TCGv_i ## bits fp1 = tcg_temp_new_i ## bits(tcg_ctx);               \
     if (ifmt == FMT_D) {                                                \
@@ -1973,70 +1978,70 @@ static inline void gen_r6_cmp_ ## fmt(DisasContext * ctx, int n,        \
     gen_ldcmp_fpr ## bits(ctx, fp1, ft);                                \
     switch (n) {                                                        \
     case  0:                                                            \
-        gen_helper_r6_cmp_ ## fmt ## _af(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0, fp1);       \
+        gen_helper_r6_cmp_ ## fmt ## _af(tcg_ctx, fp0, uc->cpu_env, fp0, fp1);       \
         break;                                                          \
     case  1:                                                            \
-        gen_helper_r6_cmp_ ## fmt ## _un(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0, fp1);       \
+        gen_helper_r6_cmp_ ## fmt ## _un(tcg_ctx, fp0, uc->cpu_env, fp0, fp1);       \
         break;                                                          \
     case  2:                                                            \
-        gen_helper_r6_cmp_ ## fmt ## _eq(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0, fp1);       \
+        gen_helper_r6_cmp_ ## fmt ## _eq(tcg_ctx, fp0, uc->cpu_env, fp0, fp1);       \
         break;                                                          \
     case  3:                                                            \
-        gen_helper_r6_cmp_ ## fmt ## _ueq(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0, fp1);      \
+        gen_helper_r6_cmp_ ## fmt ## _ueq(tcg_ctx, fp0, uc->cpu_env, fp0, fp1);      \
         break;                                                          \
     case  4:                                                            \
-        gen_helper_r6_cmp_ ## fmt ## _lt(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0, fp1);       \
+        gen_helper_r6_cmp_ ## fmt ## _lt(tcg_ctx, fp0, uc->cpu_env, fp0, fp1);       \
         break;                                                          \
     case  5:                                                            \
-        gen_helper_r6_cmp_ ## fmt ## _ult(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0, fp1);      \
+        gen_helper_r6_cmp_ ## fmt ## _ult(tcg_ctx, fp0, uc->cpu_env, fp0, fp1);      \
         break;                                                          \
     case  6:                                                            \
-        gen_helper_r6_cmp_ ## fmt ## _le(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0, fp1);       \
+        gen_helper_r6_cmp_ ## fmt ## _le(tcg_ctx, fp0, uc->cpu_env, fp0, fp1);       \
         break;                                                          \
     case  7:                                                            \
-        gen_helper_r6_cmp_ ## fmt ## _ule(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0, fp1);      \
+        gen_helper_r6_cmp_ ## fmt ## _ule(tcg_ctx, fp0, uc->cpu_env, fp0, fp1);      \
         break;                                                          \
     case  8:                                                            \
-        gen_helper_r6_cmp_ ## fmt ## _saf(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0, fp1);      \
+        gen_helper_r6_cmp_ ## fmt ## _saf(tcg_ctx, fp0, uc->cpu_env, fp0, fp1);      \
         break;                                                          \
     case  9:                                                            \
-        gen_helper_r6_cmp_ ## fmt ## _sun(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0, fp1);      \
+        gen_helper_r6_cmp_ ## fmt ## _sun(tcg_ctx, fp0, uc->cpu_env, fp0, fp1);      \
         break;                                                          \
     case 10:                                                            \
-        gen_helper_r6_cmp_ ## fmt ## _seq(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0, fp1);      \
+        gen_helper_r6_cmp_ ## fmt ## _seq(tcg_ctx, fp0, uc->cpu_env, fp0, fp1);      \
         break;                                                          \
     case 11:                                                            \
-        gen_helper_r6_cmp_ ## fmt ## _sueq(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0, fp1);     \
+        gen_helper_r6_cmp_ ## fmt ## _sueq(tcg_ctx, fp0, uc->cpu_env, fp0, fp1);     \
         break;                                                          \
     case 12:                                                            \
-        gen_helper_r6_cmp_ ## fmt ## _slt(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0, fp1);      \
+        gen_helper_r6_cmp_ ## fmt ## _slt(tcg_ctx, fp0, uc->cpu_env, fp0, fp1);      \
         break;                                                          \
     case 13:                                                            \
-        gen_helper_r6_cmp_ ## fmt ## _sult(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0, fp1);     \
+        gen_helper_r6_cmp_ ## fmt ## _sult(tcg_ctx, fp0, uc->cpu_env, fp0, fp1);     \
         break;                                                          \
     case 14:                                                            \
-        gen_helper_r6_cmp_ ## fmt ## _sle(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0, fp1);      \
+        gen_helper_r6_cmp_ ## fmt ## _sle(tcg_ctx, fp0, uc->cpu_env, fp0, fp1);      \
         break;                                                          \
     case 15:                                                            \
-        gen_helper_r6_cmp_ ## fmt ## _sule(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0, fp1);     \
+        gen_helper_r6_cmp_ ## fmt ## _sule(tcg_ctx, fp0, uc->cpu_env, fp0, fp1);     \
         break;                                                          \
     case 17:                                                            \
-        gen_helper_r6_cmp_ ## fmt ## _or(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0, fp1);       \
+        gen_helper_r6_cmp_ ## fmt ## _or(tcg_ctx, fp0, uc->cpu_env, fp0, fp1);       \
         break;                                                          \
     case 18:                                                            \
-        gen_helper_r6_cmp_ ## fmt ## _une(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0, fp1);      \
+        gen_helper_r6_cmp_ ## fmt ## _une(tcg_ctx, fp0, uc->cpu_env, fp0, fp1);      \
         break;                                                          \
     case 19:                                                            \
-        gen_helper_r6_cmp_ ## fmt ## _ne(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0, fp1);       \
+        gen_helper_r6_cmp_ ## fmt ## _ne(tcg_ctx, fp0, uc->cpu_env, fp0, fp1);       \
         break;                                                          \
     case 25:                                                            \
-        gen_helper_r6_cmp_ ## fmt ## _sor(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0, fp1);      \
+        gen_helper_r6_cmp_ ## fmt ## _sor(tcg_ctx, fp0, uc->cpu_env, fp0, fp1);      \
         break;                                                          \
     case 26:                                                            \
-        gen_helper_r6_cmp_ ## fmt ## _sune(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0, fp1);     \
+        gen_helper_r6_cmp_ ## fmt ## _sune(tcg_ctx, fp0, uc->cpu_env, fp0, fp1);     \
         break;                                                          \
     case 27:                                                            \
-        gen_helper_r6_cmp_ ## fmt ## _sne(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0, fp1);      \
+        gen_helper_r6_cmp_ ## fmt ## _sne(tcg_ctx, fp0, uc->cpu_env, fp0, fp1);      \
         break;                                                          \
     default:                                                            \
         abort();                                                        \
@@ -2054,17 +2059,18 @@ FOP_CONDNS(s, FMT_S, 32, gen_store_fpr32(ctx, fp0, fd))
 
 /* load/store instructions. */
 #ifdef CONFIG_USER_ONLY
-#define OP_LD_ATOMIC(insn,fname)                                                    \
-static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx,                   \
-                                DisasContext *ctx)                                  \
-{                                                                                   \
-    TCGContext *tcg_ctx = ctx->uc->tcg_ctx;                                         \
-    TCGv t0 = tcg_temp_new(tcg_ctx);                                                \
-    tcg_gen_mov_tl(tcg_ctx, t0, arg1);                                              \
-    tcg_gen_qemu_##fname(ret, arg1, ctx->mem_idx);                                  \
-    tcg_gen_st_tl(tcg_ctx, t0, tcg_ctx->cpu_env, offsetof(CPUMIPSState, lladdr));   \
-    tcg_gen_st_tl(tcg_ctx, ret, tcg_ctx->cpu_env, offsetof(CPUMIPSState, llval));   \
-    tcg_temp_free(tcg_ctx, t0);                                                     \
+#define OP_LD_ATOMIC(insn,fname)                                               \
+static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx,              \
+                                DisasContext *ctx)                             \
+{                                                                              \
+    struct uc_struct *uc = ctx->uc;                                            \
+    TCGContext *tcg_ctx = uc->tcg_ctx;                                         \
+    TCGv t0 = tcg_temp_new(tcg_ctx);                                           \
+    tcg_gen_mov_tl(tcg_ctx, t0, arg1);                                         \
+    tcg_gen_qemu_##fname(ret, arg1, ctx->mem_idx);                             \
+    tcg_gen_st_tl(tcg_ctx, t0, uc->cpu_env, offsetof(CPUMIPSState, lladdr));   \
+    tcg_gen_st_tl(tcg_ctx, ret, uc->cpu_env, offsetof(CPUMIPSState, llval));   \
+    tcg_temp_free(tcg_ctx, t0);                                                \
 }
 #else
 #define OP_LD_ATOMIC(insn,fname)                                    \
@@ -2086,21 +2092,22 @@ OP_LD_ATOMIC(lld,ld64);
 static inline void op_st_##insn(TCGv arg1, TCGv arg2, int rt, int mem_idx,                  \
                                 DisasContext *ctx)                                          \
 {                                                                                           \
-    TCGContext *tcg_ctx = ctx->uc->tcg_ctx;                                                 \
+    struct uc_struct *uc = ctx->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;                                                      \
     TCGv t0 = tcg_temp_new(tcg_ctx);                                                        \
     TCGLabel *l1 = gen_new_label(tcg_ctx);                                                  \
     TCGLabel *l2 = gen_new_label(tcg_ctx);                                                  \
                                                                                             \
     tcg_gen_andi_tl(tcg_ctx, t0, arg2, almask);                                             \
     tcg_gen_brcondi_tl(tcg_ctx, TCG_COND_EQ, t0, 0, l1);                                    \
-    tcg_gen_st_tl(tcg_ctx, arg2, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr));   \
+    tcg_gen_st_tl(tcg_ctx, arg2, uc->cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr));        \
     generate_exception(ctx, EXCP_AdES);                                                     \
     gen_set_label(tcg_ctx, l1);                                                             \
-    tcg_gen_ld_tl(tcg_ctx, t0, tcg_ctx->cpu_env, offsetof(CPUMIPSState, lladdr));           \
+    tcg_gen_ld_tl(tcg_ctx, t0, uc->cpu_env, offsetof(CPUMIPSState, lladdr));                \
     tcg_gen_brcond_tl(tcg_ctx, TCG_COND_NE, arg2, t0, l2);                                  \
     tcg_gen_movi_tl(tcg_ctx, t0, rt | ((almask << 3) & 0x20));                              \
-    tcg_gen_st_tl(tcg_ctx, t0, tcg_ctx->cpu_env, offsetof(CPUMIPSState, llreg));            \
-    tcg_gen_st_tl(tcg_ctx, arg1, tcg_ctx->cpu_env, offsetof(CPUMIPSState, llnewval));       \
+    tcg_gen_st_tl(tcg_ctx, t0, uc->cpu_env, offsetof(CPUMIPSState, llreg));                 \
+    tcg_gen_st_tl(tcg_ctx, arg1, uc->cpu_env, offsetof(CPUMIPSState, llnewval));            \
     generate_exception_end(ctx, EXCP_SC);                                                   \
     gen_set_label(tcg_ctx, l2);                                                             \
     tcg_gen_movi_tl(tcg_ctx, t0, 0);                                                        \
@@ -3675,7 +3682,8 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc,
 static void gen_mul_vr54xx (DisasContext *ctx, uint32_t opc,
                             int rd, int rs, int rt)
 {
-    TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
+    struct uc_struct *uc = ctx->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv t0 = tcg_temp_new(tcg_ctx);
     TCGv t1 = tcg_temp_new(tcg_ctx);
 
@@ -3684,46 +3692,46 @@ static void gen_mul_vr54xx (DisasContext *ctx, uint32_t opc,
 
     switch (opc) {
     case OPC_VR54XX_MULS:
-        gen_helper_muls(tcg_ctx, t0, tcg_ctx->cpu_env, t0, t1);
+        gen_helper_muls(tcg_ctx, t0, uc->cpu_env, t0, t1);
         break;
     case OPC_VR54XX_MULSU:
-        gen_helper_mulsu(tcg_ctx, t0, tcg_ctx->cpu_env, t0, t1);
+        gen_helper_mulsu(tcg_ctx, t0, uc->cpu_env, t0, t1);
         break;
     case OPC_VR54XX_MACC:
-        gen_helper_macc(tcg_ctx, t0, tcg_ctx->cpu_env, t0, t1);
+        gen_helper_macc(tcg_ctx, t0, uc->cpu_env, t0, t1);
         break;
     case OPC_VR54XX_MACCU:
-        gen_helper_maccu(tcg_ctx, t0, tcg_ctx->cpu_env, t0, t1);
+        gen_helper_maccu(tcg_ctx, t0, uc->cpu_env, t0, t1);
         break;
     case OPC_VR54XX_MSAC:
-        gen_helper_msac(tcg_ctx, t0, tcg_ctx->cpu_env, t0, t1);
+        gen_helper_msac(tcg_ctx, t0, uc->cpu_env, t0, t1);
         break;
     case OPC_VR54XX_MSACU:
-        gen_helper_msacu(tcg_ctx, t0, tcg_ctx->cpu_env, t0, t1);
+        gen_helper_msacu(tcg_ctx, t0, uc->cpu_env, t0, t1);
         break;
     case OPC_VR54XX_MULHI:
-        gen_helper_mulhi(tcg_ctx, t0, tcg_ctx->cpu_env, t0, t1);
+        gen_helper_mulhi(tcg_ctx, t0, uc->cpu_env, t0, t1);
         break;
     case OPC_VR54XX_MULHIU:
-        gen_helper_mulhiu(tcg_ctx, t0, tcg_ctx->cpu_env, t0, t1);
+        gen_helper_mulhiu(tcg_ctx, t0, uc->cpu_env, t0, t1);
         break;
     case OPC_VR54XX_MULSHI:
-        gen_helper_mulshi(tcg_ctx, t0, tcg_ctx->cpu_env, t0, t1);
+        gen_helper_mulshi(tcg_ctx, t0, uc->cpu_env, t0, t1);
         break;
     case OPC_VR54XX_MULSHIU:
-        gen_helper_mulshiu(tcg_ctx, t0, tcg_ctx->cpu_env, t0, t1);
+        gen_helper_mulshiu(tcg_ctx, t0, uc->cpu_env, t0, t1);
         break;
     case OPC_VR54XX_MACCHI:
-        gen_helper_macchi(tcg_ctx, t0, tcg_ctx->cpu_env, t0, t1);
+        gen_helper_macchi(tcg_ctx, t0, uc->cpu_env, t0, t1);
         break;
     case OPC_VR54XX_MACCHIU:
-        gen_helper_macchiu(tcg_ctx, t0, tcg_ctx->cpu_env, t0, t1);
+        gen_helper_macchiu(tcg_ctx, t0, uc->cpu_env, t0, t1);
         break;
     case OPC_VR54XX_MSACHI:
-        gen_helper_msachi(tcg_ctx, t0, tcg_ctx->cpu_env, t0, t1);
+        gen_helper_msachi(tcg_ctx, t0, uc->cpu_env, t0, t1);
         break;
     case OPC_VR54XX_MSACHIU:
-        gen_helper_msachiu(tcg_ctx, t0, tcg_ctx->cpu_env, t0, t1);
+        gen_helper_msachiu(tcg_ctx, t0, uc->cpu_env, t0, t1);
         break;
     default:
         MIPS_INVAL("mul vr54xx");
@@ -4348,7 +4356,8 @@ static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
 
 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
 {
-    TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
+    struct uc_struct *uc = ctx->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
 
     if (use_goto_tb(ctx, dest)) {
         tcg_gen_goto_tb(tcg_ctx, n);
@@ -4358,7 +4367,7 @@ static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
         gen_save_pc(ctx, dest);
         if (ctx->singlestep_enabled) {
             save_cpu_state(ctx, 0);
-            gen_helper_raise_exception_debug(tcg_ctx, tcg_ctx->cpu_env);
+            gen_helper_raise_exception_debug(tcg_ctx, uc->cpu_env);
         }
         tcg_gen_lookup_and_goto_ptr(tcg_ctx);
     }
@@ -4871,13 +4880,13 @@ static inline void gen_mthc0_entrylo(TCGContext *s, TCGv arg, target_ulong off)
     TCGv_i64 t1 = tcg_temp_new_i64(s);
 
     tcg_gen_ext_tl_i64(s, t0, arg);
-    tcg_gen_ld_i64(s, t1, s->cpu_env, off);
+    tcg_gen_ld_i64(s, t1, s->uc->cpu_env, off);
 #if defined(TARGET_MIPS64)
     tcg_gen_deposit_i64(s, t1, t1, t0, 30, 32);
 #else
     tcg_gen_concat32_i64(s, t1, t1, t0);
 #endif
-    tcg_gen_st_i64(s, t1, s->cpu_env, off);
+    tcg_gen_st_i64(s, t1, s->uc->cpu_env, off);
     tcg_temp_free_i64(s, t1);
     tcg_temp_free_i64(s, t0);
 }
@@ -4888,9 +4897,9 @@ static inline void gen_mthc0_store64(TCGContext *s, TCGv arg, target_ulong off)
     TCGv_i64 t1 = tcg_temp_new_i64(s);
 
     tcg_gen_ext_tl_i64(s, t0, arg);
-    tcg_gen_ld_i64(s, t1, s->cpu_env, off);
+    tcg_gen_ld_i64(s, t1, s->uc->cpu_env, off);
     tcg_gen_concat32_i64(s, t1, t1, t0);
-    tcg_gen_st_i64(s, t1, s->cpu_env, off);
+    tcg_gen_st_i64(s, t1, s->uc->cpu_env, off);
     tcg_temp_free_i64(s, t1);
     tcg_temp_free_i64(s, t0);
 }
@@ -4899,7 +4908,7 @@ static inline void gen_mfhc0_entrylo(TCGContext *s, TCGv arg, target_ulong off)
 {
     TCGv_i64 t0 = tcg_temp_new_i64(s);
 
-    tcg_gen_ld_i64(s, t0, s->cpu_env, off);
+    tcg_gen_ld_i64(s, t0, s->uc->cpu_env, off);
 #if defined(TARGET_MIPS64)
     tcg_gen_shri_i64(s, t0, t0, 30);
 #else
@@ -4913,7 +4922,7 @@ static inline void gen_mfhc0_load64(TCGContext *s, TCGv arg, target_ulong off, i
 {
     TCGv_i64 t0 = tcg_temp_new_i64(s);
 
-    tcg_gen_ld_i64(s, t0, s->cpu_env, off);
+    tcg_gen_ld_i64(s, t0, s->uc->cpu_env, off);
     tcg_gen_shri_i64(s, t0, t0, 32 + shift);
     gen_move_low32(s, arg, t0);
     tcg_temp_free_i64(s, t0);
@@ -4921,28 +4930,31 @@ static inline void gen_mfhc0_load64(TCGContext *s, TCGv arg, target_ulong off, i
 
 static inline void gen_mfc0_load32 (DisasContext *ctx, TCGv arg, target_ulong off)
 {
-    TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
+    struct uc_struct *uc = ctx->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv_i32 t0 = tcg_temp_new_i32(tcg_ctx);
 
-    tcg_gen_ld_i32(tcg_ctx, t0, tcg_ctx->cpu_env, off);
+    tcg_gen_ld_i32(tcg_ctx, t0, uc->cpu_env, off);
     tcg_gen_ext_i32_tl(tcg_ctx, arg, t0);
     tcg_temp_free_i32(tcg_ctx, t0);
 }
 
 static inline void gen_mfc0_load64 (DisasContext *ctx, TCGv arg, target_ulong off)
 {
-    TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
-    tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, off);
+    struct uc_struct *uc = ctx->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
+    tcg_gen_ld_tl(tcg_ctx, arg, uc->cpu_env, off);
     tcg_gen_ext32s_tl(tcg_ctx, arg, arg);
 }
 
 static inline void gen_mtc0_store32 (DisasContext *ctx, TCGv arg, target_ulong off)
 {
-    TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
+    struct uc_struct *uc = ctx->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv_i32 t0 = tcg_temp_new_i32(tcg_ctx);
 
     tcg_gen_trunc_tl_i32(tcg_ctx, t0, arg);
-    tcg_gen_st_i32(tcg_ctx, t0, tcg_ctx->cpu_env, off);
+    tcg_gen_st_i32(tcg_ctx, t0, uc->cpu_env, off);
     tcg_temp_free_i32(tcg_ctx, t0);
 }
 
@@ -4955,7 +4967,8 @@ static inline void gen_mtc0_store32 (DisasContext *ctx, TCGv arg, target_ulong o
 
 static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel)
 {
-    TCGContext *s = ctx->uc->tcg_ctx;
+    struct uc_struct *uc = ctx->uc;
+    TCGContext *s = uc->tcg_ctx;
     const char *rn = "invalid";
 
     CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
@@ -4990,7 +5003,7 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel)
             break;
         case 1:
             CP0_CHECK(ctx->mrp);
-            gen_helper_mfhc0_maar(s, arg, s->cpu_env);
+            gen_helper_mfhc0_maar(s, arg, uc->cpu_env);
             rn = "MAAR";
             break;
         default:
@@ -5065,7 +5078,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
             break;
         case 1:
             CP0_CHECK(ctx->mrp);
-            gen_helper_mthc0_maar(s, s->cpu_env, arg);
+            gen_helper_mthc0_maar(s, s->uc->cpu_env, arg);
             rn = "MAAR";
             break;
         default:
@@ -5107,7 +5120,8 @@ static inline void gen_mfc0_unimplemented(DisasContext *ctx, TCGv arg)
 
 static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
 {
-    TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
+    struct uc_struct *uc = ctx->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     const char *rn = "invalid";
 
     if (sel != 0)
@@ -5122,17 +5136,17 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
             break;
         case 1:
             CP0_CHECK(ctx->insn_flags & ASE_MT);
-            gen_helper_mfc0_mvpcontrol(tcg_ctx, arg, tcg_ctx->cpu_env);
+            gen_helper_mfc0_mvpcontrol(tcg_ctx, arg, uc->cpu_env);
             rn = "MVPControl";
             break;
         case 2:
             CP0_CHECK(ctx->insn_flags & ASE_MT);
-            gen_helper_mfc0_mvpconf0(tcg_ctx, arg, tcg_ctx->cpu_env);
+            gen_helper_mfc0_mvpconf0(tcg_ctx, arg, uc->cpu_env);
             rn = "MVPConf0";
             break;
         case 3:
             CP0_CHECK(ctx->insn_flags & ASE_MT);
-            gen_helper_mfc0_mvpconf1(tcg_ctx, arg, tcg_ctx->cpu_env);
+            gen_helper_mfc0_mvpconf1(tcg_ctx, arg, uc->cpu_env);
             rn = "MVPConf1";
             break;
         case 4:
@@ -5148,7 +5162,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
         switch (sel) {
         case 0:
             CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6));
-            gen_helper_mfc0_random(tcg_ctx, arg, tcg_ctx->cpu_env);
+            gen_helper_mfc0_random(tcg_ctx, arg, uc->cpu_env);
             rn = "Random";
             break;
         case 1:
@@ -5195,7 +5209,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
         case 0:
             {
                 TCGv_i64 tmp = tcg_temp_new_i64(tcg_ctx);
-                tcg_gen_ld_i64(tcg_ctx, tmp, tcg_ctx->cpu_env,
+                tcg_gen_ld_i64(tcg_ctx, tmp, uc->cpu_env,
                                offsetof(CPUMIPSState, CP0_EntryLo0));
 #if defined(TARGET_MIPS64)
                 if (ctx->rxi) {
@@ -5211,37 +5225,37 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
             break;
         case 1:
             CP0_CHECK(ctx->insn_flags & ASE_MT);
-            gen_helper_mfc0_tcstatus(tcg_ctx, arg, tcg_ctx->cpu_env);
+            gen_helper_mfc0_tcstatus(tcg_ctx, arg, uc->cpu_env);
             rn = "TCStatus";
             break;
         case 2:
             CP0_CHECK(ctx->insn_flags & ASE_MT);
-            gen_helper_mfc0_tcbind(tcg_ctx, arg, tcg_ctx->cpu_env);
+            gen_helper_mfc0_tcbind(tcg_ctx, arg, uc->cpu_env);
             rn = "TCBind";
             break;
         case 3:
             CP0_CHECK(ctx->insn_flags & ASE_MT);
-            gen_helper_mfc0_tcrestart(tcg_ctx, arg, tcg_ctx->cpu_env);
+            gen_helper_mfc0_tcrestart(tcg_ctx, arg, uc->cpu_env);
             rn = "TCRestart";
             break;
         case 4:
             CP0_CHECK(ctx->insn_flags & ASE_MT);
-            gen_helper_mfc0_tchalt(tcg_ctx, arg, tcg_ctx->cpu_env);
+            gen_helper_mfc0_tchalt(tcg_ctx, arg, uc->cpu_env);
             rn = "TCHalt";
             break;
         case 5:
             CP0_CHECK(ctx->insn_flags & ASE_MT);
-            gen_helper_mfc0_tccontext(tcg_ctx, arg, tcg_ctx->cpu_env);
+            gen_helper_mfc0_tccontext(tcg_ctx, arg, uc->cpu_env);
             rn = "TCContext";
             break;
         case 6:
             CP0_CHECK(ctx->insn_flags & ASE_MT);
-            gen_helper_mfc0_tcschedule(tcg_ctx, arg, tcg_ctx->cpu_env);
+            gen_helper_mfc0_tcschedule(tcg_ctx, arg, uc->cpu_env);
             rn = "TCSchedule";
             break;
         case 7:
             CP0_CHECK(ctx->insn_flags & ASE_MT);
-            gen_helper_mfc0_tcschefback(tcg_ctx, arg, tcg_ctx->cpu_env);
+            gen_helper_mfc0_tcschefback(tcg_ctx, arg, uc->cpu_env);
             rn = "TCScheFBack";
             break;
         default:
@@ -5253,7 +5267,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
         case 0:
             {
                 TCGv_i64 tmp = tcg_temp_new_i64(tcg_ctx);
-                tcg_gen_ld_i64(tcg_ctx, tmp, tcg_ctx->cpu_env,
+                tcg_gen_ld_i64(tcg_ctx, tmp, uc->cpu_env,
                                offsetof(CPUMIPSState, CP0_EntryLo1));
 #if defined(TARGET_MIPS64)
                 if (ctx->rxi) {
@@ -5279,7 +5293,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
     case 4:
         switch (sel) {
         case 0:
-            tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_Context));
+            tcg_gen_ld_tl(tcg_ctx, arg, uc->cpu_env, offsetof(CPUMIPSState, CP0_Context));
             tcg_gen_ext32s_tl(tcg_ctx, arg, arg);
             rn = "Context";
             break;
@@ -5289,7 +5303,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
             goto cp0_unimplemented;
         case 2:
             CP0_CHECK(ctx->ulri);
-            tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env,
+            tcg_gen_ld_tl(tcg_ctx, arg, uc->cpu_env,
                           offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
             tcg_gen_ext32s_tl(tcg_ctx, arg, arg);
             rn = "UserLocal";
@@ -5311,19 +5325,19 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
             break;
         case 2:
             CP0_CHECK(ctx->sc);
-            tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_SegCtl0));
+            tcg_gen_ld_tl(tcg_ctx, arg, uc->cpu_env, offsetof(CPUMIPSState, CP0_SegCtl0));
             tcg_gen_ext32s_tl(tcg_ctx, arg, arg);
             rn = "SegCtl0";
             break;
         case 3:
             CP0_CHECK(ctx->sc);
-            tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_SegCtl1));
+            tcg_gen_ld_tl(tcg_ctx, arg, uc->cpu_env, offsetof(CPUMIPSState, CP0_SegCtl1));
             tcg_gen_ext32s_tl(tcg_ctx, arg, arg);
             rn = "SegCtl1";
             break;
         case 4:
             CP0_CHECK(ctx->sc);
-            tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_SegCtl2));
+            tcg_gen_ld_tl(tcg_ctx, arg, uc->cpu_env, offsetof(CPUMIPSState, CP0_SegCtl2));
             tcg_gen_ext32s_tl(tcg_ctx, arg, arg);
             rn = "SegCtl2";
             break;
@@ -5380,7 +5394,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
     case 8:
         switch (sel) {
         case 0:
-            tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr));
+            tcg_gen_ld_tl(tcg_ctx, arg, uc->cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr));
             tcg_gen_ext32s_tl(tcg_ctx, arg, arg);
             rn = "BadVAddr";
             break;
@@ -5408,7 +5422,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
                gen_io_start();
             }
             #endif
-            gen_helper_mfc0_count(tcg_ctx, arg, tcg_ctx->cpu_env);
+            gen_helper_mfc0_count(tcg_ctx, arg, uc->cpu_env);
             #if 0
             if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) {
                 gen_io_end();
@@ -5429,7 +5443,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
     case 10:
         switch (sel) {
         case 0:
-            tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_EntryHi));
+            tcg_gen_ld_tl(tcg_ctx, arg, uc->cpu_env, offsetof(CPUMIPSState, CP0_EntryHi));
             tcg_gen_ext32s_tl(tcg_ctx, arg, arg);
             rn = "EntryHi";
             break;
@@ -5486,7 +5500,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
     case 14:
         switch (sel) {
         case 0:
-            tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_EPC));
+            tcg_gen_ld_tl(tcg_ctx, arg, uc->cpu_env, offsetof(CPUMIPSState, CP0_EPC));
             tcg_gen_ext32s_tl(tcg_ctx, arg, arg);
             rn = "EPC";
             break;
@@ -5502,14 +5516,14 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
             break;
         case 1:
             check_insn(ctx, ISA_MIPS32R2);
-            tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_EBase));
+            tcg_gen_ld_tl(tcg_ctx, arg, uc->cpu_env, offsetof(CPUMIPSState, CP0_EBase));
             tcg_gen_ext32s_tl(tcg_ctx, arg, arg);
             rn = "EBase";
             break;
         case 3:
             check_insn(ctx, ISA_MIPS32R2);
             CP0_CHECK(ctx->cmgcr);
-            tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBase));
+            tcg_gen_ld_tl(tcg_ctx, arg, uc->cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBase));
             tcg_gen_ext32s_tl(tcg_ctx, arg, arg);
             rn = "CMGCRBase";
             break;
@@ -5559,12 +5573,12 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
     case 17:
         switch (sel) {
         case 0:
-            gen_helper_mfc0_lladdr(tcg_ctx, arg, tcg_ctx->cpu_env);
+            gen_helper_mfc0_lladdr(tcg_ctx, arg, uc->cpu_env);
             rn = "LLAddr";
             break;
         case 1:
             CP0_CHECK(ctx->mrp);
-            gen_helper_mfc0_maar(tcg_ctx, arg, tcg_ctx->cpu_env);
+            gen_helper_mfc0_maar(tcg_ctx, arg, uc->cpu_env);
             rn = "MAAR";
             break;
         case 2:
@@ -5601,7 +5615,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
         case 0:
 #if defined(TARGET_MIPS64)
             check_insn(ctx, ISA_MIPS3);
-            tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_XContext));
+            tcg_gen_ld_tl(tcg_ctx, arg, uc->cpu_env, offsetof(CPUMIPSState, CP0_XContext));
             tcg_gen_ext32s_tl(tcg_ctx, arg, arg);
             rn = "XContext";
             break;
@@ -5629,7 +5643,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
     case 23:
         switch (sel) {
         case 0:
-            gen_helper_mfc0_debug(tcg_ctx, arg, tcg_ctx->cpu_env); /* EJTAG support */
+            gen_helper_mfc0_debug(tcg_ctx, arg, uc->cpu_env); /* EJTAG support */
             rn = "Debug";
             break;
         case 1:
@@ -5656,7 +5670,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
         switch (sel) {
         case 0:
             /* EJTAG support */
-            tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_DEPC));
+            tcg_gen_ld_tl(tcg_ctx, arg, uc->cpu_env, offsetof(CPUMIPSState, CP0_DEPC));
             tcg_gen_ext32s_tl(tcg_ctx, arg, arg);
             rn = "DEPC";
             break;
@@ -5730,7 +5744,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
         case 6:
             {
                 TCGv_i64 tmp = tcg_temp_new_i64(tcg_ctx);
-                tcg_gen_ld_i64(tcg_ctx, tmp, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_TagLo));
+                tcg_gen_ld_i64(tcg_ctx, tmp, uc->cpu_env, offsetof(CPUMIPSState, CP0_TagLo));
                 gen_move_low32(tcg_ctx, arg, tmp);
                 tcg_temp_free_i64(tcg_ctx, tmp);
             }
@@ -5770,7 +5784,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
     case 30:
         switch (sel) {
         case 0:
-            tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
+            tcg_gen_ld_tl(tcg_ctx, arg, uc->cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
             tcg_gen_ext32s_tl(tcg_ctx, arg, arg);
             rn = "ErrorEPC";
             break;
@@ -5787,7 +5801,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
             break;
         case 2: case 3: case 4: case 5: case 6: case 7:
             CP0_CHECK(ctx->kscrexist & (1 << sel));
-            tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env,
+            tcg_gen_ld_tl(tcg_ctx, arg, uc->cpu_env,
                           offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
             tcg_gen_ext32s_tl(tcg_ctx, arg, arg);
             rn = "KScratch";
@@ -5810,7 +5824,8 @@ cp0_unimplemented:
 
 static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
 {
-    TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
+    struct uc_struct *uc = ctx->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     const char *rn = "invalid";
 
     if (sel != 0)
@@ -5827,12 +5842,12 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
     case 0:
         switch (sel) {
         case 0:
-            gen_helper_mtc0_index(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_index(tcg_ctx, uc->cpu_env, arg);
             rn = "Index";
             break;
         case 1:
             CP0_CHECK(ctx->insn_flags & ASE_MT);
-            gen_helper_mtc0_mvpcontrol(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_mvpcontrol(tcg_ctx, uc->cpu_env, arg);
             rn = "MVPControl";
             break;
         case 2:
@@ -5862,39 +5877,39 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
             break;
         case 1:
             CP0_CHECK(ctx->insn_flags & ASE_MT);
-            gen_helper_mtc0_vpecontrol(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_vpecontrol(tcg_ctx, uc->cpu_env, arg);
             rn = "VPEControl";
             break;
         case 2:
             CP0_CHECK(ctx->insn_flags & ASE_MT);
-            gen_helper_mtc0_vpeconf0(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_vpeconf0(tcg_ctx, uc->cpu_env, arg);
             rn = "VPEConf0";
             break;
         case 3:
             CP0_CHECK(ctx->insn_flags & ASE_MT);
-            gen_helper_mtc0_vpeconf1(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_vpeconf1(tcg_ctx, uc->cpu_env, arg);
             rn = "VPEConf1";
             break;
         case 4:
             CP0_CHECK(ctx->insn_flags & ASE_MT);
-            gen_helper_mtc0_yqmask(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_yqmask(tcg_ctx, uc->cpu_env, arg);
             rn = "YQMask";
             break;
         case 5:
             CP0_CHECK(ctx->insn_flags & ASE_MT);
-            tcg_gen_st_tl(tcg_ctx, arg, tcg_ctx->cpu_env,
+            tcg_gen_st_tl(tcg_ctx, arg, uc->cpu_env,
                           offsetof(CPUMIPSState, CP0_VPESchedule));
             rn = "VPESchedule";
             break;
         case 6:
             CP0_CHECK(ctx->insn_flags & ASE_MT);
-            tcg_gen_st_tl(tcg_ctx, arg, tcg_ctx->cpu_env,
+            tcg_gen_st_tl(tcg_ctx, arg, uc->cpu_env,
                           offsetof(CPUMIPSState, CP0_VPEScheFBack));
             rn = "VPEScheFBack";
             break;
         case 7:
             CP0_CHECK(ctx->insn_flags & ASE_MT);
-            gen_helper_mtc0_vpeopt(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_vpeopt(tcg_ctx, uc->cpu_env, arg);
             rn = "VPEOpt";
             break;
         default:
@@ -5904,42 +5919,42 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
     case 2:
         switch (sel) {
         case 0:
-            gen_helper_mtc0_entrylo0(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_entrylo0(tcg_ctx, uc->cpu_env, arg);
             rn = "EntryLo0";
             break;
         case 1:
             CP0_CHECK(ctx->insn_flags & ASE_MT);
-            gen_helper_mtc0_tcstatus(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_tcstatus(tcg_ctx, uc->cpu_env, arg);
             rn = "TCStatus";
             break;
         case 2:
             CP0_CHECK(ctx->insn_flags & ASE_MT);
-            gen_helper_mtc0_tcbind(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_tcbind(tcg_ctx, uc->cpu_env, arg);
             rn = "TCBind";
             break;
         case 3:
             CP0_CHECK(ctx->insn_flags & ASE_MT);
-            gen_helper_mtc0_tcrestart(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_tcrestart(tcg_ctx, uc->cpu_env, arg);
             rn = "TCRestart";
             break;
         case 4:
             CP0_CHECK(ctx->insn_flags & ASE_MT);
-            gen_helper_mtc0_tchalt(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_tchalt(tcg_ctx, uc->cpu_env, arg);
             rn = "TCHalt";
             break;
         case 5:
             CP0_CHECK(ctx->insn_flags & ASE_MT);
-            gen_helper_mtc0_tccontext(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_tccontext(tcg_ctx, uc->cpu_env, arg);
             rn = "TCContext";
             break;
         case 6:
             CP0_CHECK(ctx->insn_flags & ASE_MT);
-            gen_helper_mtc0_tcschedule(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_tcschedule(tcg_ctx, uc->cpu_env, arg);
             rn = "TCSchedule";
             break;
         case 7:
             CP0_CHECK(ctx->insn_flags & ASE_MT);
-            gen_helper_mtc0_tcschefback(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_tcschefback(tcg_ctx, uc->cpu_env, arg);
             rn = "TCScheFBack";
             break;
         default:
@@ -5949,7 +5964,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
     case 3:
         switch (sel) {
         case 0:
-            gen_helper_mtc0_entrylo1(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_entrylo1(tcg_ctx, uc->cpu_env, arg);
             rn = "EntryLo1";
             break;
         case 1:
@@ -5964,16 +5979,16 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
     case 4:
         switch (sel) {
         case 0:
-            gen_helper_mtc0_context(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_context(tcg_ctx, uc->cpu_env, arg);
             rn = "Context";
             break;
         case 1:
-//            gen_helper_mtc0_contextconfig(tcg_ctx->cpu_env, arg); /* SmartMIPS ASE */
+//            gen_helper_mtc0_contextconfig(uc->cpu_env, arg); /* SmartMIPS ASE */
             rn = "ContextConfig";
             goto cp0_unimplemented;
         case 2:
             CP0_CHECK(ctx->ulri);
-            tcg_gen_st_tl(tcg_ctx, arg, tcg_ctx->cpu_env,
+            tcg_gen_st_tl(tcg_ctx, arg, uc->cpu_env,
                           offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
             rn = "UserLocal";
             break;
@@ -5984,28 +5999,28 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
     case 5:
         switch (sel) {
         case 0:
-            gen_helper_mtc0_pagemask(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_pagemask(tcg_ctx, uc->cpu_env, arg);
             rn = "PageMask";
             break;
         case 1:
             check_insn(ctx, ISA_MIPS32R2);
-            gen_helper_mtc0_pagegrain(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_pagegrain(tcg_ctx, uc->cpu_env, arg);
             rn = "PageGrain";
             ctx->bstate = BS_STOP;
             break;
         case 2:
             CP0_CHECK(ctx->sc);
-            gen_helper_mtc0_segctl0(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_segctl0(tcg_ctx, uc->cpu_env, arg);
             rn = "SegCtl0";
             break;
         case 3:
             CP0_CHECK(ctx->sc);
-            gen_helper_mtc0_segctl1(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_segctl1(tcg_ctx, uc->cpu_env, arg);
             rn = "SegCtl1";
             break;
         case 4:
             CP0_CHECK(ctx->sc);
-            gen_helper_mtc0_segctl2(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_segctl2(tcg_ctx, uc->cpu_env, arg);
             rn = "SegCtl2";
             break;
         default:
@@ -6015,32 +6030,32 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
     case 6:
         switch (sel) {
         case 0:
-            gen_helper_mtc0_wired(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_wired(tcg_ctx, uc->cpu_env, arg);
             rn = "Wired";
             break;
         case 1:
             check_insn(ctx, ISA_MIPS32R2);
-            gen_helper_mtc0_srsconf0(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_srsconf0(tcg_ctx, uc->cpu_env, arg);
             rn = "SRSConf0";
             break;
         case 2:
             check_insn(ctx, ISA_MIPS32R2);
-            gen_helper_mtc0_srsconf1(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_srsconf1(tcg_ctx, uc->cpu_env, arg);
             rn = "SRSConf1";
             break;
         case 3:
             check_insn(ctx, ISA_MIPS32R2);
-            gen_helper_mtc0_srsconf2(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_srsconf2(tcg_ctx, uc->cpu_env, arg);
             rn = "SRSConf2";
             break;
         case 4:
             check_insn(ctx, ISA_MIPS32R2);
-            gen_helper_mtc0_srsconf3(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_srsconf3(tcg_ctx, uc->cpu_env, arg);
             rn = "SRSConf3";
             break;
         case 5:
             check_insn(ctx, ISA_MIPS32R2);
-            gen_helper_mtc0_srsconf4(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_srsconf4(tcg_ctx, uc->cpu_env, arg);
             rn = "SRSConf4";
             break;
         default:
@@ -6051,7 +6066,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
         switch (sel) {
         case 0:
             check_insn(ctx, ISA_MIPS32R2);
-            gen_helper_mtc0_hwrena(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_hwrena(tcg_ctx, uc->cpu_env, arg);
             ctx->bstate = BS_STOP;
             rn = "HWREna";
             break;
@@ -6080,7 +6095,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
     case 9:
         switch (sel) {
         case 0:
-            gen_helper_mtc0_count(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_count(tcg_ctx, uc->cpu_env, arg);
             rn = "Count";
             break;
         /* 6,7 are implementation dependent */
@@ -6091,7 +6106,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
     case 10:
         switch (sel) {
         case 0:
-            gen_helper_mtc0_entryhi(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_entryhi(tcg_ctx, uc->cpu_env, arg);
             rn = "EntryHi";
             break;
         default:
@@ -6101,7 +6116,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
     case 11:
         switch (sel) {
         case 0:
-            gen_helper_mtc0_compare(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_compare(tcg_ctx, uc->cpu_env, arg);
             rn = "Compare";
             break;
         /* 6,7 are implementation dependent */
@@ -6113,7 +6128,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
         switch (sel) {
         case 0:
             save_cpu_state(ctx, 1);
-            gen_helper_mtc0_status(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_status(tcg_ctx, uc->cpu_env, arg);
             /* BS_STOP isn't good enough here, hflags may have changed. */
             gen_save_pc(ctx, ctx->pc + 4);
             ctx->bstate = BS_EXCP;
@@ -6121,14 +6136,14 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
             break;
         case 1:
             check_insn(ctx, ISA_MIPS32R2);
-            gen_helper_mtc0_intctl(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_intctl(tcg_ctx, uc->cpu_env, arg);
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
             rn = "IntCtl";
             break;
         case 2:
             check_insn(ctx, ISA_MIPS32R2);
-            gen_helper_mtc0_srsctl(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_srsctl(tcg_ctx, uc->cpu_env, arg);
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
             rn = "SRSCtl";
@@ -6148,7 +6163,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
         switch (sel) {
         case 0:
             save_cpu_state(ctx, 1);
-            gen_helper_mtc0_cause(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_cause(tcg_ctx, uc->cpu_env, arg);
             /* Stop translation as we may have triggered an interrupt. BS_STOP
              * isn't sufficient, we need to ensure we break out of translated
              * code to check for pending interrupts.  */
@@ -6163,7 +6178,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
     case 14:
         switch (sel) {
         case 0:
-            tcg_gen_st_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_EPC));
+            tcg_gen_st_tl(tcg_ctx, arg, uc->cpu_env, offsetof(CPUMIPSState, CP0_EPC));
             rn = "EPC";
             break;
         default:
@@ -6178,7 +6193,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
             break;
         case 1:
             check_insn(ctx, ISA_MIPS32R2);
-            gen_helper_mtc0_ebase(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_ebase(tcg_ctx, uc->cpu_env, arg);
             rn = "EBase";
             break;
         default:
@@ -6188,7 +6203,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
     case 16:
         switch (sel) {
         case 0:
-            gen_helper_mtc0_config0(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_config0(tcg_ctx, uc->cpu_env, arg);
             rn = "Config";
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
@@ -6198,24 +6213,24 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
             rn = "Config1";
             break;
         case 2:
-            gen_helper_mtc0_config2(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_config2(tcg_ctx, uc->cpu_env, arg);
             rn = "Config2";
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
             break;
         case 3:
-            gen_helper_mtc0_config3(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_config3(tcg_ctx, uc->cpu_env, arg);
             rn = "Config3";
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
             break;
         case 4:
-            gen_helper_mtc0_config4(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_config4(tcg_ctx, uc->cpu_env, arg);
             rn = "Config4";
             ctx->bstate = BS_STOP;
             break;
         case 5:
-            gen_helper_mtc0_config5(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_config5(tcg_ctx, uc->cpu_env, arg);
             rn = "Config5";
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
@@ -6237,17 +6252,17 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
     case 17:
         switch (sel) {
         case 0:
-            gen_helper_mtc0_lladdr(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_lladdr(tcg_ctx, uc->cpu_env, arg);
             rn = "LLAddr";
             break;
         case 1:
             CP0_CHECK(ctx->mrp);
-            gen_helper_mtc0_maar(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_maar(tcg_ctx, uc->cpu_env, arg);
             rn = "MAAR";
             break;
         case 2:
             CP0_CHECK(ctx->mrp);
-            gen_helper_mtc0_maari(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_maari(tcg_ctx, uc->cpu_env, arg);
             rn = "MAARI";
             break;
         default:
@@ -6279,7 +6294,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
         case 0:
 #if defined(TARGET_MIPS64)
             check_insn(ctx, ISA_MIPS3);
-            gen_helper_mtc0_xcontext(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_xcontext(tcg_ctx, uc->cpu_env, arg);
             rn = "XContext";
             break;
 #endif
@@ -6292,7 +6307,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
         CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6));
         switch (sel) {
         case 0:
-            gen_helper_mtc0_framemask(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_framemask(tcg_ctx, uc->cpu_env, arg);
             rn = "Framemask";
             break;
         default:
@@ -6306,20 +6321,20 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
     case 23:
         switch (sel) {
         case 0:
-            gen_helper_mtc0_debug(tcg_ctx, tcg_ctx->cpu_env, arg); /* EJTAG support */
+            gen_helper_mtc0_debug(tcg_ctx, uc->cpu_env, arg); /* EJTAG support */
             /* BS_STOP isn't good enough here, hflags may have changed. */
             gen_save_pc(ctx, ctx->pc + 4);
             ctx->bstate = BS_EXCP;
             rn = "Debug";
             break;
         case 1:
-//            gen_helper_mtc0_tracecontrol(tcg_ctx->cpu_env, arg); /* PDtrace support */
+//            gen_helper_mtc0_tracecontrol(uc->cpu_env, arg); /* PDtrace support */
             rn = "TraceControl";
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
             goto cp0_unimplemented;
         case 2:
-//            gen_helper_mtc0_tracecontrol2(tcg_ctx->cpu_env, arg); /* PDtrace support */
+//            gen_helper_mtc0_tracecontrol2(uc->cpu_env, arg); /* PDtrace support */
             rn = "TraceControl2";
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
@@ -6327,13 +6342,13 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
         case 3:
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
-//            gen_helper_mtc0_usertracedata(tcg_ctx->cpu_env, arg); /* PDtrace support */
+//            gen_helper_mtc0_usertracedata(uc->cpu_env, arg); /* PDtrace support */
             rn = "UserTraceData";
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
             goto cp0_unimplemented;
         case 4:
-//            gen_helper_mtc0_tracebpc(tcg_ctx->cpu_env, arg); /* PDtrace support */
+//            gen_helper_mtc0_tracebpc(uc->cpu_env, arg); /* PDtrace support */
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
             rn = "TraceBPC";
@@ -6346,7 +6361,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
         switch (sel) {
         case 0:
             /* EJTAG support */
-            tcg_gen_st_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_DEPC));
+            tcg_gen_st_tl(tcg_ctx, arg, uc->cpu_env, offsetof(CPUMIPSState, CP0_DEPC));
             rn = "DEPC";
             break;
         default:
@@ -6356,7 +6371,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
     case 25:
         switch (sel) {
         case 0:
-            gen_helper_mtc0_performance0(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_performance0(tcg_ctx, uc->cpu_env, arg);
             rn = "Performance0";
             break;
         case 1:
@@ -6394,7 +6409,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
     case 26:
         switch (sel) {
         case 0:
-            gen_helper_mtc0_errctl(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_errctl(tcg_ctx, uc->cpu_env, arg);
             ctx->bstate = BS_STOP;
             rn = "ErrCtl";
             break;
@@ -6418,14 +6433,14 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
         case 2:
         case 4:
         case 6:
-            gen_helper_mtc0_taglo(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_taglo(tcg_ctx, uc->cpu_env, arg);
             rn = "TagLo";
             break;
         case 1:
         case 3:
         case 5:
         case 7:
-            gen_helper_mtc0_datalo(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_datalo(tcg_ctx, uc->cpu_env, arg);
             rn = "DataLo";
             break;
         default:
@@ -6438,14 +6453,14 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
         case 2:
         case 4:
         case 6:
-            gen_helper_mtc0_taghi(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_taghi(tcg_ctx, uc->cpu_env, arg);
             rn = "TagHi";
             break;
         case 1:
         case 3:
         case 5:
         case 7:
-            gen_helper_mtc0_datahi(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_datahi(tcg_ctx, uc->cpu_env, arg);
             rn = "DataHi";
             break;
         default:
@@ -6456,7 +6471,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
     case 30:
         switch (sel) {
         case 0:
-            tcg_gen_st_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
+            tcg_gen_st_tl(tcg_ctx, arg, uc->cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
             rn = "ErrorEPC";
             break;
         default:
@@ -6472,7 +6487,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
             break;
         case 2: case 3: case 4: case 5: case 6: case 7:
             CP0_CHECK(ctx->kscrexist & (1 << sel));
-            tcg_gen_st_tl(tcg_ctx, arg, tcg_ctx->cpu_env,
+            tcg_gen_st_tl(tcg_ctx, arg, uc->cpu_env,
                           offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
             rn = "KScratch";
             break;
@@ -6503,7 +6518,8 @@ cp0_unimplemented:
 #if defined(TARGET_MIPS64)
 static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
 {
-    TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
+    struct uc_struct *uc = ctx->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     const char *rn = "invalid";
 
     if (sel != 0)
@@ -6518,17 +6534,17 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
             break;
         case 1:
             CP0_CHECK(ctx->insn_flags & ASE_MT);
-            gen_helper_mfc0_mvpcontrol(tcg_ctx, arg, tcg_ctx->cpu_env);
+            gen_helper_mfc0_mvpcontrol(tcg_ctx, arg, uc->cpu_env);
             rn = "MVPControl";
             break;
         case 2:
             CP0_CHECK(ctx->insn_flags & ASE_MT);
-            gen_helper_mfc0_mvpconf0(tcg_ctx, arg, tcg_ctx->cpu_env);
+            gen_helper_mfc0_mvpconf0(tcg_ctx, arg, uc->cpu_env);
             rn = "MVPConf0";
             break;
         case 3:
             CP0_CHECK(ctx->insn_flags & ASE_MT);
-            gen_helper_mfc0_mvpconf1(tcg_ctx, arg, tcg_ctx->cpu_env);
+            gen_helper_mfc0_mvpconf1(tcg_ctx, arg, uc->cpu_env);
             rn = "MVPConf1";
             break;
         case 4:
@@ -6544,7 +6560,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
         switch (sel) {
         case 0:
             CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6));
-            gen_helper_mfc0_random(tcg_ctx, arg, tcg_ctx->cpu_env);
+            gen_helper_mfc0_random(tcg_ctx, arg, uc->cpu_env);
             rn = "Random";
             break;
         case 1:
@@ -6564,17 +6580,17 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
             break;
         case 4:
             CP0_CHECK(ctx->insn_flags & ASE_MT);
-            tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_YQMask));
+            tcg_gen_ld_tl(tcg_ctx, arg, uc->cpu_env, offsetof(CPUMIPSState, CP0_YQMask));
             rn = "YQMask";
             break;
         case 5:
             CP0_CHECK(ctx->insn_flags & ASE_MT);
-            tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_VPESchedule));
+            tcg_gen_ld_tl(tcg_ctx, arg, uc->cpu_env, offsetof(CPUMIPSState, CP0_VPESchedule));
             rn = "VPESchedule";
             break;
         case 6:
             CP0_CHECK(ctx->insn_flags & ASE_MT);
-            tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_VPEScheFBack));
+            tcg_gen_ld_tl(tcg_ctx, arg, uc->cpu_env, offsetof(CPUMIPSState, CP0_VPEScheFBack));
             rn = "VPEScheFBack";
             break;
         case 7:
@@ -6589,42 +6605,42 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
     case 2:
         switch (sel) {
         case 0:
-            tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_EntryLo0));
+            tcg_gen_ld_tl(tcg_ctx, arg, uc->cpu_env, offsetof(CPUMIPSState, CP0_EntryLo0));
             rn = "EntryLo0";
             break;
         case 1:
             CP0_CHECK(ctx->insn_flags & ASE_MT);
-            gen_helper_mfc0_tcstatus(tcg_ctx, arg, tcg_ctx->cpu_env);
+            gen_helper_mfc0_tcstatus(tcg_ctx, arg, uc->cpu_env);
             rn = "TCStatus";
             break;
         case 2:
             CP0_CHECK(ctx->insn_flags & ASE_MT);
-            gen_helper_mfc0_tcbind(tcg_ctx, arg, tcg_ctx->cpu_env);
+            gen_helper_mfc0_tcbind(tcg_ctx, arg, uc->cpu_env);
             rn = "TCBind";
             break;
         case 3:
             CP0_CHECK(ctx->insn_flags & ASE_MT);
-            gen_helper_dmfc0_tcrestart(tcg_ctx, arg, tcg_ctx->cpu_env);
+            gen_helper_dmfc0_tcrestart(tcg_ctx, arg, uc->cpu_env);
             rn = "TCRestart";
             break;
         case 4:
             CP0_CHECK(ctx->insn_flags & ASE_MT);
-            gen_helper_dmfc0_tchalt(tcg_ctx, arg, tcg_ctx->cpu_env);
+            gen_helper_dmfc0_tchalt(tcg_ctx, arg, uc->cpu_env);
             rn = "TCHalt";
             break;
         case 5:
             CP0_CHECK(ctx->insn_flags & ASE_MT);
-            gen_helper_dmfc0_tccontext(tcg_ctx, arg, tcg_ctx->cpu_env);
+            gen_helper_dmfc0_tccontext(tcg_ctx, arg, uc->cpu_env);
             rn = "TCContext";
             break;
         case 6:
             CP0_CHECK(ctx->insn_flags & ASE_MT);
-            gen_helper_dmfc0_tcschedule(tcg_ctx, arg, tcg_ctx->cpu_env);
+            gen_helper_dmfc0_tcschedule(tcg_ctx, arg, uc->cpu_env);
             rn = "TCSchedule";
             break;
         case 7:
             CP0_CHECK(ctx->insn_flags & ASE_MT);
-            gen_helper_dmfc0_tcschefback(tcg_ctx, arg, tcg_ctx->cpu_env);
+            gen_helper_dmfc0_tcschefback(tcg_ctx, arg, uc->cpu_env);
             rn = "TCScheFBack";
             break;
         default:
@@ -6634,7 +6650,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
     case 3:
         switch (sel) {
         case 0:
-            tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_EntryLo1));
+            tcg_gen_ld_tl(tcg_ctx, arg, uc->cpu_env, offsetof(CPUMIPSState, CP0_EntryLo1));
             rn = "EntryLo1";
             break;
         case 1:
@@ -6649,7 +6665,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
     case 4:
         switch (sel) {
         case 0:
-            tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_Context));
+            tcg_gen_ld_tl(tcg_ctx, arg, uc->cpu_env, offsetof(CPUMIPSState, CP0_Context));
             rn = "Context";
             break;
         case 1:
@@ -6658,7 +6674,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
             goto cp0_unimplemented;
         case 2:
             CP0_CHECK(ctx->ulri);
-            tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env,
+            tcg_gen_ld_tl(tcg_ctx, arg, uc->cpu_env,
                           offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
             rn = "UserLocal";
             break;
@@ -6679,17 +6695,17 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
             break;
         case 2:
             CP0_CHECK(ctx->sc);
-            tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_SegCtl0));
+            tcg_gen_ld_tl(tcg_ctx, arg, uc->cpu_env, offsetof(CPUMIPSState, CP0_SegCtl0));
             rn = "SegCtl0";
             break;
         case 3:
             CP0_CHECK(ctx->sc);
-            tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_SegCtl1));
+            tcg_gen_ld_tl(tcg_ctx, arg, uc->cpu_env, offsetof(CPUMIPSState, CP0_SegCtl1));
             rn = "SegCtl1";
             break;
         case 4:
             CP0_CHECK(ctx->sc);
-            tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_SegCtl2));
+            tcg_gen_ld_tl(tcg_ctx, arg, uc->cpu_env, offsetof(CPUMIPSState, CP0_SegCtl2));
             rn = "SegCtl2";
             break;
         default:
@@ -6745,7 +6761,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
     case 8:
         switch (sel) {
         case 0:
-            tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr));
+            tcg_gen_ld_tl(tcg_ctx, arg, uc->cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr));
             rn = "BadVAddr";
             break;
         case 1:
@@ -6771,7 +6787,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
                 gen_io_start();
             }
             #endif
-            gen_helper_mfc0_count(tcg_ctx, arg, tcg_ctx->cpu_env);
+            gen_helper_mfc0_count(tcg_ctx, arg, uc->cpu_env);
             #if 0
             if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) {
                 gen_io_end();
@@ -6792,7 +6808,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
     case 10:
         switch (sel) {
         case 0:
-            tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_EntryHi));
+            tcg_gen_ld_tl(tcg_ctx, arg, uc->cpu_env, offsetof(CPUMIPSState, CP0_EntryHi));
             rn = "EntryHi";
             break;
         default:
@@ -6848,7 +6864,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
     case 14:
         switch (sel) {
         case 0:
-            tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_EPC));
+            tcg_gen_ld_tl(tcg_ctx, arg, uc->cpu_env, offsetof(CPUMIPSState, CP0_EPC));
             rn = "EPC";
             break;
         default:
@@ -6863,13 +6879,13 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
             break;
         case 1:
             check_insn(ctx, ISA_MIPS32R2);
-            tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_EBase));
+            tcg_gen_ld_tl(tcg_ctx, arg, uc->cpu_env, offsetof(CPUMIPSState, CP0_EBase));
             rn = "EBase";
             break;
         case 3:
             check_insn(ctx, ISA_MIPS32R2);
             CP0_CHECK(ctx->cmgcr);
-            tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBase));
+            tcg_gen_ld_tl(tcg_ctx, arg, uc->cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBase));
             rn = "CMGCRBase";
             break;
         default:
@@ -6918,12 +6934,12 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
     case 17:
         switch (sel) {
         case 0:
-            gen_helper_dmfc0_lladdr(tcg_ctx, arg, tcg_ctx->cpu_env);
+            gen_helper_dmfc0_lladdr(tcg_ctx, arg, uc->cpu_env);
             rn = "LLAddr";
             break;
         case 1:
             CP0_CHECK(ctx->mrp);
-            gen_helper_dmfc0_maar(tcg_ctx, arg, tcg_ctx->cpu_env);
+            gen_helper_dmfc0_maar(tcg_ctx, arg, uc->cpu_env);
             rn = "MAAR";
             break;
         case 2:
@@ -6959,7 +6975,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
         switch (sel) {
         case 0:
             check_insn(ctx, ISA_MIPS3);
-            tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_XContext));
+            tcg_gen_ld_tl(tcg_ctx, arg, uc->cpu_env, offsetof(CPUMIPSState, CP0_XContext));
             rn = "XContext";
             break;
         default:
@@ -6985,23 +7001,23 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
     case 23:
         switch (sel) {
         case 0:
-            gen_helper_mfc0_debug(tcg_ctx, arg, tcg_ctx->cpu_env); /* EJTAG support */
+            gen_helper_mfc0_debug(tcg_ctx, arg, uc->cpu_env); /* EJTAG support */
             rn = "Debug";
             break;
         case 1:
-//            gen_helper_dmfc0_tracecontrol(arg, tcg_ctx->cpu_env); /* PDtrace support */
+//            gen_helper_dmfc0_tracecontrol(arg, uc->cpu_env); /* PDtrace support */
             rn = "TraceControl";
             goto cp0_unimplemented;
         case 2:
-//            gen_helper_dmfc0_tracecontrol2(arg, tcg_ctx->cpu_env); /* PDtrace support */
+//            gen_helper_dmfc0_tracecontrol2(arg, uc->cpu_env); /* PDtrace support */
             rn = "TraceControl2";
             goto cp0_unimplemented;
         case 3:
-//            gen_helper_dmfc0_usertracedata(arg, tcg_ctx->cpu_env); /* PDtrace support */
+//            gen_helper_dmfc0_usertracedata(arg, uc->cpu_env); /* PDtrace support */
             rn = "UserTraceData";
             goto cp0_unimplemented;
         case 4:
-//            gen_helper_dmfc0_tracebpc(arg, tcg_ctx->cpu_env); /* PDtrace support */
+//            gen_helper_dmfc0_tracebpc(arg, uc->cpu_env); /* PDtrace support */
             rn = "TraceBPC";
             goto cp0_unimplemented;
         default:
@@ -7012,7 +7028,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
         switch (sel) {
         case 0:
             /* EJTAG support */
-            tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_DEPC));
+            tcg_gen_ld_tl(tcg_ctx, arg, uc->cpu_env, offsetof(CPUMIPSState, CP0_DEPC));
             rn = "DEPC";
             break;
         default:
@@ -7121,7 +7137,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
     case 30:
         switch (sel) {
         case 0:
-            tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
+            tcg_gen_ld_tl(tcg_ctx, arg, uc->cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
             rn = "ErrorEPC";
             break;
         default:
@@ -7137,7 +7153,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
             break;
         case 2: case 3: case 4: case 5: case 6: case 7:
             CP0_CHECK(ctx->kscrexist & (1 << sel));
-            tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env,
+            tcg_gen_ld_tl(tcg_ctx, arg, uc->cpu_env,
                           offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
             rn = "KScratch";
             break;
@@ -7159,7 +7175,8 @@ cp0_unimplemented:
 
 static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
 {
-    TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
+    struct uc_struct *uc = ctx->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     const char *rn = "invalid";
 
     if (sel != 0)
@@ -7176,12 +7193,12 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
     case 0:
         switch (sel) {
         case 0:
-            gen_helper_mtc0_index(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_index(tcg_ctx, uc->cpu_env, arg);
             rn = "Index";
             break;
         case 1:
             CP0_CHECK(ctx->insn_flags & ASE_MT);
-            gen_helper_mtc0_mvpcontrol(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_mvpcontrol(tcg_ctx, uc->cpu_env, arg);
             rn = "MVPControl";
             break;
         case 2:
@@ -7211,37 +7228,37 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
             break;
         case 1:
             CP0_CHECK(ctx->insn_flags & ASE_MT);
-            gen_helper_mtc0_vpecontrol(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_vpecontrol(tcg_ctx, uc->cpu_env, arg);
             rn = "VPEControl";
             break;
         case 2:
             CP0_CHECK(ctx->insn_flags & ASE_MT);
-            gen_helper_mtc0_vpeconf0(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_vpeconf0(tcg_ctx, uc->cpu_env, arg);
             rn = "VPEConf0";
             break;
         case 3:
             CP0_CHECK(ctx->insn_flags & ASE_MT);
-            gen_helper_mtc0_vpeconf1(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_vpeconf1(tcg_ctx, uc->cpu_env, arg);
             rn = "VPEConf1";
             break;
         case 4:
             CP0_CHECK(ctx->insn_flags & ASE_MT);
-            gen_helper_mtc0_yqmask(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_yqmask(tcg_ctx, uc->cpu_env, arg);
             rn = "YQMask";
             break;
         case 5:
             CP0_CHECK(ctx->insn_flags & ASE_MT);
-            tcg_gen_st_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_VPESchedule));
+            tcg_gen_st_tl(tcg_ctx, arg, uc->cpu_env, offsetof(CPUMIPSState, CP0_VPESchedule));
             rn = "VPESchedule";
             break;
         case 6:
             CP0_CHECK(ctx->insn_flags & ASE_MT);
-            tcg_gen_st_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_VPEScheFBack));
+            tcg_gen_st_tl(tcg_ctx, arg, uc->cpu_env, offsetof(CPUMIPSState, CP0_VPEScheFBack));
             rn = "VPEScheFBack";
             break;
         case 7:
             CP0_CHECK(ctx->insn_flags & ASE_MT);
-            gen_helper_mtc0_vpeopt(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_vpeopt(tcg_ctx, uc->cpu_env, arg);
             rn = "VPEOpt";
             break;
         default:
@@ -7251,42 +7268,42 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
     case 2:
         switch (sel) {
         case 0:
-            gen_helper_dmtc0_entrylo0(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_dmtc0_entrylo0(tcg_ctx, uc->cpu_env, arg);
             rn = "EntryLo0";
             break;
         case 1:
             CP0_CHECK(ctx->insn_flags & ASE_MT);
-            gen_helper_mtc0_tcstatus(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_tcstatus(tcg_ctx, uc->cpu_env, arg);
             rn = "TCStatus";
             break;
         case 2:
             CP0_CHECK(ctx->insn_flags & ASE_MT);
-            gen_helper_mtc0_tcbind(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_tcbind(tcg_ctx, uc->cpu_env, arg);
             rn = "TCBind";
             break;
         case 3:
             CP0_CHECK(ctx->insn_flags & ASE_MT);
-            gen_helper_mtc0_tcrestart(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_tcrestart(tcg_ctx, uc->cpu_env, arg);
             rn = "TCRestart";
             break;
         case 4:
             CP0_CHECK(ctx->insn_flags & ASE_MT);
-            gen_helper_mtc0_tchalt(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_tchalt(tcg_ctx, uc->cpu_env, arg);
             rn = "TCHalt";
             break;
         case 5:
             CP0_CHECK(ctx->insn_flags & ASE_MT);
-            gen_helper_mtc0_tccontext(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_tccontext(tcg_ctx, uc->cpu_env, arg);
             rn = "TCContext";
             break;
         case 6:
             CP0_CHECK(ctx->insn_flags & ASE_MT);
-            gen_helper_mtc0_tcschedule(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_tcschedule(tcg_ctx, uc->cpu_env, arg);
             rn = "TCSchedule";
             break;
         case 7:
             CP0_CHECK(ctx->insn_flags & ASE_MT);
-            gen_helper_mtc0_tcschefback(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_tcschefback(tcg_ctx, uc->cpu_env, arg);
             rn = "TCScheFBack";
             break;
         default:
@@ -7296,7 +7313,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
     case 3:
         switch (sel) {
         case 0:
-            gen_helper_dmtc0_entrylo1(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_dmtc0_entrylo1(tcg_ctx, uc->cpu_env, arg);
             rn = "EntryLo1";
             break;
         case 1:
@@ -7311,16 +7328,16 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
     case 4:
         switch (sel) {
         case 0:
-            gen_helper_mtc0_context(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_context(tcg_ctx, uc->cpu_env, arg);
             rn = "Context";
             break;
         case 1:
-//           gen_helper_mtc0_contextconfig(tcg_ctx->cpu_env, arg); /* SmartMIPS ASE */
+//           gen_helper_mtc0_contextconfig(uc->cpu_env, arg); /* SmartMIPS ASE */
             rn = "ContextConfig";
             goto cp0_unimplemented;
         case 2:
             CP0_CHECK(ctx->ulri);
-            tcg_gen_st_tl(tcg_ctx, arg, tcg_ctx->cpu_env,
+            tcg_gen_st_tl(tcg_ctx, arg, uc->cpu_env,
                           offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
             rn = "UserLocal";
             break;
@@ -7331,27 +7348,27 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
     case 5:
         switch (sel) {
         case 0:
-            gen_helper_mtc0_pagemask(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_pagemask(tcg_ctx, uc->cpu_env, arg);
             rn = "PageMask";
             break;
         case 1:
             check_insn(ctx, ISA_MIPS32R2);
-            gen_helper_mtc0_pagegrain(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_pagegrain(tcg_ctx, uc->cpu_env, arg);
             rn = "PageGrain";
             break;
         case 2:
             CP0_CHECK(ctx->sc);
-            gen_helper_mtc0_segctl0(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_segctl0(tcg_ctx, uc->cpu_env, arg);
             rn = "SegCtl0";
             break;
         case 3:
             CP0_CHECK(ctx->sc);
-            gen_helper_mtc0_segctl1(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_segctl1(tcg_ctx, uc->cpu_env, arg);
             rn = "SegCtl1";
             break;
         case 4:
             CP0_CHECK(ctx->sc);
-            gen_helper_mtc0_segctl2(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_segctl2(tcg_ctx, uc->cpu_env, arg);
             rn = "SegCtl2";
             break;
         default:
@@ -7361,32 +7378,32 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
     case 6:
         switch (sel) {
         case 0:
-            gen_helper_mtc0_wired(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_wired(tcg_ctx, uc->cpu_env, arg);
             rn = "Wired";
             break;
         case 1:
             check_insn(ctx, ISA_MIPS32R2);
-            gen_helper_mtc0_srsconf0(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_srsconf0(tcg_ctx, uc->cpu_env, arg);
             rn = "SRSConf0";
             break;
         case 2:
             check_insn(ctx, ISA_MIPS32R2);
-            gen_helper_mtc0_srsconf1(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_srsconf1(tcg_ctx, uc->cpu_env, arg);
             rn = "SRSConf1";
             break;
         case 3:
             check_insn(ctx, ISA_MIPS32R2);
-            gen_helper_mtc0_srsconf2(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_srsconf2(tcg_ctx, uc->cpu_env, arg);
             rn = "SRSConf2";
             break;
         case 4:
             check_insn(ctx, ISA_MIPS32R2);
-            gen_helper_mtc0_srsconf3(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_srsconf3(tcg_ctx, uc->cpu_env, arg);
             rn = "SRSConf3";
             break;
         case 5:
             check_insn(ctx, ISA_MIPS32R2);
-            gen_helper_mtc0_srsconf4(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_srsconf4(tcg_ctx, uc->cpu_env, arg);
             rn = "SRSConf4";
             break;
         default:
@@ -7397,7 +7414,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
         switch (sel) {
         case 0:
             check_insn(ctx, ISA_MIPS32R2);
-            gen_helper_mtc0_hwrena(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_hwrena(tcg_ctx, uc->cpu_env, arg);
             ctx->bstate = BS_STOP;
             rn = "HWREna";
             break;
@@ -7426,7 +7443,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
     case 9:
         switch (sel) {
         case 0:
-            gen_helper_mtc0_count(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_count(tcg_ctx, uc->cpu_env, arg);
             rn = "Count";
             break;
         /* 6,7 are implementation dependent */
@@ -7439,7 +7456,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
     case 10:
         switch (sel) {
         case 0:
-            gen_helper_mtc0_entryhi(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_entryhi(tcg_ctx, uc->cpu_env, arg);
             rn = "EntryHi";
             break;
         default:
@@ -7449,7 +7466,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
     case 11:
         switch (sel) {
         case 0:
-            gen_helper_mtc0_compare(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_compare(tcg_ctx, uc->cpu_env, arg);
             rn = "Compare";
             break;
         /* 6,7 are implementation dependent */
@@ -7463,7 +7480,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
         switch (sel) {
         case 0:
             save_cpu_state(ctx, 1);
-            gen_helper_mtc0_status(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_status(tcg_ctx, uc->cpu_env, arg);
             /* BS_STOP isn't good enough here, hflags may have changed. */
             gen_save_pc(ctx, ctx->pc + 4);
             ctx->bstate = BS_EXCP;
@@ -7471,14 +7488,14 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
             break;
         case 1:
             check_insn(ctx, ISA_MIPS32R2);
-            gen_helper_mtc0_intctl(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_intctl(tcg_ctx, uc->cpu_env, arg);
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
             rn = "IntCtl";
             break;
         case 2:
             check_insn(ctx, ISA_MIPS32R2);
-            gen_helper_mtc0_srsctl(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_srsctl(tcg_ctx, uc->cpu_env, arg);
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
             rn = "SRSCtl";
@@ -7498,7 +7515,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
         switch (sel) {
         case 0:
             save_cpu_state(ctx, 1);
-            gen_helper_mtc0_cause(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_cause(tcg_ctx, uc->cpu_env, arg);
             /* Stop translation as we may have triggered an intetrupt. BS_STOP
              * isn't sufficient, we need to ensure we break out of translated
              * code to check for pending interrupts.  */
@@ -7513,7 +7530,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
     case 14:
         switch (sel) {
         case 0:
-            tcg_gen_st_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_EPC));
+            tcg_gen_st_tl(tcg_ctx, arg, uc->cpu_env, offsetof(CPUMIPSState, CP0_EPC));
             rn = "EPC";
             break;
         default:
@@ -7528,7 +7545,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
             break;
         case 1:
             check_insn(ctx, ISA_MIPS32R2);
-            gen_helper_mtc0_ebase(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_ebase(tcg_ctx, uc->cpu_env, arg);
             rn = "EBase";
             break;
         default:
@@ -7538,7 +7555,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
     case 16:
         switch (sel) {
         case 0:
-            gen_helper_mtc0_config0(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_config0(tcg_ctx, uc->cpu_env, arg);
             rn = "Config";
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
@@ -7548,13 +7565,13 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
             rn = "Config1";
             break;
         case 2:
-            gen_helper_mtc0_config2(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_config2(tcg_ctx, uc->cpu_env, arg);
             rn = "Config2";
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
             break;
         case 3:
-            gen_helper_mtc0_config3(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_config3(tcg_ctx, uc->cpu_env, arg);
             rn = "Config3";
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
@@ -7564,7 +7581,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
             rn = "Config4";
             break;
         case 5:
-            gen_helper_mtc0_config5(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_config5(tcg_ctx, uc->cpu_env, arg);
             rn = "Config5";
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
@@ -7578,17 +7595,17 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
     case 17:
         switch (sel) {
         case 0:
-            gen_helper_mtc0_lladdr(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_lladdr(tcg_ctx, uc->cpu_env, arg);
             rn = "LLAddr";
             break;
         case 1:
             CP0_CHECK(ctx->mrp);
-            gen_helper_mtc0_maar(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_maar(tcg_ctx, uc->cpu_env, arg);
             rn = "MAAR";
             break;
         case 2:
             CP0_CHECK(ctx->mrp);
-            gen_helper_mtc0_maari(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_maari(tcg_ctx, uc->cpu_env, arg);
             rn = "MAARI";
             break;
         default:
@@ -7619,7 +7636,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
         switch (sel) {
         case 0:
             check_insn(ctx, ISA_MIPS3);
-            gen_helper_mtc0_xcontext(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_xcontext(tcg_ctx, uc->cpu_env, arg);
             rn = "XContext";
             break;
         default:
@@ -7631,7 +7648,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
         CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6));
         switch (sel) {
         case 0:
-            gen_helper_mtc0_framemask(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_framemask(tcg_ctx, uc->cpu_env, arg);
             rn = "Framemask";
             break;
         default:
@@ -7645,32 +7662,32 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
     case 23:
         switch (sel) {
         case 0:
-            gen_helper_mtc0_debug(tcg_ctx, tcg_ctx->cpu_env, arg); /* EJTAG support */
+            gen_helper_mtc0_debug(tcg_ctx, uc->cpu_env, arg); /* EJTAG support */
             /* BS_STOP isn't good enough here, hflags may have changed. */
             gen_save_pc(ctx, ctx->pc + 4);
             ctx->bstate = BS_EXCP;
             rn = "Debug";
             break;
         case 1:
-//            gen_helper_mtc0_tracecontrol(tcg_ctx->cpu_env, arg); /* PDtrace support */
+//            gen_helper_mtc0_tracecontrol(uc->cpu_env, arg); /* PDtrace support */
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
             rn = "TraceControl";
             goto cp0_unimplemented;
         case 2:
-//            gen_helper_mtc0_tracecontrol2(tcg_ctx->cpu_env, arg); /* PDtrace support */
+//            gen_helper_mtc0_tracecontrol2(uc->cpu_env, arg); /* PDtrace support */
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
             rn = "TraceControl2";
             goto cp0_unimplemented;
         case 3:
-//            gen_helper_mtc0_usertracedata(tcg_ctx->cpu_env, arg); /* PDtrace support */
+//            gen_helper_mtc0_usertracedata(uc->cpu_env, arg); /* PDtrace support */
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
             rn = "UserTraceData";
             goto cp0_unimplemented;
         case 4:
-//            gen_helper_mtc0_tracebpc(tcg_ctx->cpu_env, arg); /* PDtrace support */
+//            gen_helper_mtc0_tracebpc(uc->cpu_env, arg); /* PDtrace support */
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
             rn = "TraceBPC";
@@ -7683,7 +7700,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
         switch (sel) {
         case 0:
             /* EJTAG support */
-            tcg_gen_st_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_DEPC));
+            tcg_gen_st_tl(tcg_ctx, arg, uc->cpu_env, offsetof(CPUMIPSState, CP0_DEPC));
             rn = "DEPC";
             break;
         default:
@@ -7693,35 +7710,35 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
     case 25:
         switch (sel) {
         case 0:
-            gen_helper_mtc0_performance0(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_performance0(tcg_ctx, uc->cpu_env, arg);
             rn = "Performance0";
             break;
         case 1:
-//            gen_helper_mtc0_performance1(tcg_ctx->cpu_env, arg);
+//            gen_helper_mtc0_performance1(uc->cpu_env, arg);
             rn = "Performance1";
             goto cp0_unimplemented;
         case 2:
-//            gen_helper_mtc0_performance2(tcg_ctx->cpu_env, arg);
+//            gen_helper_mtc0_performance2(uc->cpu_env, arg);
             rn = "Performance2";
             goto cp0_unimplemented;
         case 3:
-//            gen_helper_mtc0_performance3(tcg_ctx->cpu_env, arg);
+//            gen_helper_mtc0_performance3(uc->cpu_env, arg);
             rn = "Performance3";
             goto cp0_unimplemented;
         case 4:
-//            gen_helper_mtc0_performance4(tcg_ctx->cpu_env, arg);
+//            gen_helper_mtc0_performance4(uc->cpu_env, arg);
             rn = "Performance4";
             goto cp0_unimplemented;
         case 5:
-//            gen_helper_mtc0_performance5(tcg_ctx->cpu_env, arg);
+//            gen_helper_mtc0_performance5(uc->cpu_env, arg);
             rn = "Performance5";
             goto cp0_unimplemented;
         case 6:
-//            gen_helper_mtc0_performance6(tcg_ctx->cpu_env, arg);
+//            gen_helper_mtc0_performance6(uc->cpu_env, arg);
             rn = "Performance6";
             goto cp0_unimplemented;
         case 7:
-//            gen_helper_mtc0_performance7(tcg_ctx->cpu_env, arg);
+//            gen_helper_mtc0_performance7(uc->cpu_env, arg);
             rn = "Performance7";
             goto cp0_unimplemented;
         default:
@@ -7731,7 +7748,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
     case 26:
         switch (sel) {
         case 0:
-            gen_helper_mtc0_errctl(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_errctl(tcg_ctx, uc->cpu_env, arg);
             ctx->bstate = BS_STOP;
             rn = "ErrCtl";
             break;
@@ -7755,14 +7772,14 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
         case 2:
         case 4:
         case 6:
-            gen_helper_mtc0_taglo(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_taglo(tcg_ctx, uc->cpu_env, arg);
             rn = "TagLo";
             break;
         case 1:
         case 3:
         case 5:
         case 7:
-            gen_helper_mtc0_datalo(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_datalo(tcg_ctx, uc->cpu_env, arg);
             rn = "DataLo";
             break;
         default:
@@ -7775,14 +7792,14 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
         case 2:
         case 4:
         case 6:
-            gen_helper_mtc0_taghi(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_taghi(tcg_ctx, uc->cpu_env, arg);
             rn = "TagHi";
             break;
         case 1:
         case 3:
         case 5:
         case 7:
-            gen_helper_mtc0_datahi(tcg_ctx, tcg_ctx->cpu_env, arg);
+            gen_helper_mtc0_datahi(tcg_ctx, uc->cpu_env, arg);
             rn = "DataHi";
             break;
         default:
@@ -7793,7 +7810,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
     case 30:
         switch (sel) {
         case 0:
-            tcg_gen_st_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
+            tcg_gen_st_tl(tcg_ctx, arg, uc->cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
             rn = "ErrorEPC";
             break;
         default:
@@ -7809,7 +7826,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
             break;
         case 2: case 3: case 4: case 5: case 6: case 7:
             CP0_CHECK(ctx->kscrexist & (1 << sel));
-            tcg_gen_st_tl(tcg_ctx, arg, tcg_ctx->cpu_env,
+            tcg_gen_st_tl(tcg_ctx, arg, uc->cpu_env,
                           offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
             rn = "KScratch";
             break;
@@ -7840,7 +7857,8 @@ cp0_unimplemented:
 static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
                      int u, int sel, int h)
 {
-    TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
+    struct uc_struct *uc = ctx->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
     TCGv t0 = tcg_temp_local_new(tcg_ctx);
 
@@ -7856,10 +7874,10 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
         case 1:
             switch (sel) {
             case 1:
-                gen_helper_mftc0_vpecontrol(tcg_ctx, t0, tcg_ctx->cpu_env);
+                gen_helper_mftc0_vpecontrol(tcg_ctx, t0, uc->cpu_env);
                 break;
             case 2:
-                gen_helper_mftc0_vpeconf0(tcg_ctx, t0, tcg_ctx->cpu_env);
+                gen_helper_mftc0_vpeconf0(tcg_ctx, t0, uc->cpu_env);
                 break;
             default:
                 goto die;
@@ -7869,25 +7887,25 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
         case 2:
             switch (sel) {
             case 1:
-                gen_helper_mftc0_tcstatus(tcg_ctx, t0, tcg_ctx->cpu_env);
+                gen_helper_mftc0_tcstatus(tcg_ctx, t0, uc->cpu_env);
                 break;
             case 2:
-                gen_helper_mftc0_tcbind(tcg_ctx, t0, tcg_ctx->cpu_env);
+                gen_helper_mftc0_tcbind(tcg_ctx, t0, uc->cpu_env);
                 break;
             case 3:
-                gen_helper_mftc0_tcrestart(tcg_ctx, t0, tcg_ctx->cpu_env);
+                gen_helper_mftc0_tcrestart(tcg_ctx, t0, uc->cpu_env);
                 break;
             case 4:
-                gen_helper_mftc0_tchalt(tcg_ctx, t0, tcg_ctx->cpu_env);
+                gen_helper_mftc0_tchalt(tcg_ctx, t0, uc->cpu_env);
                 break;
             case 5:
-                gen_helper_mftc0_tccontext(tcg_ctx, t0, tcg_ctx->cpu_env);
+                gen_helper_mftc0_tccontext(tcg_ctx, t0, uc->cpu_env);
                 break;
             case 6:
-                gen_helper_mftc0_tcschedule(tcg_ctx, t0, tcg_ctx->cpu_env);
+                gen_helper_mftc0_tcschedule(tcg_ctx, t0, uc->cpu_env);
                 break;
             case 7:
-                gen_helper_mftc0_tcschefback(tcg_ctx, t0, tcg_ctx->cpu_env);
+                gen_helper_mftc0_tcschefback(tcg_ctx, t0, uc->cpu_env);
                 break;
             default:
                 gen_mfc0(ctx, t0, rt, sel);
@@ -7897,7 +7915,7 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
         case 10:
             switch (sel) {
             case 0:
-                gen_helper_mftc0_entryhi(tcg_ctx, t0, tcg_ctx->cpu_env);
+                gen_helper_mftc0_entryhi(tcg_ctx, t0, uc->cpu_env);
                 break;
             default:
                 gen_mfc0(ctx, t0, rt, sel);
@@ -7906,7 +7924,7 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
         case 12:
             switch (sel) {
             case 0:
-                gen_helper_mftc0_status(tcg_ctx, t0, tcg_ctx->cpu_env);
+                gen_helper_mftc0_status(tcg_ctx, t0, uc->cpu_env);
                 break;
             default:
                 gen_mfc0(ctx, t0, rt, sel);
@@ -7915,7 +7933,7 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
         case 13:
             switch (sel) {
             case 0:
-                gen_helper_mftc0_cause(tcg_ctx, t0, tcg_ctx->cpu_env);
+                gen_helper_mftc0_cause(tcg_ctx, t0, uc->cpu_env);
                 break;
             default:
                 goto die;
@@ -7925,7 +7943,7 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
         case 14:
             switch (sel) {
             case 0:
-                gen_helper_mftc0_epc(tcg_ctx, t0, tcg_ctx->cpu_env);
+                gen_helper_mftc0_epc(tcg_ctx, t0, uc->cpu_env);
                 break;
             default:
                 goto die;
@@ -7935,7 +7953,7 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
         case 15:
             switch (sel) {
             case 1:
-                gen_helper_mftc0_ebase(tcg_ctx, t0, tcg_ctx->cpu_env);
+                gen_helper_mftc0_ebase(tcg_ctx, t0, uc->cpu_env);
                 break;
             default:
                 goto die;
@@ -7945,7 +7963,7 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
         case 16:
             switch (sel) {
             case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7:
-                gen_helper_mftc0_configx(tcg_ctx, t0, tcg_ctx->cpu_env, tcg_const_tl(tcg_ctx, sel));
+                gen_helper_mftc0_configx(tcg_ctx, t0, uc->cpu_env, tcg_const_tl(tcg_ctx, sel));
                 break;
             default:
                 goto die;
@@ -7955,7 +7973,7 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
         case 23:
             switch (sel) {
             case 0:
-                gen_helper_mftc0_debug(tcg_ctx, t0, tcg_ctx->cpu_env);
+                gen_helper_mftc0_debug(tcg_ctx, t0, uc->cpu_env);
                 break;
             default:
                 gen_mfc0(ctx, t0, rt, sel);
@@ -8010,7 +8028,7 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
             gen_helper_1e0i(tcg_ctx, mftacx, t0, 3);
             break;
         case 16:
-            gen_helper_mftdsp(tcg_ctx, t0, tcg_ctx->cpu_env);
+            gen_helper_mftdsp(tcg_ctx, t0, uc->cpu_env);
             break;
         default:
             goto die;
@@ -8058,7 +8076,8 @@ die:
 static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
                      int u, int sel, int h)
 {
-    TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
+    struct uc_struct *uc = ctx->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
     TCGv t0 = tcg_temp_local_new(tcg_ctx);
 
@@ -8075,10 +8094,10 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
         case 1:
             switch (sel) {
             case 1:
-                gen_helper_mttc0_vpecontrol(tcg_ctx, tcg_ctx->cpu_env, t0);
+                gen_helper_mttc0_vpecontrol(tcg_ctx, uc->cpu_env, t0);
                 break;
             case 2:
-                gen_helper_mttc0_vpeconf0(tcg_ctx, tcg_ctx->cpu_env, t0);
+                gen_helper_mttc0_vpeconf0(tcg_ctx, uc->cpu_env, t0);
                 break;
             default:
                 goto die;
@@ -8088,25 +8107,25 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
         case 2:
             switch (sel) {
             case 1:
-                gen_helper_mttc0_tcstatus(tcg_ctx, tcg_ctx->cpu_env, t0);
+                gen_helper_mttc0_tcstatus(tcg_ctx, uc->cpu_env, t0);
                 break;
             case 2:
-                gen_helper_mttc0_tcbind(tcg_ctx, tcg_ctx->cpu_env, t0);
+                gen_helper_mttc0_tcbind(tcg_ctx, uc->cpu_env, t0);
                 break;
             case 3:
-                gen_helper_mttc0_tcrestart(tcg_ctx, tcg_ctx->cpu_env, t0);
+                gen_helper_mttc0_tcrestart(tcg_ctx, uc->cpu_env, t0);
                 break;
             case 4:
-                gen_helper_mttc0_tchalt(tcg_ctx, tcg_ctx->cpu_env, t0);
+                gen_helper_mttc0_tchalt(tcg_ctx, uc->cpu_env, t0);
                 break;
             case 5:
-                gen_helper_mttc0_tccontext(tcg_ctx, tcg_ctx->cpu_env, t0);
+                gen_helper_mttc0_tccontext(tcg_ctx, uc->cpu_env, t0);
                 break;
             case 6:
-                gen_helper_mttc0_tcschedule(tcg_ctx, tcg_ctx->cpu_env, t0);
+                gen_helper_mttc0_tcschedule(tcg_ctx, uc->cpu_env, t0);
                 break;
             case 7:
-                gen_helper_mttc0_tcschefback(tcg_ctx, tcg_ctx->cpu_env, t0);
+                gen_helper_mttc0_tcschefback(tcg_ctx, uc->cpu_env, t0);
                 break;
             default:
                 gen_mtc0(ctx, t0, rd, sel);
@@ -8116,7 +8135,7 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
         case 10:
             switch (sel) {
             case 0:
-                gen_helper_mttc0_entryhi(tcg_ctx, tcg_ctx->cpu_env, t0);
+                gen_helper_mttc0_entryhi(tcg_ctx, uc->cpu_env, t0);
                 break;
             default:
                 gen_mtc0(ctx, t0, rd, sel);
@@ -8125,7 +8144,7 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
         case 12:
             switch (sel) {
             case 0:
-                gen_helper_mttc0_status(tcg_ctx, tcg_ctx->cpu_env, t0);
+                gen_helper_mttc0_status(tcg_ctx, uc->cpu_env, t0);
                 break;
             default:
                 gen_mtc0(ctx, t0, rd, sel);
@@ -8134,7 +8153,7 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
         case 13:
             switch (sel) {
             case 0:
-                gen_helper_mttc0_cause(tcg_ctx, tcg_ctx->cpu_env, t0);
+                gen_helper_mttc0_cause(tcg_ctx, uc->cpu_env, t0);
                 break;
             default:
                 goto die;
@@ -8144,7 +8163,7 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
         case 15:
             switch (sel) {
             case 1:
-                gen_helper_mttc0_ebase(tcg_ctx, tcg_ctx->cpu_env, t0);
+                gen_helper_mttc0_ebase(tcg_ctx, uc->cpu_env, t0);
                 break;
             default:
                 goto die;
@@ -8154,7 +8173,7 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
         case 23:
             switch (sel) {
             case 0:
-                gen_helper_mttc0_debug(tcg_ctx, tcg_ctx->cpu_env, t0);
+                gen_helper_mttc0_debug(tcg_ctx, uc->cpu_env, t0);
                 break;
             default:
                 gen_mtc0(ctx, t0, rd, sel);
@@ -8209,7 +8228,7 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
             gen_helper_0e1i(tcg_ctx, mttacx, t0, 3);
             break;
         case 16:
-            gen_helper_mttdsp(tcg_ctx, tcg_ctx->cpu_env, t0);
+            gen_helper_mttdsp(tcg_ctx, uc->cpu_env, t0);
             break;
         default:
             goto die;
@@ -8262,7 +8281,8 @@ die:
 
 static void gen_cp0 (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, int rt, int rd)
 {
-    TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
+    struct uc_struct *uc = ctx->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv *cpu_gpr = tcg_ctx->cpu_gpr;
     const char *opn = "ldst";
 
@@ -8347,7 +8367,7 @@ static void gen_cp0 (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, int rt,
         opn = "tlbwi";
         if (!env->tlb->helper_tlbwi)
             goto die;
-        gen_helper_tlbwi(tcg_ctx, tcg_ctx->cpu_env);
+        gen_helper_tlbwi(tcg_ctx, uc->cpu_env);
         break;
     case OPC_TLBINV:
         opn = "tlbinv";
@@ -8355,7 +8375,7 @@ static void gen_cp0 (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, int rt,
             if (!env->tlb->helper_tlbinv) {
                 goto die;
             }
-            gen_helper_tlbinv(tcg_ctx, tcg_ctx->cpu_env);
+            gen_helper_tlbinv(tcg_ctx, uc->cpu_env);
         } /* treat as nop if TLBINV not supported */
         break;
     case OPC_TLBINVF:
@@ -8364,26 +8384,26 @@ static void gen_cp0 (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, int rt,
             if (!env->tlb->helper_tlbinvf) {
                 goto die;
             }
-            gen_helper_tlbinvf(tcg_ctx, tcg_ctx->cpu_env);
+            gen_helper_tlbinvf(tcg_ctx, uc->cpu_env);
         } /* treat as nop if TLBINV not supported */
         break;
     case OPC_TLBWR:
         opn = "tlbwr";
         if (!env->tlb->helper_tlbwr)
             goto die;
-        gen_helper_tlbwr(tcg_ctx, tcg_ctx->cpu_env);
+        gen_helper_tlbwr(tcg_ctx, uc->cpu_env);
         break;
     case OPC_TLBP:
         opn = "tlbp";
         if (!env->tlb->helper_tlbp)
             goto die;
-        gen_helper_tlbp(tcg_ctx, tcg_ctx->cpu_env);
+        gen_helper_tlbp(tcg_ctx, uc->cpu_env);
         break;
     case OPC_TLBR:
         opn = "tlbr";
         if (!env->tlb->helper_tlbr)
             goto die;
-        gen_helper_tlbr(tcg_ctx, tcg_ctx->cpu_env);
+        gen_helper_tlbr(tcg_ctx, uc->cpu_env);
         break;
     case OPC_ERET: /* OPC_ERETNC */
         if ((ctx->insn_flags & ISA_MIPS32R6) &&
@@ -8395,12 +8415,12 @@ static void gen_cp0 (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, int rt,
                 /* OPC_ERETNC */
                 opn = "eretnc";
                 check_insn(ctx, ISA_MIPS32R5);
-                gen_helper_eretnc(tcg_ctx, tcg_ctx->cpu_env);
+                gen_helper_eretnc(tcg_ctx, uc->cpu_env);
             } else {
                 /* OPC_ERET */
                 opn = "eret";
                 check_insn(ctx, ISA_MIPS2);
-                gen_helper_eret(tcg_ctx, tcg_ctx->cpu_env);
+                gen_helper_eret(tcg_ctx, uc->cpu_env);
             }
             ctx->bstate = BS_EXCP;
         }
@@ -8416,7 +8436,7 @@ static void gen_cp0 (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, int rt,
             MIPS_INVAL(opn);
             generate_exception_end(ctx, EXCP_RI);
         } else {
-            gen_helper_deret(tcg_ctx, tcg_ctx->cpu_env);
+            gen_helper_deret(tcg_ctx, uc->cpu_env);
             ctx->bstate = BS_EXCP;
         }
         break;
@@ -8431,7 +8451,7 @@ static void gen_cp0 (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, int rt,
         ctx->pc += 4;
         save_cpu_state(ctx, 1);
         ctx->pc -= 4;
-        gen_helper_wait(tcg_ctx, tcg_ctx->cpu_env);
+        gen_helper_wait(tcg_ctx, uc->cpu_env);
         ctx->bstate = BS_EXCP;
         break;
     default:
@@ -9084,7 +9104,8 @@ static void gen_sel_d(DisasContext *ctx, enum fopcode op1, int fd, int ft,
 static void gen_farith (DisasContext *ctx, enum fopcode op1,
                         int ft, int fs, int fd, int cc)
 {
-    TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
+    struct uc_struct *uc = ctx->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
 
     TCGv *cpu_gpr = tcg_ctx->cpu_gpr;
     uint32_t func = ctx->opcode & 0x3f;
@@ -9096,7 +9117,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
 
             gen_load_fpr32(ctx, fp0, fs);
             gen_load_fpr32(ctx, fp1, ft);
-            gen_helper_float_add_s(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0, fp1);
+            gen_helper_float_add_s(tcg_ctx, fp0, uc->cpu_env, fp0, fp1);
             tcg_temp_free_i32(tcg_ctx, fp1);
             gen_store_fpr32(ctx, fp0, fd);
             tcg_temp_free_i32(tcg_ctx, fp0);
@@ -9109,7 +9130,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
 
             gen_load_fpr32(ctx, fp0, fs);
             gen_load_fpr32(ctx, fp1, ft);
-            gen_helper_float_sub_s(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0, fp1);
+            gen_helper_float_sub_s(tcg_ctx, fp0, uc->cpu_env, fp0, fp1);
             tcg_temp_free_i32(tcg_ctx, fp1);
             gen_store_fpr32(ctx, fp0, fd);
             tcg_temp_free_i32(tcg_ctx, fp0);
@@ -9122,7 +9143,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
 
             gen_load_fpr32(ctx, fp0, fs);
             gen_load_fpr32(ctx, fp1, ft);
-            gen_helper_float_mul_s(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0, fp1);
+            gen_helper_float_mul_s(tcg_ctx, fp0, uc->cpu_env, fp0, fp1);
             tcg_temp_free_i32(tcg_ctx, fp1);
             gen_store_fpr32(ctx, fp0, fd);
             tcg_temp_free_i32(tcg_ctx, fp0);
@@ -9135,7 +9156,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
 
             gen_load_fpr32(ctx, fp0, fs);
             gen_load_fpr32(ctx, fp1, ft);
-            gen_helper_float_div_s(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0, fp1);
+            gen_helper_float_div_s(tcg_ctx, fp0, uc->cpu_env, fp0, fp1);
             tcg_temp_free_i32(tcg_ctx, fp1);
             gen_store_fpr32(ctx, fp0, fd);
             tcg_temp_free_i32(tcg_ctx, fp0);
@@ -9146,7 +9167,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
             TCGv_i32 fp0 = tcg_temp_new_i32(tcg_ctx);
 
             gen_load_fpr32(ctx, fp0, fs);
-            gen_helper_float_sqrt_s(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0);
+            gen_helper_float_sqrt_s(tcg_ctx, fp0, uc->cpu_env, fp0);
             gen_store_fpr32(ctx, fp0, fd);
             tcg_temp_free_i32(tcg_ctx, fp0);
         }
@@ -9196,9 +9217,9 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
 
             gen_load_fpr32(ctx, fp32, fs);
             if (ctx->nan2008) {
-                gen_helper_float_round_2008_l_s(tcg_ctx, fp64, tcg_ctx->cpu_env, fp32);
+                gen_helper_float_round_2008_l_s(tcg_ctx, fp64, uc->cpu_env, fp32);
             } else {
-                gen_helper_float_round_l_s(tcg_ctx, fp64, tcg_ctx->cpu_env, fp32);
+                gen_helper_float_round_l_s(tcg_ctx, fp64, uc->cpu_env, fp32);
             }
             tcg_temp_free_i32(tcg_ctx, fp32);
             gen_store_fpr64(ctx, fp64, fd);
@@ -9213,9 +9234,9 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
 
             gen_load_fpr32(ctx, fp32, fs);
             if (ctx->nan2008) {
-                gen_helper_float_trunc_2008_l_s(tcg_ctx, fp64, tcg_ctx->cpu_env, fp32);
+                gen_helper_float_trunc_2008_l_s(tcg_ctx, fp64, uc->cpu_env, fp32);
             } else {
-                gen_helper_float_trunc_l_s(tcg_ctx, fp64, tcg_ctx->cpu_env, fp32);
+                gen_helper_float_trunc_l_s(tcg_ctx, fp64, uc->cpu_env, fp32);
             }
             tcg_temp_free_i32(tcg_ctx, fp32);
             gen_store_fpr64(ctx, fp64, fd);
@@ -9230,9 +9251,9 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
 
             gen_load_fpr32(ctx, fp32, fs);
             if (ctx->nan2008) {
-                gen_helper_float_ceil_2008_l_s(tcg_ctx, fp64, tcg_ctx->cpu_env, fp32);
+                gen_helper_float_ceil_2008_l_s(tcg_ctx, fp64, uc->cpu_env, fp32);
             } else {
-                gen_helper_float_ceil_l_s(tcg_ctx, fp64, tcg_ctx->cpu_env, fp32);
+                gen_helper_float_ceil_l_s(tcg_ctx, fp64, uc->cpu_env, fp32);
             }
             tcg_temp_free_i32(tcg_ctx, fp32);
             gen_store_fpr64(ctx, fp64, fd);
@@ -9247,9 +9268,9 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
 
             gen_load_fpr32(ctx, fp32, fs);
             if (ctx->nan2008) {
-                gen_helper_float_floor_2008_l_s(tcg_ctx, fp64, tcg_ctx->cpu_env, fp32);
+                gen_helper_float_floor_2008_l_s(tcg_ctx, fp64, uc->cpu_env, fp32);
             } else {
-                gen_helper_float_floor_l_s(tcg_ctx, fp64, tcg_ctx->cpu_env, fp32);
+                gen_helper_float_floor_l_s(tcg_ctx, fp64, uc->cpu_env, fp32);
             }
             tcg_temp_free_i32(tcg_ctx, fp32);
             gen_store_fpr64(ctx, fp64, fd);
@@ -9262,9 +9283,9 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
 
             gen_load_fpr32(ctx, fp0, fs);
             if (ctx->nan2008) {
-                gen_helper_float_round_2008_w_s(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0);
+                gen_helper_float_round_2008_w_s(tcg_ctx, fp0, uc->cpu_env, fp0);
             } else {
-                gen_helper_float_round_w_s(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0);
+                gen_helper_float_round_w_s(tcg_ctx, fp0, uc->cpu_env, fp0);
             }
             gen_store_fpr32(ctx, fp0, fd);
             tcg_temp_free_i32(tcg_ctx, fp0);
@@ -9276,9 +9297,9 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
 
             gen_load_fpr32(ctx, fp0, fs);
             if (ctx->nan2008) {
-                gen_helper_float_trunc_2008_w_s(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0);
+                gen_helper_float_trunc_2008_w_s(tcg_ctx, fp0, uc->cpu_env, fp0);
             } else {
-                gen_helper_float_trunc_w_s(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0);
+                gen_helper_float_trunc_w_s(tcg_ctx, fp0, uc->cpu_env, fp0);
             }
             gen_store_fpr32(ctx, fp0, fd);
             tcg_temp_free_i32(tcg_ctx, fp0);
@@ -9290,9 +9311,9 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
 
             gen_load_fpr32(ctx, fp0, fs);
             if (ctx->nan2008) {
-                gen_helper_float_ceil_2008_w_s(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0);
+                gen_helper_float_ceil_2008_w_s(tcg_ctx, fp0, uc->cpu_env, fp0);
             } else {
-                gen_helper_float_ceil_w_s(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0);
+                gen_helper_float_ceil_w_s(tcg_ctx, fp0, uc->cpu_env, fp0);
             }
             gen_store_fpr32(ctx, fp0, fd);
             tcg_temp_free_i32(tcg_ctx, fp0);
@@ -9304,9 +9325,9 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
 
             gen_load_fpr32(ctx, fp0, fs);
             if (ctx->nan2008) {
-                gen_helper_float_floor_2008_w_s(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0);
+                gen_helper_float_floor_2008_w_s(tcg_ctx, fp0, uc->cpu_env, fp0);
             } else {
-                gen_helper_float_floor_w_s(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0);
+                gen_helper_float_floor_w_s(tcg_ctx, fp0, uc->cpu_env, fp0);
             }
             gen_store_fpr32(ctx, fp0, fd);
             tcg_temp_free_i32(tcg_ctx, fp0);
@@ -9365,7 +9386,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
             TCGv_i32 fp0 = tcg_temp_new_i32(tcg_ctx);
 
             gen_load_fpr32(ctx, fp0, fs);
-            gen_helper_float_recip_s(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0);
+            gen_helper_float_recip_s(tcg_ctx, fp0, uc->cpu_env, fp0);
             gen_store_fpr32(ctx, fp0, fd);
             tcg_temp_free_i32(tcg_ctx, fp0);
         }
@@ -9375,7 +9396,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
             TCGv_i32 fp0 = tcg_temp_new_i32(tcg_ctx);
 
             gen_load_fpr32(ctx, fp0, fs);
-            gen_helper_float_rsqrt_s(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0);
+            gen_helper_float_rsqrt_s(tcg_ctx, fp0, uc->cpu_env, fp0);
             gen_store_fpr32(ctx, fp0, fd);
             tcg_temp_free_i32(tcg_ctx, fp0);
         }
@@ -9389,7 +9410,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
             gen_load_fpr32(ctx, fp0, fs);
             gen_load_fpr32(ctx, fp1, ft);
             gen_load_fpr32(ctx, fp2, fd);
-            gen_helper_float_maddf_s(tcg_ctx, fp2, tcg_ctx->cpu_env, fp0, fp1, fp2);
+            gen_helper_float_maddf_s(tcg_ctx, fp2, uc->cpu_env, fp0, fp1, fp2);
             gen_store_fpr32(ctx, fp2, fd);
             tcg_temp_free_i32(tcg_ctx, fp2);
             tcg_temp_free_i32(tcg_ctx, fp1);
@@ -9405,7 +9426,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
             gen_load_fpr32(ctx, fp0, fs);
             gen_load_fpr32(ctx, fp1, ft);
             gen_load_fpr32(ctx, fp2, fd);
-            gen_helper_float_msubf_s(tcg_ctx, fp2, tcg_ctx->cpu_env, fp0, fp1, fp2);
+            gen_helper_float_msubf_s(tcg_ctx, fp2, uc->cpu_env, fp0, fp1, fp2);
             gen_store_fpr32(ctx, fp2, fd);
             tcg_temp_free_i32(tcg_ctx, fp2);
             tcg_temp_free_i32(tcg_ctx, fp1);
@@ -9417,7 +9438,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
         {
             TCGv_i32 fp0 = tcg_temp_new_i32(tcg_ctx);
             gen_load_fpr32(ctx, fp0, fs);
-            gen_helper_float_rint_s(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0);
+            gen_helper_float_rint_s(tcg_ctx, fp0, uc->cpu_env, fp0);
             gen_store_fpr32(ctx, fp0, fd);
             tcg_temp_free_i32(tcg_ctx, fp0);
         }
@@ -9427,7 +9448,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
         {
             TCGv_i32 fp0 = tcg_temp_new_i32(tcg_ctx);
             gen_load_fpr32(ctx, fp0, fs);
-            gen_helper_float_class_s(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0);
+            gen_helper_float_class_s(tcg_ctx, fp0, uc->cpu_env, fp0);
             gen_store_fpr32(ctx, fp0, fd);
             tcg_temp_free_i32(tcg_ctx, fp0);
         }
@@ -9440,7 +9461,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
             TCGv_i32 fp2 = tcg_temp_new_i32(tcg_ctx);
             gen_load_fpr32(ctx, fp0, fs);
             gen_load_fpr32(ctx, fp1, ft);
-            gen_helper_float_min_s(tcg_ctx, fp2, tcg_ctx->cpu_env, fp0, fp1);
+            gen_helper_float_min_s(tcg_ctx, fp2, uc->cpu_env, fp0, fp1);
             gen_store_fpr32(ctx, fp2, fd);
             tcg_temp_free_i32(tcg_ctx, fp2);
             tcg_temp_free_i32(tcg_ctx, fp1);
@@ -9454,7 +9475,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
 
                 gen_load_fpr32(ctx, fp0, fs);
                 gen_load_fpr32(ctx, fp1, ft);
-                gen_helper_float_recip2_s(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0, fp1);
+                gen_helper_float_recip2_s(tcg_ctx, fp0, uc->cpu_env, fp0, fp1);
                 tcg_temp_free_i32(tcg_ctx, fp1);
                 gen_store_fpr32(ctx, fp0, fd);
                 tcg_temp_free_i32(tcg_ctx, fp0);
@@ -9469,7 +9490,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
             TCGv_i32 fp2 = tcg_temp_new_i32(tcg_ctx);
             gen_load_fpr32(ctx, fp0, fs);
             gen_load_fpr32(ctx, fp1, ft);
-            gen_helper_float_mina_s(tcg_ctx, fp2, tcg_ctx->cpu_env, fp0, fp1);
+            gen_helper_float_mina_s(tcg_ctx, fp2, uc->cpu_env, fp0, fp1);
             gen_store_fpr32(ctx, fp2, fd);
             tcg_temp_free_i32(tcg_ctx, fp2);
             tcg_temp_free_i32(tcg_ctx, fp1);
@@ -9481,7 +9502,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
                 TCGv_i32 fp0 = tcg_temp_new_i32(tcg_ctx);
 
                 gen_load_fpr32(ctx, fp0, fs);
-                gen_helper_float_recip1_s(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0);
+                gen_helper_float_recip1_s(tcg_ctx, fp0, uc->cpu_env, fp0);
                 gen_store_fpr32(ctx, fp0, fd);
                 tcg_temp_free_i32(tcg_ctx, fp0);
             }
@@ -9494,7 +9515,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
             TCGv_i32 fp1 = tcg_temp_new_i32(tcg_ctx);
             gen_load_fpr32(ctx, fp0, fs);
             gen_load_fpr32(ctx, fp1, ft);
-            gen_helper_float_max_s(tcg_ctx, fp1, tcg_ctx->cpu_env, fp0, fp1);
+            gen_helper_float_max_s(tcg_ctx, fp1, uc->cpu_env, fp0, fp1);
             gen_store_fpr32(ctx, fp1, fd);
             tcg_temp_free_i32(tcg_ctx, fp1);
             tcg_temp_free_i32(tcg_ctx, fp0);
@@ -9505,7 +9526,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
                 TCGv_i32 fp0 = tcg_temp_new_i32(tcg_ctx);
 
                 gen_load_fpr32(ctx, fp0, fs);
-                gen_helper_float_rsqrt1_s(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0);
+                gen_helper_float_rsqrt1_s(tcg_ctx, fp0, uc->cpu_env, fp0);
                 gen_store_fpr32(ctx, fp0, fd);
                 tcg_temp_free_i32(tcg_ctx, fp0);
             }
@@ -9518,7 +9539,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
             TCGv_i32 fp1 = tcg_temp_new_i32(tcg_ctx);
             gen_load_fpr32(ctx, fp0, fs);
             gen_load_fpr32(ctx, fp1, ft);
-            gen_helper_float_maxa_s(tcg_ctx, fp1, tcg_ctx->cpu_env, fp0, fp1);
+            gen_helper_float_maxa_s(tcg_ctx, fp1, uc->cpu_env, fp0, fp1);
             gen_store_fpr32(ctx, fp1, fd);
             tcg_temp_free_i32(tcg_ctx, fp1);
             tcg_temp_free_i32(tcg_ctx, fp0);
@@ -9531,7 +9552,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
 
                 gen_load_fpr32(ctx, fp0, fs);
                 gen_load_fpr32(ctx, fp1, ft);
-                gen_helper_float_rsqrt2_s(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0, fp1);
+                gen_helper_float_rsqrt2_s(tcg_ctx, fp0, uc->cpu_env, fp0, fp1);
                 tcg_temp_free_i32(tcg_ctx, fp1);
                 gen_store_fpr32(ctx, fp0, fd);
                 tcg_temp_free_i32(tcg_ctx, fp0);
@@ -9545,7 +9566,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
             TCGv_i64 fp64 = tcg_temp_new_i64(tcg_ctx);
 
             gen_load_fpr32(ctx, fp32, fs);
-            gen_helper_float_cvtd_s(tcg_ctx, fp64, tcg_ctx->cpu_env, fp32);
+            gen_helper_float_cvtd_s(tcg_ctx, fp64, uc->cpu_env, fp32);
             tcg_temp_free_i32(tcg_ctx, fp32);
             gen_store_fpr64(ctx, fp64, fd);
             tcg_temp_free_i64(tcg_ctx, fp64);
@@ -9557,9 +9578,9 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
 
             gen_load_fpr32(ctx, fp0, fs);
             if (ctx->nan2008) {
-                gen_helper_float_cvt_2008_w_s(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0);
+                gen_helper_float_cvt_2008_w_s(tcg_ctx, fp0, uc->cpu_env, fp0);
             } else {
-                gen_helper_float_cvt_w_s(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0);
+                gen_helper_float_cvt_w_s(tcg_ctx, fp0, uc->cpu_env, fp0);
             }
             gen_store_fpr32(ctx, fp0, fd);
             tcg_temp_free_i32(tcg_ctx, fp0);
@@ -9573,9 +9594,9 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
 
             gen_load_fpr32(ctx, fp32, fs);
             if (ctx->nan2008) {
-                gen_helper_float_cvt_2008_l_s(tcg_ctx, fp64, tcg_ctx->cpu_env, fp32);
+                gen_helper_float_cvt_2008_l_s(tcg_ctx, fp64, uc->cpu_env, fp32);
             } else {
-                gen_helper_float_cvt_l_s(tcg_ctx, fp64, tcg_ctx->cpu_env, fp32);
+                gen_helper_float_cvt_l_s(tcg_ctx, fp64, uc->cpu_env, fp32);
             }
             tcg_temp_free_i32(tcg_ctx, fp32);
             gen_store_fpr64(ctx, fp64, fd);
@@ -9629,7 +9650,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
 
             gen_load_fpr64(ctx, fp0, fs);
             gen_load_fpr64(ctx, fp1, ft);
-            gen_helper_float_add_d(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0, fp1);
+            gen_helper_float_add_d(tcg_ctx, fp0, uc->cpu_env, fp0, fp1);
             tcg_temp_free_i64(tcg_ctx, fp1);
             gen_store_fpr64(ctx, fp0, fd);
             tcg_temp_free_i64(tcg_ctx, fp0);
@@ -9643,7 +9664,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
 
             gen_load_fpr64(ctx, fp0, fs);
             gen_load_fpr64(ctx, fp1, ft);
-            gen_helper_float_sub_d(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0, fp1);
+            gen_helper_float_sub_d(tcg_ctx, fp0, uc->cpu_env, fp0, fp1);
             tcg_temp_free_i64(tcg_ctx, fp1);
             gen_store_fpr64(ctx, fp0, fd);
             tcg_temp_free_i64(tcg_ctx, fp0);
@@ -9657,7 +9678,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
 
             gen_load_fpr64(ctx, fp0, fs);
             gen_load_fpr64(ctx, fp1, ft);
-            gen_helper_float_mul_d(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0, fp1);
+            gen_helper_float_mul_d(tcg_ctx, fp0, uc->cpu_env, fp0, fp1);
             tcg_temp_free_i64(tcg_ctx, fp1);
             gen_store_fpr64(ctx, fp0, fd);
             tcg_temp_free_i64(tcg_ctx, fp0);
@@ -9671,7 +9692,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
 
             gen_load_fpr64(ctx, fp0, fs);
             gen_load_fpr64(ctx, fp1, ft);
-            gen_helper_float_div_d(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0, fp1);
+            gen_helper_float_div_d(tcg_ctx, fp0, uc->cpu_env, fp0, fp1);
             tcg_temp_free_i64(tcg_ctx, fp1);
             gen_store_fpr64(ctx, fp0, fd);
             tcg_temp_free_i64(tcg_ctx, fp0);
@@ -9683,7 +9704,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
             TCGv_i64 fp0 = tcg_temp_new_i64(tcg_ctx);
 
             gen_load_fpr64(ctx, fp0, fs);
-            gen_helper_float_sqrt_d(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0);
+            gen_helper_float_sqrt_d(tcg_ctx, fp0, uc->cpu_env, fp0);
             gen_store_fpr64(ctx, fp0, fd);
             tcg_temp_free_i64(tcg_ctx, fp0);
         }
@@ -9735,9 +9756,9 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
 
             gen_load_fpr64(ctx, fp0, fs);
             if (ctx->nan2008) {
-                gen_helper_float_round_2008_l_d(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0);
+                gen_helper_float_round_2008_l_d(tcg_ctx, fp0, uc->cpu_env, fp0);
             } else {
-                gen_helper_float_round_l_d(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0);
+                gen_helper_float_round_l_d(tcg_ctx, fp0, uc->cpu_env, fp0);
             }
             gen_store_fpr64(ctx, fp0, fd);
             tcg_temp_free_i64(tcg_ctx, fp0);
@@ -9750,9 +9771,9 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
 
             gen_load_fpr64(ctx, fp0, fs);
             if (ctx->nan2008) {
-                gen_helper_float_trunc_2008_l_d(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0);
+                gen_helper_float_trunc_2008_l_d(tcg_ctx, fp0, uc->cpu_env, fp0);
             } else {
-                gen_helper_float_trunc_l_d(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0);
+                gen_helper_float_trunc_l_d(tcg_ctx, fp0, uc->cpu_env, fp0);
             }
             gen_store_fpr64(ctx, fp0, fd);
             tcg_temp_free_i64(tcg_ctx, fp0);
@@ -9765,9 +9786,9 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
 
             gen_load_fpr64(ctx, fp0, fs);
             if (ctx->nan2008) {
-                gen_helper_float_ceil_2008_l_d(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0);
+                gen_helper_float_ceil_2008_l_d(tcg_ctx, fp0, uc->cpu_env, fp0);
             } else {
-                gen_helper_float_ceil_l_d(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0);
+                gen_helper_float_ceil_l_d(tcg_ctx, fp0, uc->cpu_env, fp0);
             }
             gen_store_fpr64(ctx, fp0, fd);
             tcg_temp_free_i64(tcg_ctx, fp0);
@@ -9780,9 +9801,9 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
 
             gen_load_fpr64(ctx, fp0, fs);
             if (ctx->nan2008) {
-                gen_helper_float_floor_2008_l_d(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0);
+                gen_helper_float_floor_2008_l_d(tcg_ctx, fp0, uc->cpu_env, fp0);
             } else {
-                gen_helper_float_floor_l_d(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0);
+                gen_helper_float_floor_l_d(tcg_ctx, fp0, uc->cpu_env, fp0);
             }
             gen_store_fpr64(ctx, fp0, fd);
             tcg_temp_free_i64(tcg_ctx, fp0);
@@ -9796,9 +9817,9 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
 
             gen_load_fpr64(ctx, fp64, fs);
             if (ctx->nan2008) {
-                gen_helper_float_round_2008_w_d(tcg_ctx, fp32, tcg_ctx->cpu_env, fp64);
+                gen_helper_float_round_2008_w_d(tcg_ctx, fp32, uc->cpu_env, fp64);
             } else {
-                gen_helper_float_round_w_d(tcg_ctx, fp32, tcg_ctx->cpu_env, fp64);
+                gen_helper_float_round_w_d(tcg_ctx, fp32, uc->cpu_env, fp64);
             }
             tcg_temp_free_i64(tcg_ctx, fp64);
             gen_store_fpr32(ctx, fp32, fd);
@@ -9813,9 +9834,9 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
 
             gen_load_fpr64(ctx, fp64, fs);
             if (ctx->nan2008) {
-                gen_helper_float_trunc_2008_w_d(tcg_ctx, fp32, tcg_ctx->cpu_env, fp64);
+                gen_helper_float_trunc_2008_w_d(tcg_ctx, fp32, uc->cpu_env, fp64);
             } else {
-                gen_helper_float_trunc_w_d(tcg_ctx, fp32, tcg_ctx->cpu_env, fp64);
+                gen_helper_float_trunc_w_d(tcg_ctx, fp32, uc->cpu_env, fp64);
             }
             tcg_temp_free_i64(tcg_ctx, fp64);
             gen_store_fpr32(ctx, fp32, fd);
@@ -9830,9 +9851,9 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
 
             gen_load_fpr64(ctx, fp64, fs);
             if (ctx->nan2008) {
-                gen_helper_float_ceil_2008_w_d(tcg_ctx, fp32, tcg_ctx->cpu_env, fp64);
+                gen_helper_float_ceil_2008_w_d(tcg_ctx, fp32, uc->cpu_env, fp64);
             } else {
-                gen_helper_float_ceil_w_d(tcg_ctx, fp32, tcg_ctx->cpu_env, fp64);
+                gen_helper_float_ceil_w_d(tcg_ctx, fp32, uc->cpu_env, fp64);
             }
             tcg_temp_free_i64(tcg_ctx, fp64);
             gen_store_fpr32(ctx, fp32, fd);
@@ -9847,9 +9868,9 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
 
             gen_load_fpr64(ctx, fp64, fs);
             if (ctx->nan2008) {
-                gen_helper_float_floor_2008_w_d(tcg_ctx, fp32, tcg_ctx->cpu_env, fp64);
+                gen_helper_float_floor_2008_w_d(tcg_ctx, fp32, uc->cpu_env, fp64);
             } else {
-                gen_helper_float_floor_w_d(tcg_ctx, fp32, tcg_ctx->cpu_env, fp64);
+                gen_helper_float_floor_w_d(tcg_ctx, fp32, uc->cpu_env, fp64);
             }
             tcg_temp_free_i64(tcg_ctx, fp64);
             gen_store_fpr32(ctx, fp32, fd);
@@ -9910,7 +9931,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
             TCGv_i64 fp0 = tcg_temp_new_i64(tcg_ctx);
 
             gen_load_fpr64(ctx, fp0, fs);
-            gen_helper_float_recip_d(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0);
+            gen_helper_float_recip_d(tcg_ctx, fp0, uc->cpu_env, fp0);
             gen_store_fpr64(ctx, fp0, fd);
             tcg_temp_free_i64(tcg_ctx, fp0);
         }
@@ -9921,7 +9942,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
             TCGv_i64 fp0 = tcg_temp_new_i64(tcg_ctx);
 
             gen_load_fpr64(ctx, fp0, fs);
-            gen_helper_float_rsqrt_d(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0);
+            gen_helper_float_rsqrt_d(tcg_ctx, fp0, uc->cpu_env, fp0);
             gen_store_fpr64(ctx, fp0, fd);
             tcg_temp_free_i64(tcg_ctx, fp0);
         }
@@ -9935,7 +9956,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
             gen_load_fpr64(ctx, fp0, fs);
             gen_load_fpr64(ctx, fp1, ft);
             gen_load_fpr64(ctx, fp2, fd);
-            gen_helper_float_maddf_d(tcg_ctx, fp2, tcg_ctx->cpu_env, fp0, fp1, fp2);
+            gen_helper_float_maddf_d(tcg_ctx, fp2, uc->cpu_env, fp0, fp1, fp2);
             gen_store_fpr64(ctx, fp2, fd);
             tcg_temp_free_i64(tcg_ctx, fp2);
             tcg_temp_free_i64(tcg_ctx, fp1);
@@ -9951,7 +9972,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
             gen_load_fpr64(ctx, fp0, fs);
             gen_load_fpr64(ctx, fp1, ft);
             gen_load_fpr64(ctx, fp2, fd);
-            gen_helper_float_msubf_d(tcg_ctx, fp2, tcg_ctx->cpu_env, fp0, fp1, fp2);
+            gen_helper_float_msubf_d(tcg_ctx, fp2, uc->cpu_env, fp0, fp1, fp2);
             gen_store_fpr64(ctx, fp2, fd);
             tcg_temp_free_i64(tcg_ctx, fp2);
             tcg_temp_free_i64(tcg_ctx, fp1);
@@ -9963,7 +9984,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
         {
             TCGv_i64 fp0 = tcg_temp_new_i64(tcg_ctx);
             gen_load_fpr64(ctx, fp0, fs);
-            gen_helper_float_rint_d(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0);
+            gen_helper_float_rint_d(tcg_ctx, fp0, uc->cpu_env, fp0);
             gen_store_fpr64(ctx, fp0, fd);
             tcg_temp_free_i64(tcg_ctx, fp0);
         }
@@ -9973,7 +9994,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
         {
             TCGv_i64 fp0 = tcg_temp_new_i64(tcg_ctx);
             gen_load_fpr64(ctx, fp0, fs);
-            gen_helper_float_class_d(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0);
+            gen_helper_float_class_d(tcg_ctx, fp0, uc->cpu_env, fp0);
             gen_store_fpr64(ctx, fp0, fd);
             tcg_temp_free_i64(tcg_ctx, fp0);
         }
@@ -9985,7 +10006,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
             TCGv_i64 fp1 = tcg_temp_new_i64(tcg_ctx);
             gen_load_fpr64(ctx, fp0, fs);
             gen_load_fpr64(ctx, fp1, ft);
-            gen_helper_float_min_d(tcg_ctx, fp1, tcg_ctx->cpu_env, fp0, fp1);
+            gen_helper_float_min_d(tcg_ctx, fp1, uc->cpu_env, fp0, fp1);
             gen_store_fpr64(ctx, fp1, fd);
             tcg_temp_free_i64(tcg_ctx, fp1);
             tcg_temp_free_i64(tcg_ctx, fp0);
@@ -9998,7 +10019,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
 
                 gen_load_fpr64(ctx, fp0, fs);
                 gen_load_fpr64(ctx, fp1, ft);
-                gen_helper_float_recip2_d(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0, fp1);
+                gen_helper_float_recip2_d(tcg_ctx, fp0, uc->cpu_env, fp0, fp1);
                 tcg_temp_free_i64(tcg_ctx, fp1);
                 gen_store_fpr64(ctx, fp0, fd);
                 tcg_temp_free_i64(tcg_ctx, fp0);
@@ -10012,7 +10033,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
             TCGv_i64 fp1 = tcg_temp_new_i64(tcg_ctx);
             gen_load_fpr64(ctx, fp0, fs);
             gen_load_fpr64(ctx, fp1, ft);
-            gen_helper_float_mina_d(tcg_ctx, fp1, tcg_ctx->cpu_env, fp0, fp1);
+            gen_helper_float_mina_d(tcg_ctx, fp1, uc->cpu_env, fp0, fp1);
             gen_store_fpr64(ctx, fp1, fd);
             tcg_temp_free_i64(tcg_ctx, fp1);
             tcg_temp_free_i64(tcg_ctx, fp0);
@@ -10023,7 +10044,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
                 TCGv_i64 fp0 = tcg_temp_new_i64(tcg_ctx);
 
                 gen_load_fpr64(ctx, fp0, fs);
-                gen_helper_float_recip1_d(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0);
+                gen_helper_float_recip1_d(tcg_ctx, fp0, uc->cpu_env, fp0);
                 gen_store_fpr64(ctx, fp0, fd);
                 tcg_temp_free_i64(tcg_ctx, fp0);
             }
@@ -10036,7 +10057,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
             TCGv_i64 fp1 = tcg_temp_new_i64(tcg_ctx);
             gen_load_fpr64(ctx, fp0, fs);
             gen_load_fpr64(ctx, fp1, ft);
-            gen_helper_float_max_d(tcg_ctx, fp1, tcg_ctx->cpu_env, fp0, fp1);
+            gen_helper_float_max_d(tcg_ctx, fp1, uc->cpu_env, fp0, fp1);
             gen_store_fpr64(ctx, fp1, fd);
             tcg_temp_free_i64(tcg_ctx, fp1);
             tcg_temp_free_i64(tcg_ctx, fp0);
@@ -10047,7 +10068,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
                 TCGv_i64 fp0 = tcg_temp_new_i64(tcg_ctx);
 
                 gen_load_fpr64(ctx, fp0, fs);
-                gen_helper_float_rsqrt1_d(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0);
+                gen_helper_float_rsqrt1_d(tcg_ctx, fp0, uc->cpu_env, fp0);
                 gen_store_fpr64(ctx, fp0, fd);
                 tcg_temp_free_i64(tcg_ctx, fp0);
             }
@@ -10060,7 +10081,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
             TCGv_i64 fp1 = tcg_temp_new_i64(tcg_ctx);
             gen_load_fpr64(ctx, fp0, fs);
             gen_load_fpr64(ctx, fp1, ft);
-            gen_helper_float_maxa_d(tcg_ctx, fp1, tcg_ctx->cpu_env, fp0, fp1);
+            gen_helper_float_maxa_d(tcg_ctx, fp1, uc->cpu_env, fp0, fp1);
             gen_store_fpr64(ctx, fp1, fd);
             tcg_temp_free_i64(tcg_ctx, fp1);
             tcg_temp_free_i64(tcg_ctx, fp0);
@@ -10073,7 +10094,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
 
                 gen_load_fpr64(ctx, fp0, fs);
                 gen_load_fpr64(ctx, fp1, ft);
-                gen_helper_float_rsqrt2_d(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0, fp1);
+                gen_helper_float_rsqrt2_d(tcg_ctx, fp0, uc->cpu_env, fp0, fp1);
                 tcg_temp_free_i64(tcg_ctx, fp1);
                 gen_store_fpr64(ctx, fp0, fd);
                 tcg_temp_free_i64(tcg_ctx, fp0);
@@ -10110,7 +10131,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
             TCGv_i64 fp64 = tcg_temp_new_i64(tcg_ctx);
 
             gen_load_fpr64(ctx, fp64, fs);
-            gen_helper_float_cvts_d(tcg_ctx, fp32, tcg_ctx->cpu_env, fp64);
+            gen_helper_float_cvts_d(tcg_ctx, fp32, uc->cpu_env, fp64);
             tcg_temp_free_i64(tcg_ctx, fp64);
             gen_store_fpr32(ctx, fp32, fd);
             tcg_temp_free_i32(tcg_ctx, fp32);
@@ -10124,9 +10145,9 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
 
             gen_load_fpr64(ctx, fp64, fs);
             if (ctx->nan2008) {
-                gen_helper_float_cvt_2008_w_d(tcg_ctx, fp32, tcg_ctx->cpu_env, fp64);
+                gen_helper_float_cvt_2008_w_d(tcg_ctx, fp32, uc->cpu_env, fp64);
             } else {
-                gen_helper_float_cvt_w_d(tcg_ctx, fp32, tcg_ctx->cpu_env, fp64);
+                gen_helper_float_cvt_w_d(tcg_ctx, fp32, uc->cpu_env, fp64);
             }
             tcg_temp_free_i64(tcg_ctx, fp64);
             gen_store_fpr32(ctx, fp32, fd);
@@ -10140,9 +10161,9 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
 
             gen_load_fpr64(ctx, fp0, fs);
             if (ctx->nan2008) {
-                gen_helper_float_cvt_2008_l_d(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0);
+                gen_helper_float_cvt_2008_l_d(tcg_ctx, fp0, uc->cpu_env, fp0);
             } else {
-                gen_helper_float_cvt_l_d(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0);
+                gen_helper_float_cvt_l_d(tcg_ctx, fp0, uc->cpu_env, fp0);
             }
             gen_store_fpr64(ctx, fp0, fd);
             tcg_temp_free_i64(tcg_ctx, fp0);
@@ -10153,7 +10174,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
             TCGv_i32 fp0 = tcg_temp_new_i32(tcg_ctx);
 
             gen_load_fpr32(ctx, fp0, fs);
-            gen_helper_float_cvts_w(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0);
+            gen_helper_float_cvts_w(tcg_ctx, fp0, uc->cpu_env, fp0);
             gen_store_fpr32(ctx, fp0, fd);
             tcg_temp_free_i32(tcg_ctx, fp0);
         }
@@ -10165,7 +10186,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
             TCGv_i64 fp64 = tcg_temp_new_i64(tcg_ctx);
 
             gen_load_fpr32(ctx, fp32, fs);
-            gen_helper_float_cvtd_w(tcg_ctx, fp64, tcg_ctx->cpu_env, fp32);
+            gen_helper_float_cvtd_w(tcg_ctx, fp64, uc->cpu_env, fp32);
             tcg_temp_free_i32(tcg_ctx, fp32);
             gen_store_fpr64(ctx, fp64, fd);
             tcg_temp_free_i64(tcg_ctx, fp64);
@@ -10178,7 +10199,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
             TCGv_i64 fp64 = tcg_temp_new_i64(tcg_ctx);
 
             gen_load_fpr64(ctx, fp64, fs);
-            gen_helper_float_cvts_l(tcg_ctx, fp32, tcg_ctx->cpu_env, fp64);
+            gen_helper_float_cvts_l(tcg_ctx, fp32, uc->cpu_env, fp64);
             tcg_temp_free_i64(tcg_ctx, fp64);
             gen_store_fpr32(ctx, fp32, fd);
             tcg_temp_free_i32(tcg_ctx, fp32);
@@ -10190,7 +10211,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
             TCGv_i64 fp0 = tcg_temp_new_i64(tcg_ctx);
 
             gen_load_fpr64(ctx, fp0, fs);
-            gen_helper_float_cvtd_l(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0);
+            gen_helper_float_cvtd_l(tcg_ctx, fp0, uc->cpu_env, fp0);
             gen_store_fpr64(ctx, fp0, fd);
             tcg_temp_free_i64(tcg_ctx, fp0);
         }
@@ -10201,7 +10222,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
             TCGv_i64 fp0 = tcg_temp_new_i64(tcg_ctx);
 
             gen_load_fpr64(ctx, fp0, fs);
-            gen_helper_float_cvtps_pw(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0);
+            gen_helper_float_cvtps_pw(tcg_ctx, fp0, uc->cpu_env, fp0);
             gen_store_fpr64(ctx, fp0, fd);
             tcg_temp_free_i64(tcg_ctx, fp0);
         }
@@ -10214,7 +10235,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
 
             gen_load_fpr64(ctx, fp0, fs);
             gen_load_fpr64(ctx, fp1, ft);
-            gen_helper_float_add_ps(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0, fp1);
+            gen_helper_float_add_ps(tcg_ctx, fp0, uc->cpu_env, fp0, fp1);
             tcg_temp_free_i64(tcg_ctx, fp1);
             gen_store_fpr64(ctx, fp0, fd);
             tcg_temp_free_i64(tcg_ctx, fp0);
@@ -10228,7 +10249,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
 
             gen_load_fpr64(ctx, fp0, fs);
             gen_load_fpr64(ctx, fp1, ft);
-            gen_helper_float_sub_ps(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0, fp1);
+            gen_helper_float_sub_ps(tcg_ctx, fp0, uc->cpu_env, fp0, fp1);
             tcg_temp_free_i64(tcg_ctx, fp1);
             gen_store_fpr64(ctx, fp0, fd);
             tcg_temp_free_i64(tcg_ctx, fp0);
@@ -10242,7 +10263,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
 
             gen_load_fpr64(ctx, fp0, fs);
             gen_load_fpr64(ctx, fp1, ft);
-            gen_helper_float_mul_ps(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0, fp1);
+            gen_helper_float_mul_ps(tcg_ctx, fp0, uc->cpu_env, fp0, fp1);
             tcg_temp_free_i64(tcg_ctx, fp1);
             gen_store_fpr64(ctx, fp0, fd);
             tcg_temp_free_i64(tcg_ctx, fp0);
@@ -10323,7 +10344,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
 
             gen_load_fpr64(ctx, fp0, ft);
             gen_load_fpr64(ctx, fp1, fs);
-            gen_helper_float_addr_ps(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0, fp1);
+            gen_helper_float_addr_ps(tcg_ctx, fp0, uc->cpu_env, fp0, fp1);
             tcg_temp_free_i64(tcg_ctx, fp1);
             gen_store_fpr64(ctx, fp0, fd);
             tcg_temp_free_i64(tcg_ctx, fp0);
@@ -10337,7 +10358,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
 
             gen_load_fpr64(ctx, fp0, ft);
             gen_load_fpr64(ctx, fp1, fs);
-            gen_helper_float_mulr_ps(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0, fp1);
+            gen_helper_float_mulr_ps(tcg_ctx, fp0, uc->cpu_env, fp0, fp1);
             tcg_temp_free_i64(tcg_ctx, fp1);
             gen_store_fpr64(ctx, fp0, fd);
             tcg_temp_free_i64(tcg_ctx, fp0);
@@ -10351,7 +10372,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
 
             gen_load_fpr64(ctx, fp0, fs);
             gen_load_fpr64(ctx, fp1, ft);
-            gen_helper_float_recip2_ps(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0, fp1);
+            gen_helper_float_recip2_ps(tcg_ctx, fp0, uc->cpu_env, fp0, fp1);
             tcg_temp_free_i64(tcg_ctx, fp1);
             gen_store_fpr64(ctx, fp0, fd);
             tcg_temp_free_i64(tcg_ctx, fp0);
@@ -10363,7 +10384,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
             TCGv_i64 fp0 = tcg_temp_new_i64(tcg_ctx);
 
             gen_load_fpr64(ctx, fp0, fs);
-            gen_helper_float_recip1_ps(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0);
+            gen_helper_float_recip1_ps(tcg_ctx, fp0, uc->cpu_env, fp0);
             gen_store_fpr64(ctx, fp0, fd);
             tcg_temp_free_i64(tcg_ctx, fp0);
         }
@@ -10374,7 +10395,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
             TCGv_i64 fp0 = tcg_temp_new_i64(tcg_ctx);
 
             gen_load_fpr64(ctx, fp0, fs);
-            gen_helper_float_rsqrt1_ps(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0);
+            gen_helper_float_rsqrt1_ps(tcg_ctx, fp0, uc->cpu_env, fp0);
             gen_store_fpr64(ctx, fp0, fd);
             tcg_temp_free_i64(tcg_ctx, fp0);
         }
@@ -10387,7 +10408,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
 
             gen_load_fpr64(ctx, fp0, fs);
             gen_load_fpr64(ctx, fp1, ft);
-            gen_helper_float_rsqrt2_ps(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0, fp1);
+            gen_helper_float_rsqrt2_ps(tcg_ctx, fp0, uc->cpu_env, fp0, fp1);
             tcg_temp_free_i64(tcg_ctx, fp1);
             gen_store_fpr64(ctx, fp0, fd);
             tcg_temp_free_i64(tcg_ctx, fp0);
@@ -10399,7 +10420,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
             TCGv_i32 fp0 = tcg_temp_new_i32(tcg_ctx);
 
             gen_load_fpr32h(ctx, fp0, fs);
-            gen_helper_float_cvts_pu(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0);
+            gen_helper_float_cvts_pu(tcg_ctx, fp0, uc->cpu_env, fp0);
             gen_store_fpr32(ctx, fp0, fd);
             tcg_temp_free_i32(tcg_ctx, fp0);
         }
@@ -10410,7 +10431,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
             TCGv_i64 fp0 = tcg_temp_new_i64(tcg_ctx);
 
             gen_load_fpr64(ctx, fp0, fs);
-            gen_helper_float_cvtpw_ps(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0);
+            gen_helper_float_cvtpw_ps(tcg_ctx, fp0, uc->cpu_env, fp0);
             gen_store_fpr64(ctx, fp0, fd);
             tcg_temp_free_i64(tcg_ctx, fp0);
         }
@@ -10421,7 +10442,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
             TCGv_i32 fp0 = tcg_temp_new_i32(tcg_ctx);
 
             gen_load_fpr32(ctx, fp0, fs);
-            gen_helper_float_cvts_pl(tcg_ctx, fp0, tcg_ctx->cpu_env, fp0);
+            gen_helper_float_cvts_pl(tcg_ctx, fp0, uc->cpu_env, fp0);
             gen_store_fpr32(ctx, fp0, fd);
             tcg_temp_free_i32(tcg_ctx, fp0);
         }
@@ -10597,7 +10618,8 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc,
 static void gen_flt3_arith (DisasContext *ctx, uint32_t opc,
                             int fd, int fr, int fs, int ft)
 {
-    TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
+    struct uc_struct *uc = ctx->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
 
     switch (opc) {
     case OPC_ALNV_PS:
@@ -10647,7 +10669,7 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc,
             gen_load_fpr32(ctx, fp0, fs);
             gen_load_fpr32(ctx, fp1, ft);
             gen_load_fpr32(ctx, fp2, fr);
-            gen_helper_float_madd_s(tcg_ctx, fp2, tcg_ctx->cpu_env, fp0, fp1, fp2);
+            gen_helper_float_madd_s(tcg_ctx, fp2, uc->cpu_env, fp0, fp1, fp2);
             tcg_temp_free_i32(tcg_ctx, fp0);
             tcg_temp_free_i32(tcg_ctx, fp1);
             gen_store_fpr32(ctx, fp2, fd);
@@ -10665,7 +10687,7 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc,
             gen_load_fpr64(ctx, fp0, fs);
             gen_load_fpr64(ctx, fp1, ft);
             gen_load_fpr64(ctx, fp2, fr);
-            gen_helper_float_madd_d(tcg_ctx, fp2, tcg_ctx->cpu_env, fp0, fp1, fp2);
+            gen_helper_float_madd_d(tcg_ctx, fp2, uc->cpu_env, fp0, fp1, fp2);
             tcg_temp_free_i64(tcg_ctx, fp0);
             tcg_temp_free_i64(tcg_ctx, fp1);
             gen_store_fpr64(ctx, fp2, fd);
@@ -10682,7 +10704,7 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc,
             gen_load_fpr64(ctx, fp0, fs);
             gen_load_fpr64(ctx, fp1, ft);
             gen_load_fpr64(ctx, fp2, fr);
-            gen_helper_float_madd_ps(tcg_ctx, fp2, tcg_ctx->cpu_env, fp0, fp1, fp2);
+            gen_helper_float_madd_ps(tcg_ctx, fp2, uc->cpu_env, fp0, fp1, fp2);
             tcg_temp_free_i64(tcg_ctx, fp0);
             tcg_temp_free_i64(tcg_ctx, fp1);
             gen_store_fpr64(ctx, fp2, fd);
@@ -10699,7 +10721,7 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc,
             gen_load_fpr32(ctx, fp0, fs);
             gen_load_fpr32(ctx, fp1, ft);
             gen_load_fpr32(ctx, fp2, fr);
-            gen_helper_float_msub_s(tcg_ctx, fp2, tcg_ctx->cpu_env, fp0, fp1, fp2);
+            gen_helper_float_msub_s(tcg_ctx, fp2, uc->cpu_env, fp0, fp1, fp2);
             tcg_temp_free_i32(tcg_ctx, fp0);
             tcg_temp_free_i32(tcg_ctx, fp1);
             gen_store_fpr32(ctx, fp2, fd);
@@ -10717,7 +10739,7 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc,
             gen_load_fpr64(ctx, fp0, fs);
             gen_load_fpr64(ctx, fp1, ft);
             gen_load_fpr64(ctx, fp2, fr);
-            gen_helper_float_msub_d(tcg_ctx, fp2, tcg_ctx->cpu_env, fp0, fp1, fp2);
+            gen_helper_float_msub_d(tcg_ctx, fp2, uc->cpu_env, fp0, fp1, fp2);
             tcg_temp_free_i64(tcg_ctx, fp0);
             tcg_temp_free_i64(tcg_ctx, fp1);
             gen_store_fpr64(ctx, fp2, fd);
@@ -10734,7 +10756,7 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc,
             gen_load_fpr64(ctx, fp0, fs);
             gen_load_fpr64(ctx, fp1, ft);
             gen_load_fpr64(ctx, fp2, fr);
-            gen_helper_float_msub_ps(tcg_ctx, fp2, tcg_ctx->cpu_env, fp0, fp1, fp2);
+            gen_helper_float_msub_ps(tcg_ctx, fp2, uc->cpu_env, fp0, fp1, fp2);
             tcg_temp_free_i64(tcg_ctx, fp0);
             tcg_temp_free_i64(tcg_ctx, fp1);
             gen_store_fpr64(ctx, fp2, fd);
@@ -10751,7 +10773,7 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc,
             gen_load_fpr32(ctx, fp0, fs);
             gen_load_fpr32(ctx, fp1, ft);
             gen_load_fpr32(ctx, fp2, fr);
-            gen_helper_float_nmadd_s(tcg_ctx, fp2, tcg_ctx->cpu_env, fp0, fp1, fp2);
+            gen_helper_float_nmadd_s(tcg_ctx, fp2, uc->cpu_env, fp0, fp1, fp2);
             tcg_temp_free_i32(tcg_ctx, fp0);
             tcg_temp_free_i32(tcg_ctx, fp1);
             gen_store_fpr32(ctx, fp2, fd);
@@ -10769,7 +10791,7 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc,
             gen_load_fpr64(ctx, fp0, fs);
             gen_load_fpr64(ctx, fp1, ft);
             gen_load_fpr64(ctx, fp2, fr);
-            gen_helper_float_nmadd_d(tcg_ctx, fp2, tcg_ctx->cpu_env, fp0, fp1, fp2);
+            gen_helper_float_nmadd_d(tcg_ctx, fp2, uc->cpu_env, fp0, fp1, fp2);
             tcg_temp_free_i64(tcg_ctx, fp0);
             tcg_temp_free_i64(tcg_ctx, fp1);
             gen_store_fpr64(ctx, fp2, fd);
@@ -10786,7 +10808,7 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc,
             gen_load_fpr64(ctx, fp0, fs);
             gen_load_fpr64(ctx, fp1, ft);
             gen_load_fpr64(ctx, fp2, fr);
-            gen_helper_float_nmadd_ps(tcg_ctx, fp2, tcg_ctx->cpu_env, fp0, fp1, fp2);
+            gen_helper_float_nmadd_ps(tcg_ctx, fp2, uc->cpu_env, fp0, fp1, fp2);
             tcg_temp_free_i64(tcg_ctx, fp0);
             tcg_temp_free_i64(tcg_ctx, fp1);
             gen_store_fpr64(ctx, fp2, fd);
@@ -10803,7 +10825,7 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc,
             gen_load_fpr32(ctx, fp0, fs);
             gen_load_fpr32(ctx, fp1, ft);
             gen_load_fpr32(ctx, fp2, fr);
-            gen_helper_float_nmsub_s(tcg_ctx, fp2, tcg_ctx->cpu_env, fp0, fp1, fp2);
+            gen_helper_float_nmsub_s(tcg_ctx, fp2, uc->cpu_env, fp0, fp1, fp2);
             tcg_temp_free_i32(tcg_ctx, fp0);
             tcg_temp_free_i32(tcg_ctx, fp1);
             gen_store_fpr32(ctx, fp2, fd);
@@ -10821,7 +10843,7 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc,
             gen_load_fpr64(ctx, fp0, fs);
             gen_load_fpr64(ctx, fp1, ft);
             gen_load_fpr64(ctx, fp2, fr);
-            gen_helper_float_nmsub_d(tcg_ctx, fp2, tcg_ctx->cpu_env, fp0, fp1, fp2);
+            gen_helper_float_nmsub_d(tcg_ctx, fp2, uc->cpu_env, fp0, fp1, fp2);
             tcg_temp_free_i64(tcg_ctx, fp0);
             tcg_temp_free_i64(tcg_ctx, fp1);
             gen_store_fpr64(ctx, fp2, fd);
@@ -10838,7 +10860,7 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc,
             gen_load_fpr64(ctx, fp0, fs);
             gen_load_fpr64(ctx, fp1, ft);
             gen_load_fpr64(ctx, fp2, fr);
-            gen_helper_float_nmsub_ps(tcg_ctx, fp2, tcg_ctx->cpu_env, fp0, fp1, fp2);
+            gen_helper_float_nmsub_ps(tcg_ctx, fp2, uc->cpu_env, fp0, fp1, fp2);
             tcg_temp_free_i64(tcg_ctx, fp0);
             tcg_temp_free_i64(tcg_ctx, fp1);
             gen_store_fpr64(ctx, fp2, fd);
@@ -10854,7 +10876,8 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc,
 
 static void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel)
 {
-    TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
+    struct uc_struct *uc = ctx->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv t0;
 
 #if !defined(CONFIG_USER_ONLY)
@@ -10866,11 +10889,11 @@ static void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel)
 
     switch (rd) {
     case 0:
-        gen_helper_rdhwr_cpunum(tcg_ctx, t0, tcg_ctx->cpu_env);
+        gen_helper_rdhwr_cpunum(tcg_ctx, t0, uc->cpu_env);
         gen_store_gpr(tcg_ctx, t0, rt);
         break;
     case 1:
-        gen_helper_rdhwr_synci_step(tcg_ctx, t0, tcg_ctx->cpu_env);
+        gen_helper_rdhwr_synci_step(tcg_ctx, t0, uc->cpu_env);
         gen_store_gpr(tcg_ctx, t0, rt);
         break;
     case 2:
@@ -10880,7 +10903,7 @@ static void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel)
             gen_io_start();
         }
 #endif
-        gen_helper_rdhwr_cc(tcg_ctx, t0, tcg_ctx->cpu_env);
+        gen_helper_rdhwr_cc(tcg_ctx, t0, uc->cpu_env);
 #if 0
         if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) {
             gen_io_end();
@@ -10894,7 +10917,7 @@ static void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel)
         ctx->bstate = BS_EXCP;
         break;
     case 3:
-        gen_helper_rdhwr_ccres(tcg_ctx, t0, tcg_ctx->cpu_env);
+        gen_helper_rdhwr_ccres(tcg_ctx, t0, uc->cpu_env);
         gen_store_gpr(tcg_ctx, t0, rt);
         break;
     case 4:
@@ -10905,24 +10928,24 @@ static void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel)
              */
             generate_exception(ctx, EXCP_RI);
         }
-        gen_helper_rdhwr_performance(tcg_ctx, t0, tcg_ctx->cpu_env);
+        gen_helper_rdhwr_performance(tcg_ctx, t0, uc->cpu_env);
         gen_store_gpr(tcg_ctx, t0, rt);
         break;
     case 5:
         check_insn(ctx, ISA_MIPS32R6);
-        gen_helper_rdhwr_xnp(tcg_ctx, t0, tcg_ctx->cpu_env);
+        gen_helper_rdhwr_xnp(tcg_ctx, t0, uc->cpu_env);
         gen_store_gpr(tcg_ctx, t0, rt);
         break;
     case 29:
 #if defined(CONFIG_USER_ONLY)
-        tcg_gen_ld_tl(tcg_ctx, t0, tcg_ctx->cpu_env,
+        tcg_gen_ld_tl(tcg_ctx, t0, uc->cpu_env,
                       offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
         gen_store_gpr(tcg_ctx, t0, rt);
         break;
 #else
         if ((ctx->hflags & MIPS_HFLAG_CP0) ||
             (ctx->hflags & MIPS_HFLAG_HWRENA_ULR)) {
-            tcg_gen_ld_tl(tcg_ctx, t0, tcg_ctx->cpu_env,
+            tcg_gen_ld_tl(tcg_ctx, t0, uc->cpu_env,
                           offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
             gen_store_gpr(tcg_ctx, t0, rt);
         } else {
@@ -10953,7 +10976,9 @@ static inline void clear_branch_hflags(DisasContext *ctx)
 
 static void gen_branch(DisasContext *ctx, int insn_bytes)
 {
-    TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
+    struct uc_struct *uc = ctx->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
+
     if (ctx->hflags & MIPS_HFLAG_BMASK) {
         int proc_hflags = ctx->hflags & MIPS_HFLAG_BMASK;
         /* Branches completion */
@@ -11006,7 +11031,7 @@ static void gen_branch(DisasContext *ctx, int insn_bytes)
             }
             if (ctx->singlestep_enabled) {
                 save_cpu_state(ctx, 0);
-                gen_helper_raise_exception_debug(tcg_ctx, tcg_ctx->cpu_env);
+                gen_helper_raise_exception_debug(tcg_ctx, uc->cpu_env);
             }
             tcg_gen_lookup_and_goto_ptr(tcg_ctx);
             break;
@@ -11669,11 +11694,12 @@ static void gen_addiupc (DisasContext *ctx, int rx, int imm,
 static void gen_cache_operation(DisasContext *ctx, uint32_t op, int base,
                                 int16_t offset)
 {
-    TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
+    struct uc_struct *uc = ctx->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv_i32 t0 = tcg_const_i32(tcg_ctx, op);
     TCGv t1 = tcg_temp_new(tcg_ctx);
     gen_base_offset_addr(ctx, t1, base, offset);
-    gen_helper_cache(tcg_ctx, tcg_ctx->cpu_env, t1, t0);
+    gen_helper_cache(tcg_ctx, uc->cpu_env, t1, t0);
 }
 
 #if defined(TARGET_MIPS64)
@@ -13081,7 +13107,8 @@ static void gen_andi16(DisasContext *ctx)
 static void gen_ldst_multiple (DisasContext *ctx, uint32_t opc, int reglist,
                                int base, int16_t offset)
 {
-    TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
+    struct uc_struct *uc = ctx->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv t0, t1;
     TCGv_i32 t2;
 
@@ -13100,17 +13127,17 @@ static void gen_ldst_multiple (DisasContext *ctx, uint32_t opc, int reglist,
     save_cpu_state(ctx, 1);
     switch (opc) {
     case LWM32:
-        gen_helper_lwm(tcg_ctx, tcg_ctx->cpu_env, t0, t1, t2);
+        gen_helper_lwm(tcg_ctx, uc->cpu_env, t0, t1, t2);
         break;
     case SWM32:
-        gen_helper_swm(tcg_ctx, tcg_ctx->cpu_env, t0, t1, t2);
+        gen_helper_swm(tcg_ctx, uc->cpu_env, t0, t1, t2);
         break;
 #ifdef TARGET_MIPS64
     case LDM:
-        gen_helper_ldm(tcg_ctx, tcg_ctx->cpu_env, t0, t1, t2);
+        gen_helper_ldm(tcg_ctx, uc->cpu_env, t0, t1, t2);
         break;
     case SDM:
-        gen_helper_sdm(tcg_ctx, tcg_ctx->cpu_env, t0, t1, t2);
+        gen_helper_sdm(tcg_ctx, uc->cpu_env, t0, t1, t2);
         break;
 #endif
     }
@@ -13461,7 +13488,8 @@ static void gen_sync(TCGContext *ctx, int stype)
 
 static void gen_pool32axf (CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
 {
-    TCGContext *tcg_ctx = env->uc->tcg_ctx;
+    struct uc_struct *uc = ctx->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv *cpu_gpr = tcg_ctx->cpu_gpr;
     int extension = (ctx->opcode >> 6) & 0x3f;
     int minor = (ctx->opcode >> 12) & 0xf;
@@ -13708,7 +13736,7 @@ static void gen_pool32axf (CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
                 TCGv t0 = tcg_temp_new(tcg_ctx);
 
                 save_cpu_state(ctx, 1);
-                gen_helper_di(tcg_ctx, t0, tcg_ctx->cpu_env);
+                gen_helper_di(tcg_ctx, t0, uc->cpu_env);
                 gen_store_gpr(tcg_ctx, t0, rs);
                 /* Stop translation as we may have switched the execution mode */
                 ctx->bstate = BS_STOP;
@@ -13721,7 +13749,7 @@ static void gen_pool32axf (CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
                 TCGv t0 = tcg_temp_new(tcg_ctx);
 
                 save_cpu_state(ctx, 1);
-                gen_helper_ei(tcg_ctx, t0, tcg_ctx->cpu_env);
+                gen_helper_ei(tcg_ctx, t0, uc->cpu_env);
                 gen_store_gpr(tcg_ctx, t0, rs);
                 /* BS_STOP isn't sufficient, we need to ensure we break out
                    of translated code to check for pending interrupts.  */
@@ -15728,7 +15756,8 @@ static void gen_mipsdsp_ld(DisasContext *ctx, uint32_t opc,
 static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2,
                               int ret, int v1, int v2)
 {
-    TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
+    struct uc_struct *uc = ctx->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv *cpu_gpr = tcg_ctx->cpu_gpr;
     TCGv v1_t;
     TCGv v2_t;
@@ -15791,15 +15820,15 @@ static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2,
         switch (op2) {
         case OPC_ABSQ_S_QB:
             check_dspr2(ctx);
-            gen_helper_absq_s_qb(tcg_ctx, cpu_gpr[ret], v2_t, tcg_ctx->cpu_env);
+            gen_helper_absq_s_qb(tcg_ctx, cpu_gpr[ret], v2_t, uc->cpu_env);
             break;
         case OPC_ABSQ_S_PH:
             check_dsp(ctx);
-            gen_helper_absq_s_ph(tcg_ctx, cpu_gpr[ret], v2_t, tcg_ctx->cpu_env);
+            gen_helper_absq_s_ph(tcg_ctx, cpu_gpr[ret], v2_t, uc->cpu_env);
             break;
         case OPC_ABSQ_S_W:
             check_dsp(ctx);
-            gen_helper_absq_s_w(tcg_ctx, cpu_gpr[ret], v2_t, tcg_ctx->cpu_env);
+            gen_helper_absq_s_w(tcg_ctx, cpu_gpr[ret], v2_t, uc->cpu_env);
             break;
         case OPC_PRECEQ_W_PHL:
             check_dsp(ctx);
@@ -15850,67 +15879,67 @@ static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2,
         switch (op2) {
         case OPC_ADDQ_PH:
             check_dsp(ctx);
-            gen_helper_addq_ph(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_addq_ph(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_ADDQ_S_PH:
             check_dsp(ctx);
-            gen_helper_addq_s_ph(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_addq_s_ph(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_ADDQ_S_W:
             check_dsp(ctx);
-            gen_helper_addq_s_w(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_addq_s_w(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_ADDU_QB:
             check_dsp(ctx);
-            gen_helper_addu_qb(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_addu_qb(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_ADDU_S_QB:
             check_dsp(ctx);
-            gen_helper_addu_s_qb(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_addu_s_qb(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_ADDU_PH:
             check_dspr2(ctx);
-            gen_helper_addu_ph(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_addu_ph(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_ADDU_S_PH:
             check_dspr2(ctx);
-            gen_helper_addu_s_ph(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_addu_s_ph(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_SUBQ_PH:
             check_dsp(ctx);
-            gen_helper_subq_ph(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_subq_ph(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_SUBQ_S_PH:
             check_dsp(ctx);
-            gen_helper_subq_s_ph(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_subq_s_ph(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_SUBQ_S_W:
             check_dsp(ctx);
-            gen_helper_subq_s_w(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_subq_s_w(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_SUBU_QB:
             check_dsp(ctx);
-            gen_helper_subu_qb(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_subu_qb(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_SUBU_S_QB:
             check_dsp(ctx);
-            gen_helper_subu_s_qb(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_subu_s_qb(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_SUBU_PH:
             check_dspr2(ctx);
-            gen_helper_subu_ph(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_subu_ph(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_SUBU_S_PH:
             check_dspr2(ctx);
-            gen_helper_subu_s_ph(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_subu_s_ph(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_ADDSC:
             check_dsp(ctx);
-            gen_helper_addsc(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_addsc(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_ADDWC:
             check_dsp(ctx);
-            gen_helper_addwc(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_addwc(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_MODSUB:
             check_dsp(ctx);
@@ -15956,11 +15985,11 @@ static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2,
             break;
         case OPC_PRECRQ_RS_PH_W:
             check_dsp(ctx);
-            gen_helper_precrq_rs_ph_w(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_precrq_rs_ph_w(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_PRECRQU_S_QB_PH:
             check_dsp(ctx);
-            gen_helper_precrqu_s_qb_ph(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_precrqu_s_qb_ph(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, uc->cpu_env);
             break;
         }
         break;
@@ -16025,15 +16054,15 @@ static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2,
             break;
         case OPC_ABSQ_S_OB:
             check_dspr2(ctx);
-            gen_helper_absq_s_ob(tcg_ctx, cpu_gpr[ret], v2_t, tcg_ctx->cpu_env);
+            gen_helper_absq_s_ob(tcg_ctx, cpu_gpr[ret], v2_t, uc->cpu_env);
             break;
         case OPC_ABSQ_S_PW:
             check_dsp(ctx);
-            gen_helper_absq_s_pw(tcg_ctx, cpu_gpr[ret], v2_t, tcg_ctx->cpu_env);
+            gen_helper_absq_s_pw(tcg_ctx, cpu_gpr[ret], v2_t, uc->cpu_env);
             break;
         case OPC_ABSQ_S_QH:
             check_dsp(ctx);
-            gen_helper_absq_s_qh(tcg_ctx, cpu_gpr[ret], v2_t, tcg_ctx->cpu_env);
+            gen_helper_absq_s_qh(tcg_ctx, cpu_gpr[ret], v2_t, uc->cpu_env);
             break;
         }
         break;
@@ -16045,35 +16074,35 @@ static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2,
             break;
         case OPC_SUBQ_PW:
             check_dsp(ctx);
-            gen_helper_subq_pw(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_subq_pw(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_SUBQ_S_PW:
             check_dsp(ctx);
-            gen_helper_subq_s_pw(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_subq_s_pw(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_SUBQ_QH:
             check_dsp(ctx);
-            gen_helper_subq_qh(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_subq_qh(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_SUBQ_S_QH:
             check_dsp(ctx);
-            gen_helper_subq_s_qh(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_subq_s_qh(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_SUBU_OB:
             check_dsp(ctx);
-            gen_helper_subu_ob(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_subu_ob(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_SUBU_S_OB:
             check_dsp(ctx);
-            gen_helper_subu_s_ob(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_subu_s_ob(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_SUBU_QH:
             check_dspr2(ctx);
-            gen_helper_subu_qh(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_subu_qh(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_SUBU_S_QH:
             check_dspr2(ctx);
-            gen_helper_subu_s_qh(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_subu_s_qh(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_SUBUH_OB:
             check_dspr2(ctx);
@@ -16085,35 +16114,35 @@ static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2,
             break;
         case OPC_ADDQ_PW:
             check_dsp(ctx);
-            gen_helper_addq_pw(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_addq_pw(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_ADDQ_S_PW:
             check_dsp(ctx);
-            gen_helper_addq_s_pw(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_addq_s_pw(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_ADDQ_QH:
             check_dsp(ctx);
-            gen_helper_addq_qh(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_addq_qh(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_ADDQ_S_QH:
             check_dsp(ctx);
-            gen_helper_addq_s_qh(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_addq_s_qh(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_ADDU_OB:
             check_dsp(ctx);
-            gen_helper_addu_ob(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_addu_ob(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_ADDU_S_OB:
             check_dsp(ctx);
-            gen_helper_addu_s_ob(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_addu_s_ob(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_ADDU_QH:
             check_dspr2(ctx);
-            gen_helper_addu_qh(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_addu_qh(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_ADDU_S_QH:
             check_dspr2(ctx);
-            gen_helper_addu_s_qh(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_addu_s_qh(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_ADDUH_OB:
             check_dspr2(ctx);
@@ -16161,11 +16190,11 @@ static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2,
             break;
         case OPC_PRECRQ_RS_QH_PW:
             check_dsp(ctx);
-            gen_helper_precrq_rs_qh_pw(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_precrq_rs_qh_pw(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_PRECRQU_S_OB_QH:
             check_dsp(ctx);
-            gen_helper_precrqu_s_ob_qh(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_precrqu_s_ob_qh(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, uc->cpu_env);
             break;
         }
         break;
@@ -16179,7 +16208,8 @@ static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2,
 static void gen_mipsdsp_shift(DisasContext *ctx, uint32_t opc,
                               int ret, int v1, int v2)
 {
-    TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
+    struct uc_struct *uc = ctx->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv *cpu_gpr = tcg_ctx->cpu_gpr;
     uint32_t op2;
     TCGv t0;
@@ -16206,35 +16236,35 @@ static void gen_mipsdsp_shift(DisasContext *ctx, uint32_t opc,
             switch (op2) {
             case OPC_SHLL_QB:
                 check_dsp(ctx);
-                gen_helper_shll_qb(tcg_ctx, cpu_gpr[ret], t0, v2_t, tcg_ctx->cpu_env);
+                gen_helper_shll_qb(tcg_ctx, cpu_gpr[ret], t0, v2_t, uc->cpu_env);
                 break;
             case OPC_SHLLV_QB:
                 check_dsp(ctx);
-                gen_helper_shll_qb(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
+                gen_helper_shll_qb(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, uc->cpu_env);
                 break;
             case OPC_SHLL_PH:
                 check_dsp(ctx);
-                gen_helper_shll_ph(tcg_ctx, cpu_gpr[ret], t0, v2_t, tcg_ctx->cpu_env);
+                gen_helper_shll_ph(tcg_ctx, cpu_gpr[ret], t0, v2_t, uc->cpu_env);
                 break;
             case OPC_SHLLV_PH:
                 check_dsp(ctx);
-                gen_helper_shll_ph(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
+                gen_helper_shll_ph(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, uc->cpu_env);
                 break;
             case OPC_SHLL_S_PH:
                 check_dsp(ctx);
-                gen_helper_shll_s_ph(tcg_ctx, cpu_gpr[ret], t0, v2_t, tcg_ctx->cpu_env);
+                gen_helper_shll_s_ph(tcg_ctx, cpu_gpr[ret], t0, v2_t, uc->cpu_env);
                 break;
             case OPC_SHLLV_S_PH:
                 check_dsp(ctx);
-                gen_helper_shll_s_ph(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
+                gen_helper_shll_s_ph(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, uc->cpu_env);
                 break;
             case OPC_SHLL_S_W:
                 check_dsp(ctx);
-                gen_helper_shll_s_w(tcg_ctx, cpu_gpr[ret], t0, v2_t, tcg_ctx->cpu_env);
+                gen_helper_shll_s_w(tcg_ctx, cpu_gpr[ret], t0, v2_t, uc->cpu_env);
                 break;
             case OPC_SHLLV_S_W:
                 check_dsp(ctx);
-                gen_helper_shll_s_w(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
+                gen_helper_shll_s_w(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, uc->cpu_env);
                 break;
             case OPC_SHRL_QB:
                 check_dsp(ctx);
@@ -16305,43 +16335,43 @@ static void gen_mipsdsp_shift(DisasContext *ctx, uint32_t opc,
         switch (op2) {
         case OPC_SHLL_PW:
             check_dsp(ctx);
-            gen_helper_shll_pw(tcg_ctx, cpu_gpr[ret], v2_t, t0, tcg_ctx->cpu_env);
+            gen_helper_shll_pw(tcg_ctx, cpu_gpr[ret], v2_t, t0, uc->cpu_env);
             break;
         case OPC_SHLLV_PW:
             check_dsp(ctx);
-            gen_helper_shll_pw(tcg_ctx, cpu_gpr[ret], v2_t, v1_t, tcg_ctx->cpu_env);
+            gen_helper_shll_pw(tcg_ctx, cpu_gpr[ret], v2_t, v1_t, uc->cpu_env);
             break;
         case OPC_SHLL_S_PW:
             check_dsp(ctx);
-            gen_helper_shll_s_pw(tcg_ctx, cpu_gpr[ret], v2_t, t0, tcg_ctx->cpu_env);
+            gen_helper_shll_s_pw(tcg_ctx, cpu_gpr[ret], v2_t, t0, uc->cpu_env);
             break;
         case OPC_SHLLV_S_PW:
             check_dsp(ctx);
-            gen_helper_shll_s_pw(tcg_ctx, cpu_gpr[ret], v2_t, v1_t, tcg_ctx->cpu_env);
+            gen_helper_shll_s_pw(tcg_ctx, cpu_gpr[ret], v2_t, v1_t, uc->cpu_env);
             break;
         case OPC_SHLL_OB:
             check_dsp(ctx);
-            gen_helper_shll_ob(tcg_ctx, cpu_gpr[ret], v2_t, t0, tcg_ctx->cpu_env);
+            gen_helper_shll_ob(tcg_ctx, cpu_gpr[ret], v2_t, t0, uc->cpu_env);
             break;
         case OPC_SHLLV_OB:
             check_dsp(ctx);
-            gen_helper_shll_ob(tcg_ctx, cpu_gpr[ret], v2_t, v1_t, tcg_ctx->cpu_env);
+            gen_helper_shll_ob(tcg_ctx, cpu_gpr[ret], v2_t, v1_t, uc->cpu_env);
             break;
         case OPC_SHLL_QH:
             check_dsp(ctx);
-            gen_helper_shll_qh(tcg_ctx, cpu_gpr[ret], v2_t, t0, tcg_ctx->cpu_env);
+            gen_helper_shll_qh(tcg_ctx, cpu_gpr[ret], v2_t, t0, uc->cpu_env);
             break;
         case OPC_SHLLV_QH:
             check_dsp(ctx);
-            gen_helper_shll_qh(tcg_ctx, cpu_gpr[ret], v2_t, v1_t, tcg_ctx->cpu_env);
+            gen_helper_shll_qh(tcg_ctx, cpu_gpr[ret], v2_t, v1_t, uc->cpu_env);
             break;
         case OPC_SHLL_S_QH:
             check_dsp(ctx);
-            gen_helper_shll_s_qh(tcg_ctx, cpu_gpr[ret], v2_t, t0, tcg_ctx->cpu_env);
+            gen_helper_shll_s_qh(tcg_ctx, cpu_gpr[ret], v2_t, t0, uc->cpu_env);
             break;
         case OPC_SHLLV_S_QH:
             check_dsp(ctx);
-            gen_helper_shll_s_qh(tcg_ctx, cpu_gpr[ret], v2_t, v1_t, tcg_ctx->cpu_env);
+            gen_helper_shll_s_qh(tcg_ctx, cpu_gpr[ret], v2_t, v1_t, uc->cpu_env);
             break;
         case OPC_SHRA_OB:
             check_dspr2(ctx);
@@ -16424,7 +16454,8 @@ static void gen_mipsdsp_shift(DisasContext *ctx, uint32_t opc,
 static void gen_mipsdsp_multiply(DisasContext *ctx, uint32_t op1, uint32_t op2,
                                  int ret, int v1, int v2, int check_ret)
 {
-    TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
+    struct uc_struct *uc = ctx->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv *cpu_gpr = tcg_ctx->cpu_gpr;
     TCGv_i32 t0;
     TCGv v1_t;
@@ -16450,16 +16481,16 @@ static void gen_mipsdsp_multiply(DisasContext *ctx, uint32_t op1, uint32_t op2,
         check_dspr2(ctx);
         switch (op2) {
         case  OPC_MUL_PH:
-            gen_helper_mul_ph(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_mul_ph(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, uc->cpu_env);
             break;
         case  OPC_MUL_S_PH:
-            gen_helper_mul_s_ph(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_mul_s_ph(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_MULQ_S_W:
-            gen_helper_mulq_s_w(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_mulq_s_w(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_MULQ_RS_W:
-            gen_helper_mulq_rs_w(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_mulq_rs_w(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, uc->cpu_env);
             break;
         }
         break;
@@ -16467,91 +16498,91 @@ static void gen_mipsdsp_multiply(DisasContext *ctx, uint32_t op1, uint32_t op2,
         switch (op2) {
         case OPC_DPAU_H_QBL:
             check_dsp(ctx);
-            gen_helper_dpau_h_qbl(tcg_ctx, t0, v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_dpau_h_qbl(tcg_ctx, t0, v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_DPAU_H_QBR:
             check_dsp(ctx);
-            gen_helper_dpau_h_qbr(tcg_ctx, t0, v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_dpau_h_qbr(tcg_ctx, t0, v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_DPSU_H_QBL:
             check_dsp(ctx);
-            gen_helper_dpsu_h_qbl(tcg_ctx, t0, v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_dpsu_h_qbl(tcg_ctx, t0, v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_DPSU_H_QBR:
             check_dsp(ctx);
-            gen_helper_dpsu_h_qbr(tcg_ctx, t0, v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_dpsu_h_qbr(tcg_ctx, t0, v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_DPA_W_PH:
             check_dspr2(ctx);
-            gen_helper_dpa_w_ph(tcg_ctx, t0, v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_dpa_w_ph(tcg_ctx, t0, v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_DPAX_W_PH:
             check_dspr2(ctx);
-            gen_helper_dpax_w_ph(tcg_ctx, t0, v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_dpax_w_ph(tcg_ctx, t0, v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_DPAQ_S_W_PH:
             check_dsp(ctx);
-            gen_helper_dpaq_s_w_ph(tcg_ctx, t0, v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_dpaq_s_w_ph(tcg_ctx, t0, v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_DPAQX_S_W_PH:
             check_dspr2(ctx);
-            gen_helper_dpaqx_s_w_ph(tcg_ctx, t0, v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_dpaqx_s_w_ph(tcg_ctx, t0, v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_DPAQX_SA_W_PH:
             check_dspr2(ctx);
-            gen_helper_dpaqx_sa_w_ph(tcg_ctx, t0, v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_dpaqx_sa_w_ph(tcg_ctx, t0, v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_DPS_W_PH:
             check_dspr2(ctx);
-            gen_helper_dps_w_ph(tcg_ctx, t0, v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_dps_w_ph(tcg_ctx, t0, v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_DPSX_W_PH:
             check_dspr2(ctx);
-            gen_helper_dpsx_w_ph(tcg_ctx, t0, v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_dpsx_w_ph(tcg_ctx, t0, v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_DPSQ_S_W_PH:
             check_dsp(ctx);
-            gen_helper_dpsq_s_w_ph(tcg_ctx, t0, v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_dpsq_s_w_ph(tcg_ctx, t0, v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_DPSQX_S_W_PH:
             check_dspr2(ctx);
-            gen_helper_dpsqx_s_w_ph(tcg_ctx, t0, v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_dpsqx_s_w_ph(tcg_ctx, t0, v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_DPSQX_SA_W_PH:
             check_dspr2(ctx);
-            gen_helper_dpsqx_sa_w_ph(tcg_ctx, t0, v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_dpsqx_sa_w_ph(tcg_ctx, t0, v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_MULSAQ_S_W_PH:
             check_dsp(ctx);
-            gen_helper_mulsaq_s_w_ph(tcg_ctx, t0, v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_mulsaq_s_w_ph(tcg_ctx, t0, v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_DPAQ_SA_L_W:
             check_dsp(ctx);
-            gen_helper_dpaq_sa_l_w(tcg_ctx, t0, v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_dpaq_sa_l_w(tcg_ctx, t0, v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_DPSQ_SA_L_W:
             check_dsp(ctx);
-            gen_helper_dpsq_sa_l_w(tcg_ctx, t0, v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_dpsq_sa_l_w(tcg_ctx, t0, v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_MAQ_S_W_PHL:
             check_dsp(ctx);
-            gen_helper_maq_s_w_phl(tcg_ctx, t0, v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_maq_s_w_phl(tcg_ctx, t0, v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_MAQ_S_W_PHR:
             check_dsp(ctx);
-            gen_helper_maq_s_w_phr(tcg_ctx, t0, v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_maq_s_w_phr(tcg_ctx, t0, v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_MAQ_SA_W_PHL:
             check_dsp(ctx);
-            gen_helper_maq_sa_w_phl(tcg_ctx, t0, v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_maq_sa_w_phl(tcg_ctx, t0, v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_MAQ_SA_W_PHR:
             check_dsp(ctx);
-            gen_helper_maq_sa_w_phr(tcg_ctx, t0, v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_maq_sa_w_phr(tcg_ctx, t0, v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_MULSA_W_PH:
             check_dspr2(ctx);
-            gen_helper_mulsa_w_ph(tcg_ctx, t0, v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_mulsa_w_ph(tcg_ctx, t0, v1_t, v2_t, uc->cpu_env);
             break;
         }
         break;
@@ -16564,107 +16595,107 @@ static void gen_mipsdsp_multiply(DisasContext *ctx, uint32_t op1, uint32_t op2,
             switch (op2) {
             case OPC_DMADD:
                 check_dsp(ctx);
-                gen_helper_dmadd(tcg_ctx, v1_t, v2_t, t0, tcg_ctx->cpu_env);
+                gen_helper_dmadd(tcg_ctx, v1_t, v2_t, t0, uc->cpu_env);
                 break;
             case OPC_DMADDU:
                 check_dsp(ctx);
-                gen_helper_dmaddu(tcg_ctx, v1_t, v2_t, t0, tcg_ctx->cpu_env);
+                gen_helper_dmaddu(tcg_ctx, v1_t, v2_t, t0, uc->cpu_env);
                 break;
             case OPC_DMSUB:
                 check_dsp(ctx);
-                gen_helper_dmsub(tcg_ctx, v1_t, v2_t, t0, tcg_ctx->cpu_env);
+                gen_helper_dmsub(tcg_ctx, v1_t, v2_t, t0, uc->cpu_env);
                 break;
             case OPC_DMSUBU:
                 check_dsp(ctx);
-                gen_helper_dmsubu(tcg_ctx, v1_t, v2_t, t0, tcg_ctx->cpu_env);
+                gen_helper_dmsubu(tcg_ctx, v1_t, v2_t, t0, uc->cpu_env);
                 break;
             case OPC_DPA_W_QH:
                 check_dspr2(ctx);
-                gen_helper_dpa_w_qh(tcg_ctx, v1_t, v2_t, t0, tcg_ctx->cpu_env);
+                gen_helper_dpa_w_qh(tcg_ctx, v1_t, v2_t, t0, uc->cpu_env);
                 break;
             case OPC_DPAQ_S_W_QH:
                 check_dsp(ctx);
-                gen_helper_dpaq_s_w_qh(tcg_ctx, v1_t, v2_t, t0, tcg_ctx->cpu_env);
+                gen_helper_dpaq_s_w_qh(tcg_ctx, v1_t, v2_t, t0, uc->cpu_env);
                 break;
             case OPC_DPAQ_SA_L_PW:
                 check_dsp(ctx);
-                gen_helper_dpaq_sa_l_pw(tcg_ctx, v1_t, v2_t, t0, tcg_ctx->cpu_env);
+                gen_helper_dpaq_sa_l_pw(tcg_ctx, v1_t, v2_t, t0, uc->cpu_env);
                 break;
             case OPC_DPAU_H_OBL:
                 check_dsp(ctx);
-                gen_helper_dpau_h_obl(tcg_ctx, v1_t, v2_t, t0, tcg_ctx->cpu_env);
+                gen_helper_dpau_h_obl(tcg_ctx, v1_t, v2_t, t0, uc->cpu_env);
                 break;
             case OPC_DPAU_H_OBR:
                 check_dsp(ctx);
-                gen_helper_dpau_h_obr(tcg_ctx, v1_t, v2_t, t0, tcg_ctx->cpu_env);
+                gen_helper_dpau_h_obr(tcg_ctx, v1_t, v2_t, t0, uc->cpu_env);
                 break;
             case OPC_DPS_W_QH:
                 check_dspr2(ctx);
-                gen_helper_dps_w_qh(tcg_ctx, v1_t, v2_t, t0, tcg_ctx->cpu_env);
+                gen_helper_dps_w_qh(tcg_ctx, v1_t, v2_t, t0, uc->cpu_env);
                 break;
             case OPC_DPSQ_S_W_QH:
                 check_dsp(ctx);
-                gen_helper_dpsq_s_w_qh(tcg_ctx, v1_t, v2_t, t0, tcg_ctx->cpu_env);
+                gen_helper_dpsq_s_w_qh(tcg_ctx, v1_t, v2_t, t0, uc->cpu_env);
                 break;
             case OPC_DPSQ_SA_L_PW:
                 check_dsp(ctx);
-                gen_helper_dpsq_sa_l_pw(tcg_ctx, v1_t, v2_t, t0, tcg_ctx->cpu_env);
+                gen_helper_dpsq_sa_l_pw(tcg_ctx, v1_t, v2_t, t0, uc->cpu_env);
                 break;
             case OPC_DPSU_H_OBL:
                 check_dsp(ctx);
-                gen_helper_dpsu_h_obl(tcg_ctx, v1_t, v2_t, t0, tcg_ctx->cpu_env);
+                gen_helper_dpsu_h_obl(tcg_ctx, v1_t, v2_t, t0, uc->cpu_env);
                 break;
             case OPC_DPSU_H_OBR:
                 check_dsp(ctx);
-                gen_helper_dpsu_h_obr(tcg_ctx, v1_t, v2_t, t0, tcg_ctx->cpu_env);
+                gen_helper_dpsu_h_obr(tcg_ctx, v1_t, v2_t, t0, uc->cpu_env);
                 break;
             case OPC_MAQ_S_L_PWL:
                 check_dsp(ctx);
-                gen_helper_maq_s_l_pwl(tcg_ctx, v1_t, v2_t, t0, tcg_ctx->cpu_env);
+                gen_helper_maq_s_l_pwl(tcg_ctx, v1_t, v2_t, t0, uc->cpu_env);
                 break;
             case OPC_MAQ_S_L_PWR:
                 check_dsp(ctx);
-                gen_helper_maq_s_l_pwr(tcg_ctx, v1_t, v2_t, t0, tcg_ctx->cpu_env);
+                gen_helper_maq_s_l_pwr(tcg_ctx, v1_t, v2_t, t0, uc->cpu_env);
                 break;
             case OPC_MAQ_S_W_QHLL:
                 check_dsp(ctx);
-                gen_helper_maq_s_w_qhll(tcg_ctx, v1_t, v2_t, t0, tcg_ctx->cpu_env);
+                gen_helper_maq_s_w_qhll(tcg_ctx, v1_t, v2_t, t0, uc->cpu_env);
                 break;
             case OPC_MAQ_SA_W_QHLL:
                 check_dsp(ctx);
-                gen_helper_maq_sa_w_qhll(tcg_ctx, v1_t, v2_t, t0, tcg_ctx->cpu_env);
+                gen_helper_maq_sa_w_qhll(tcg_ctx, v1_t, v2_t, t0, uc->cpu_env);
                 break;
             case OPC_MAQ_S_W_QHLR:
                 check_dsp(ctx);
-                gen_helper_maq_s_w_qhlr(tcg_ctx, v1_t, v2_t, t0, tcg_ctx->cpu_env);
+                gen_helper_maq_s_w_qhlr(tcg_ctx, v1_t, v2_t, t0, uc->cpu_env);
                 break;
             case OPC_MAQ_SA_W_QHLR:
                 check_dsp(ctx);
-                gen_helper_maq_sa_w_qhlr(tcg_ctx, v1_t, v2_t, t0, tcg_ctx->cpu_env);
+                gen_helper_maq_sa_w_qhlr(tcg_ctx, v1_t, v2_t, t0, uc->cpu_env);
                 break;
             case OPC_MAQ_S_W_QHRL:
                 check_dsp(ctx);
-                gen_helper_maq_s_w_qhrl(tcg_ctx, v1_t, v2_t, t0, tcg_ctx->cpu_env);
+                gen_helper_maq_s_w_qhrl(tcg_ctx, v1_t, v2_t, t0, uc->cpu_env);
                 break;
             case OPC_MAQ_SA_W_QHRL:
                 check_dsp(ctx);
-                gen_helper_maq_sa_w_qhrl(tcg_ctx, v1_t, v2_t, t0, tcg_ctx->cpu_env);
+                gen_helper_maq_sa_w_qhrl(tcg_ctx, v1_t, v2_t, t0, uc->cpu_env);
                 break;
             case OPC_MAQ_S_W_QHRR:
                 check_dsp(ctx);
-                gen_helper_maq_s_w_qhrr(tcg_ctx, v1_t, v2_t, t0, tcg_ctx->cpu_env);
+                gen_helper_maq_s_w_qhrr(tcg_ctx, v1_t, v2_t, t0, uc->cpu_env);
                 break;
             case OPC_MAQ_SA_W_QHRR:
                 check_dsp(ctx);
-                gen_helper_maq_sa_w_qhrr(tcg_ctx, v1_t, v2_t, t0, tcg_ctx->cpu_env);
+                gen_helper_maq_sa_w_qhrr(tcg_ctx, v1_t, v2_t, t0, uc->cpu_env);
                 break;
             case OPC_MULSAQ_S_L_PW:
                 check_dsp(ctx);
-                gen_helper_mulsaq_s_l_pw(tcg_ctx, v1_t, v2_t, t0, tcg_ctx->cpu_env);
+                gen_helper_mulsaq_s_l_pw(tcg_ctx, v1_t, v2_t, t0, uc->cpu_env);
                 break;
             case OPC_MULSAQ_S_W_QH:
                 check_dsp(ctx);
-                gen_helper_mulsaq_s_w_qh(tcg_ctx, v1_t, v2_t, t0, tcg_ctx->cpu_env);
+                gen_helper_mulsaq_s_w_qh(tcg_ctx, v1_t, v2_t, t0, uc->cpu_env);
                 break;
             }
         }
@@ -16674,27 +16705,27 @@ static void gen_mipsdsp_multiply(DisasContext *ctx, uint32_t op1, uint32_t op2,
         switch (op2) {
         case OPC_MULEU_S_PH_QBL:
             check_dsp(ctx);
-            gen_helper_muleu_s_ph_qbl(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_muleu_s_ph_qbl(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_MULEU_S_PH_QBR:
             check_dsp(ctx);
-            gen_helper_muleu_s_ph_qbr(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_muleu_s_ph_qbr(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_MULQ_RS_PH:
             check_dsp(ctx);
-            gen_helper_mulq_rs_ph(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_mulq_rs_ph(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_MULEQ_S_W_PHL:
             check_dsp(ctx);
-            gen_helper_muleq_s_w_phl(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_muleq_s_w_phl(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_MULEQ_S_W_PHR:
             check_dsp(ctx);
-            gen_helper_muleq_s_w_phr(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_muleq_s_w_phr(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_MULQ_S_PH:
             check_dspr2(ctx);
-            gen_helper_mulq_s_ph(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_mulq_s_ph(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, uc->cpu_env);
             break;
         }
         break;
@@ -16703,23 +16734,23 @@ static void gen_mipsdsp_multiply(DisasContext *ctx, uint32_t op1, uint32_t op2,
         switch (op2) {
         case OPC_MULEQ_S_PW_QHL:
             check_dsp(ctx);
-            gen_helper_muleq_s_pw_qhl(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_muleq_s_pw_qhl(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_MULEQ_S_PW_QHR:
             check_dsp(ctx);
-            gen_helper_muleq_s_pw_qhr(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_muleq_s_pw_qhr(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_MULEU_S_QH_OBL:
             check_dsp(ctx);
-            gen_helper_muleu_s_qh_obl(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_muleu_s_qh_obl(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_MULEU_S_QH_OBR:
             check_dsp(ctx);
-            gen_helper_muleu_s_qh_obr(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_muleu_s_qh_obr(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_MULQ_RS_QH:
             check_dsp(ctx);
-            gen_helper_mulq_rs_qh(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_mulq_rs_qh(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, uc->cpu_env);
             break;
         }
         break;
@@ -16875,7 +16906,8 @@ static void gen_mipsdsp_add_cmp_pick(DisasContext *ctx,
                                      uint32_t op1, uint32_t op2,
                                      int ret, int v1, int v2, int check_ret)
 {
-    TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
+    struct uc_struct *uc = ctx->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv *cpu_gpr = tcg_ctx->cpu_gpr;
     TCGv t1;
     TCGv v1_t;
@@ -16898,15 +16930,15 @@ static void gen_mipsdsp_add_cmp_pick(DisasContext *ctx,
         switch (op2) {
         case OPC_CMPU_EQ_QB:
             check_dsp(ctx);
-            gen_helper_cmpu_eq_qb(tcg_ctx, v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_cmpu_eq_qb(tcg_ctx, v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_CMPU_LT_QB:
             check_dsp(ctx);
-            gen_helper_cmpu_lt_qb(tcg_ctx, v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_cmpu_lt_qb(tcg_ctx, v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_CMPU_LE_QB:
             check_dsp(ctx);
-            gen_helper_cmpu_le_qb(tcg_ctx, v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_cmpu_le_qb(tcg_ctx, v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_CMPGU_EQ_QB:
             check_dsp(ctx);
@@ -16946,23 +16978,23 @@ static void gen_mipsdsp_add_cmp_pick(DisasContext *ctx,
             break;
         case OPC_CMP_EQ_PH:
             check_dsp(ctx);
-            gen_helper_cmp_eq_ph(tcg_ctx, v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_cmp_eq_ph(tcg_ctx, v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_CMP_LT_PH:
             check_dsp(ctx);
-            gen_helper_cmp_lt_ph(tcg_ctx, v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_cmp_lt_ph(tcg_ctx, v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_CMP_LE_PH:
             check_dsp(ctx);
-            gen_helper_cmp_le_ph(tcg_ctx, v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_cmp_le_ph(tcg_ctx, v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_PICK_QB:
             check_dsp(ctx);
-            gen_helper_pick_qb(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_pick_qb(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_PICK_PH:
             check_dsp(ctx);
-            gen_helper_pick_ph(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_pick_ph(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_PACKRL_PH:
             check_dsp(ctx);
@@ -16975,39 +17007,39 @@ static void gen_mipsdsp_add_cmp_pick(DisasContext *ctx,
         switch (op2) {
         case OPC_CMP_EQ_PW:
             check_dsp(ctx);
-            gen_helper_cmp_eq_pw(tcg_ctx, v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_cmp_eq_pw(tcg_ctx, v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_CMP_LT_PW:
             check_dsp(ctx);
-            gen_helper_cmp_lt_pw(tcg_ctx, v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_cmp_lt_pw(tcg_ctx, v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_CMP_LE_PW:
             check_dsp(ctx);
-            gen_helper_cmp_le_pw(tcg_ctx, v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_cmp_le_pw(tcg_ctx, v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_CMP_EQ_QH:
             check_dsp(ctx);
-            gen_helper_cmp_eq_qh(tcg_ctx, v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_cmp_eq_qh(tcg_ctx, v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_CMP_LT_QH:
             check_dsp(ctx);
-            gen_helper_cmp_lt_qh(tcg_ctx, v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_cmp_lt_qh(tcg_ctx, v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_CMP_LE_QH:
             check_dsp(ctx);
-            gen_helper_cmp_le_qh(tcg_ctx, v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_cmp_le_qh(tcg_ctx, v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_CMPGDU_EQ_OB:
             check_dspr2(ctx);
-            gen_helper_cmpgdu_eq_ob(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_cmpgdu_eq_ob(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_CMPGDU_LT_OB:
             check_dspr2(ctx);
-            gen_helper_cmpgdu_lt_ob(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_cmpgdu_lt_ob(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_CMPGDU_LE_OB:
             check_dspr2(ctx);
-            gen_helper_cmpgdu_le_ob(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_cmpgdu_le_ob(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_CMPGU_EQ_OB:
             check_dsp(ctx);
@@ -17023,15 +17055,15 @@ static void gen_mipsdsp_add_cmp_pick(DisasContext *ctx,
             break;
         case OPC_CMPU_EQ_OB:
             check_dsp(ctx);
-            gen_helper_cmpu_eq_ob(tcg_ctx, v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_cmpu_eq_ob(tcg_ctx, v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_CMPU_LT_OB:
             check_dsp(ctx);
-            gen_helper_cmpu_lt_ob(tcg_ctx, v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_cmpu_lt_ob(tcg_ctx, v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_CMPU_LE_OB:
             check_dsp(ctx);
-            gen_helper_cmpu_le_ob(tcg_ctx, v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_cmpu_le_ob(tcg_ctx, v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_PACKRL_PW:
             check_dsp(ctx);
@@ -17039,15 +17071,15 @@ static void gen_mipsdsp_add_cmp_pick(DisasContext *ctx,
             break;
         case OPC_PICK_OB:
             check_dsp(ctx);
-            gen_helper_pick_ob(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_pick_ob(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_PICK_PW:
             check_dsp(ctx);
-            gen_helper_pick_pw(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_pick_pw(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, uc->cpu_env);
             break;
         case OPC_PICK_QH:
             check_dsp(ctx);
-            gen_helper_pick_qh(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
+            gen_helper_pick_qh(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, uc->cpu_env);
             break;
         }
         break;
@@ -17153,7 +17185,8 @@ static void gen_mipsdsp_accinsn(DisasContext *ctx, uint32_t op1, uint32_t op2,
                                 int ret, int v1, int v2, int check_ret)
 
 {
-    TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
+    struct uc_struct *uc = ctx->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv *cpu_gpr = tcg_ctx->cpu_gpr;
     TCGv t0;
     TCGv t1;
@@ -17181,80 +17214,80 @@ static void gen_mipsdsp_accinsn(DisasContext *ctx, uint32_t op1, uint32_t op2,
         case OPC_EXTR_W:
             tcg_gen_movi_tl(tcg_ctx, t0, v2);
             tcg_gen_movi_tl(tcg_ctx, t1, v1);
-            gen_helper_extr_w(tcg_ctx, cpu_gpr[ret], t0, t1, tcg_ctx->cpu_env);
+            gen_helper_extr_w(tcg_ctx, cpu_gpr[ret], t0, t1, uc->cpu_env);
             break;
         case OPC_EXTR_R_W:
             tcg_gen_movi_tl(tcg_ctx, t0, v2);
             tcg_gen_movi_tl(tcg_ctx, t1, v1);
-            gen_helper_extr_r_w(tcg_ctx, cpu_gpr[ret], t0, t1, tcg_ctx->cpu_env);
+            gen_helper_extr_r_w(tcg_ctx, cpu_gpr[ret], t0, t1, uc->cpu_env);
             break;
         case OPC_EXTR_RS_W:
             tcg_gen_movi_tl(tcg_ctx, t0, v2);
             tcg_gen_movi_tl(tcg_ctx, t1, v1);
-            gen_helper_extr_rs_w(tcg_ctx, cpu_gpr[ret], t0, t1, tcg_ctx->cpu_env);
+            gen_helper_extr_rs_w(tcg_ctx, cpu_gpr[ret], t0, t1, uc->cpu_env);
             break;
         case OPC_EXTR_S_H:
             tcg_gen_movi_tl(tcg_ctx, t0, v2);
             tcg_gen_movi_tl(tcg_ctx, t1, v1);
-            gen_helper_extr_s_h(tcg_ctx, cpu_gpr[ret], t0, t1, tcg_ctx->cpu_env);
+            gen_helper_extr_s_h(tcg_ctx, cpu_gpr[ret], t0, t1, uc->cpu_env);
             break;
         case OPC_EXTRV_S_H:
             tcg_gen_movi_tl(tcg_ctx, t0, v2);
-            gen_helper_extr_s_h(tcg_ctx, cpu_gpr[ret], t0, v1_t, tcg_ctx->cpu_env);
+            gen_helper_extr_s_h(tcg_ctx, cpu_gpr[ret], t0, v1_t, uc->cpu_env);
             break;
         case OPC_EXTRV_W:
             tcg_gen_movi_tl(tcg_ctx, t0, v2);
-            gen_helper_extr_w(tcg_ctx, cpu_gpr[ret], t0, v1_t, tcg_ctx->cpu_env);
+            gen_helper_extr_w(tcg_ctx, cpu_gpr[ret], t0, v1_t, uc->cpu_env);
             break;
         case OPC_EXTRV_R_W:
             tcg_gen_movi_tl(tcg_ctx, t0, v2);
-            gen_helper_extr_r_w(tcg_ctx, cpu_gpr[ret], t0, v1_t, tcg_ctx->cpu_env);
+            gen_helper_extr_r_w(tcg_ctx, cpu_gpr[ret], t0, v1_t, uc->cpu_env);
             break;
         case OPC_EXTRV_RS_W:
             tcg_gen_movi_tl(tcg_ctx, t0, v2);
-            gen_helper_extr_rs_w(tcg_ctx, cpu_gpr[ret], t0, v1_t, tcg_ctx->cpu_env);
+            gen_helper_extr_rs_w(tcg_ctx, cpu_gpr[ret], t0, v1_t, uc->cpu_env);
             break;
         case OPC_EXTP:
             tcg_gen_movi_tl(tcg_ctx, t0, v2);
             tcg_gen_movi_tl(tcg_ctx, t1, v1);
-            gen_helper_extp(tcg_ctx, cpu_gpr[ret], t0, t1, tcg_ctx->cpu_env);
+            gen_helper_extp(tcg_ctx, cpu_gpr[ret], t0, t1, uc->cpu_env);
             break;
         case OPC_EXTPV:
             tcg_gen_movi_tl(tcg_ctx, t0, v2);
-            gen_helper_extp(tcg_ctx, cpu_gpr[ret], t0, v1_t, tcg_ctx->cpu_env);
+            gen_helper_extp(tcg_ctx, cpu_gpr[ret], t0, v1_t, uc->cpu_env);
             break;
         case OPC_EXTPDP:
             tcg_gen_movi_tl(tcg_ctx, t0, v2);
             tcg_gen_movi_tl(tcg_ctx, t1, v1);
-            gen_helper_extpdp(tcg_ctx, cpu_gpr[ret], t0, t1, tcg_ctx->cpu_env);
+            gen_helper_extpdp(tcg_ctx, cpu_gpr[ret], t0, t1, uc->cpu_env);
             break;
         case OPC_EXTPDPV:
             tcg_gen_movi_tl(tcg_ctx, t0, v2);
-            gen_helper_extpdp(tcg_ctx, cpu_gpr[ret], t0, v1_t, tcg_ctx->cpu_env);
+            gen_helper_extpdp(tcg_ctx, cpu_gpr[ret], t0, v1_t, uc->cpu_env);
             break;
         case OPC_SHILO:
             imm = (ctx->opcode >> 20) & 0x3F;
             tcg_gen_movi_tl(tcg_ctx, t0, ret);
             tcg_gen_movi_tl(tcg_ctx, t1, imm);
-            gen_helper_shilo(tcg_ctx, t0, t1, tcg_ctx->cpu_env);
+            gen_helper_shilo(tcg_ctx, t0, t1, uc->cpu_env);
             break;
         case OPC_SHILOV:
             tcg_gen_movi_tl(tcg_ctx, t0, ret);
-            gen_helper_shilo(tcg_ctx, t0, v1_t, tcg_ctx->cpu_env);
+            gen_helper_shilo(tcg_ctx, t0, v1_t, uc->cpu_env);
             break;
         case OPC_MTHLIP:
             tcg_gen_movi_tl(tcg_ctx, t0, ret);
-            gen_helper_mthlip(tcg_ctx, t0, v1_t, tcg_ctx->cpu_env);
+            gen_helper_mthlip(tcg_ctx, t0, v1_t, uc->cpu_env);
             break;
         case OPC_WRDSP:
             imm = (ctx->opcode >> 11) & 0x3FF;
             tcg_gen_movi_tl(tcg_ctx, t0, imm);
-            gen_helper_wrdsp(tcg_ctx, v1_t, t0, tcg_ctx->cpu_env);
+            gen_helper_wrdsp(tcg_ctx, v1_t, t0, uc->cpu_env);
             break;
         case OPC_RDDSP:
             imm = (ctx->opcode >> 16) & 0x03FF;
             tcg_gen_movi_tl(tcg_ctx, t0, imm);
-            gen_helper_rddsp(tcg_ctx, cpu_gpr[ret], t0, tcg_ctx->cpu_env);
+            gen_helper_rddsp(tcg_ctx, cpu_gpr[ret], t0, uc->cpu_env);
             break;
         }
         break;
@@ -17264,7 +17297,7 @@ static void gen_mipsdsp_accinsn(DisasContext *ctx, uint32_t op1, uint32_t op2,
         switch (op2) {
         case OPC_DMTHLIP:
             tcg_gen_movi_tl(tcg_ctx, t0, ret);
-            gen_helper_dmthlip(tcg_ctx, v1_t, t0, tcg_ctx->cpu_env);
+            gen_helper_dmthlip(tcg_ctx, v1_t, t0, uc->cpu_env);
             break;
         case OPC_DSHILO:
             {
@@ -17272,98 +17305,98 @@ static void gen_mipsdsp_accinsn(DisasContext *ctx, uint32_t op1, uint32_t op2,
                 int ac = (ctx->opcode >> 11) & 0x03;
                 tcg_gen_movi_tl(tcg_ctx, t0, shift);
                 tcg_gen_movi_tl(tcg_ctx, t1, ac);
-                gen_helper_dshilo(tcg_ctx, t0, t1, tcg_ctx->cpu_env);
+                gen_helper_dshilo(tcg_ctx, t0, t1, uc->cpu_env);
                 break;
             }
         case OPC_DSHILOV:
             {
                 int ac = (ctx->opcode >> 11) & 0x03;
                 tcg_gen_movi_tl(tcg_ctx, t0, ac);
-                gen_helper_dshilo(tcg_ctx, v1_t, t0, tcg_ctx->cpu_env);
+                gen_helper_dshilo(tcg_ctx, v1_t, t0, uc->cpu_env);
                 break;
             }
         case OPC_DEXTP:
             tcg_gen_movi_tl(tcg_ctx, t0, v2);
             tcg_gen_movi_tl(tcg_ctx, t1, v1);
 
-            gen_helper_dextp(tcg_ctx, cpu_gpr[ret], t0, t1, tcg_ctx->cpu_env);
+            gen_helper_dextp(tcg_ctx, cpu_gpr[ret], t0, t1, uc->cpu_env);
             break;
         case OPC_DEXTPV:
             tcg_gen_movi_tl(tcg_ctx, t0, v2);
-            gen_helper_dextp(tcg_ctx, cpu_gpr[ret], t0, v1_t, tcg_ctx->cpu_env);
+            gen_helper_dextp(tcg_ctx, cpu_gpr[ret], t0, v1_t, uc->cpu_env);
             break;
         case OPC_DEXTPDP:
             tcg_gen_movi_tl(tcg_ctx, t0, v2);
             tcg_gen_movi_tl(tcg_ctx, t1, v1);
-            gen_helper_dextpdp(tcg_ctx, cpu_gpr[ret], t0, t1, tcg_ctx->cpu_env);
+            gen_helper_dextpdp(tcg_ctx, cpu_gpr[ret], t0, t1, uc->cpu_env);
             break;
         case OPC_DEXTPDPV:
             tcg_gen_movi_tl(tcg_ctx, t0, v2);
-            gen_helper_dextpdp(tcg_ctx, cpu_gpr[ret], t0, v1_t, tcg_ctx->cpu_env);
+            gen_helper_dextpdp(tcg_ctx, cpu_gpr[ret], t0, v1_t, uc->cpu_env);
             break;
         case OPC_DEXTR_L:
             tcg_gen_movi_tl(tcg_ctx, t0, v2);
             tcg_gen_movi_tl(tcg_ctx, t1, v1);
-            gen_helper_dextr_l(tcg_ctx, cpu_gpr[ret], t0, t1, tcg_ctx->cpu_env);
+            gen_helper_dextr_l(tcg_ctx, cpu_gpr[ret], t0, t1, uc->cpu_env);
             break;
         case OPC_DEXTR_R_L:
             tcg_gen_movi_tl(tcg_ctx, t0, v2);
             tcg_gen_movi_tl(tcg_ctx, t1, v1);
-            gen_helper_dextr_r_l(tcg_ctx, cpu_gpr[ret], t0, t1, tcg_ctx->cpu_env);
+            gen_helper_dextr_r_l(tcg_ctx, cpu_gpr[ret], t0, t1, uc->cpu_env);
             break;
         case OPC_DEXTR_RS_L:
             tcg_gen_movi_tl(tcg_ctx, t0, v2);
             tcg_gen_movi_tl(tcg_ctx, t1, v1);
-            gen_helper_dextr_rs_l(tcg_ctx, cpu_gpr[ret], t0, t1, tcg_ctx->cpu_env);
+            gen_helper_dextr_rs_l(tcg_ctx, cpu_gpr[ret], t0, t1, uc->cpu_env);
             break;
         case OPC_DEXTR_W:
             tcg_gen_movi_tl(tcg_ctx, t0, v2);
             tcg_gen_movi_tl(tcg_ctx, t1, v1);
-            gen_helper_dextr_w(tcg_ctx, cpu_gpr[ret], t0, t1, tcg_ctx->cpu_env);
+            gen_helper_dextr_w(tcg_ctx, cpu_gpr[ret], t0, t1, uc->cpu_env);
             break;
         case OPC_DEXTR_R_W:
             tcg_gen_movi_tl(tcg_ctx, t0, v2);
             tcg_gen_movi_tl(tcg_ctx, t1, v1);
-            gen_helper_dextr_r_w(tcg_ctx, cpu_gpr[ret], t0, t1, tcg_ctx->cpu_env);
+            gen_helper_dextr_r_w(tcg_ctx, cpu_gpr[ret], t0, t1, uc->cpu_env);
             break;
         case OPC_DEXTR_RS_W:
             tcg_gen_movi_tl(tcg_ctx, t0, v2);
             tcg_gen_movi_tl(tcg_ctx, t1, v1);
-            gen_helper_dextr_rs_w(tcg_ctx, cpu_gpr[ret], t0, t1, tcg_ctx->cpu_env);
+            gen_helper_dextr_rs_w(tcg_ctx, cpu_gpr[ret], t0, t1, uc->cpu_env);
             break;
         case OPC_DEXTR_S_H:
             tcg_gen_movi_tl(tcg_ctx, t0, v2);
             tcg_gen_movi_tl(tcg_ctx, t1, v1);
-            gen_helper_dextr_s_h(tcg_ctx, cpu_gpr[ret], t0, t1, tcg_ctx->cpu_env);
+            gen_helper_dextr_s_h(tcg_ctx, cpu_gpr[ret], t0, t1, uc->cpu_env);
             break;
         case OPC_DEXTRV_S_H:
             tcg_gen_movi_tl(tcg_ctx, t0, v2);
             tcg_gen_movi_tl(tcg_ctx, t1, v1);
-            gen_helper_dextr_s_h(tcg_ctx, cpu_gpr[ret], t0, t1, tcg_ctx->cpu_env);
+            gen_helper_dextr_s_h(tcg_ctx, cpu_gpr[ret], t0, t1, uc->cpu_env);
             break;
         case OPC_DEXTRV_L:
             tcg_gen_movi_tl(tcg_ctx, t0, v2);
-            gen_helper_dextr_l(tcg_ctx, cpu_gpr[ret], t0, v1_t, tcg_ctx->cpu_env);
+            gen_helper_dextr_l(tcg_ctx, cpu_gpr[ret], t0, v1_t, uc->cpu_env);
             break;
         case OPC_DEXTRV_R_L:
             tcg_gen_movi_tl(tcg_ctx, t0, v2);
-            gen_helper_dextr_r_l(tcg_ctx, cpu_gpr[ret], t0, v1_t, tcg_ctx->cpu_env);
+            gen_helper_dextr_r_l(tcg_ctx, cpu_gpr[ret], t0, v1_t, uc->cpu_env);
             break;
         case OPC_DEXTRV_RS_L:
             tcg_gen_movi_tl(tcg_ctx, t0, v2);
-            gen_helper_dextr_rs_l(tcg_ctx, cpu_gpr[ret], t0, v1_t, tcg_ctx->cpu_env);
+            gen_helper_dextr_rs_l(tcg_ctx, cpu_gpr[ret], t0, v1_t, uc->cpu_env);
             break;
         case OPC_DEXTRV_W:
             tcg_gen_movi_tl(tcg_ctx, t0, v2);
-            gen_helper_dextr_w(tcg_ctx, cpu_gpr[ret], t0, v1_t, tcg_ctx->cpu_env);
+            gen_helper_dextr_w(tcg_ctx, cpu_gpr[ret], t0, v1_t, uc->cpu_env);
             break;
         case OPC_DEXTRV_R_W:
             tcg_gen_movi_tl(tcg_ctx, t0, v2);
-            gen_helper_dextr_r_w(tcg_ctx, cpu_gpr[ret], t0, v1_t, tcg_ctx->cpu_env);
+            gen_helper_dextr_r_w(tcg_ctx, cpu_gpr[ret], t0, v1_t, uc->cpu_env);
             break;
         case OPC_DEXTRV_RS_W:
             tcg_gen_movi_tl(tcg_ctx, t0, v2);
-            gen_helper_dextr_rs_w(tcg_ctx, cpu_gpr[ret], t0, v1_t, tcg_ctx->cpu_env);
+            gen_helper_dextr_rs_w(tcg_ctx, cpu_gpr[ret], t0, v1_t, uc->cpu_env);
             break;
         }
         break;
@@ -17905,7 +17938,8 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx)
 
 static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
 {
-    TCGContext *tcg_ctx = env->uc->tcg_ctx;
+    struct uc_struct *uc = env->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv *cpu_gpr = tcg_ctx->cpu_gpr;
     int rs, rt, rd;
     uint32_t op1, op2;
@@ -18134,7 +18168,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
                 gen_load_gpr(ctx, t0, rt);
                 gen_load_gpr(ctx, t1, rs);
 
-                gen_helper_insv(tcg_ctx, cpu_gpr[rt], tcg_ctx->cpu_env, t1, t0);
+                gen_helper_insv(tcg_ctx, cpu_gpr[rt], uc->cpu_env, t1, t0);
 
                 tcg_temp_free(tcg_ctx, t0);
                 tcg_temp_free(tcg_ctx, t1);
@@ -18402,7 +18436,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
             gen_load_gpr(ctx, t0, rt);
             gen_load_gpr(ctx, t1, rs);
 
-            gen_helper_dinsv(tcg_ctx, cpu_gpr[rt], tcg_ctx->cpu_env, t1, t0);
+            gen_helper_dinsv(tcg_ctx, cpu_gpr[rt], uc->cpu_env, t1, t0);
 
             tcg_temp_free(tcg_ctx, t0);
             tcg_temp_free(tcg_ctx, t1);
@@ -18427,7 +18461,8 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
 
 static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
 {
-    TCGContext *tcg_ctx = env->uc->tcg_ctx;
+    struct uc_struct *uc = env->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     int rs, rt, rd, sa;
     uint32_t op1, op2;
     int16_t imm;
@@ -18547,7 +18582,7 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
             TCGv t0 = tcg_temp_new(tcg_ctx);
 
             gen_load_gpr(ctx, t0, rs);
-            gen_helper_yield(tcg_ctx, t0, tcg_ctx->cpu_env, t0);
+            gen_helper_yield(tcg_ctx, t0, uc->cpu_env, t0);
             gen_store_gpr(tcg_ctx, t0, rd);
             tcg_temp_free(tcg_ctx, t0);
         }
@@ -18673,7 +18708,8 @@ static void gen_msa_branch(CPUMIPSState *env, DisasContext *ctx, uint32_t op1)
 static void gen_msa_i8(CPUMIPSState *env, DisasContext *ctx)
 {
 #define MASK_MSA_I8(op)    (MASK_MSA_MINOR(op) | (op & (0x03 << 24)))
-    TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
+    struct uc_struct *uc = ctx->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     uint8_t i8 = (ctx->opcode >> 16) & 0xff;
     uint8_t ws = (ctx->opcode >> 11) & 0x1f;
     uint8_t wd = (ctx->opcode >> 6) & 0x1f;
@@ -18684,25 +18720,25 @@ static void gen_msa_i8(CPUMIPSState *env, DisasContext *ctx)
 
     switch (MASK_MSA_I8(ctx->opcode)) {
     case OPC_ANDI_B:
-        gen_helper_msa_andi_b(tcg_ctx, tcg_ctx->cpu_env, twd, tws, ti8);
+        gen_helper_msa_andi_b(tcg_ctx, uc->cpu_env, twd, tws, ti8);
         break;
     case OPC_ORI_B:
-        gen_helper_msa_ori_b(tcg_ctx, tcg_ctx->cpu_env, twd, tws, ti8);
+        gen_helper_msa_ori_b(tcg_ctx, uc->cpu_env, twd, tws, ti8);
         break;
     case OPC_NORI_B:
-        gen_helper_msa_nori_b(tcg_ctx, tcg_ctx->cpu_env, twd, tws, ti8);
+        gen_helper_msa_nori_b(tcg_ctx, uc->cpu_env, twd, tws, ti8);
         break;
     case OPC_XORI_B:
-        gen_helper_msa_xori_b(tcg_ctx, tcg_ctx->cpu_env, twd, tws, ti8);
+        gen_helper_msa_xori_b(tcg_ctx, uc->cpu_env, twd, tws, ti8);
         break;
     case OPC_BMNZI_B:
-        gen_helper_msa_bmnzi_b(tcg_ctx, tcg_ctx->cpu_env, twd, tws, ti8);
+        gen_helper_msa_bmnzi_b(tcg_ctx, uc->cpu_env, twd, tws, ti8);
         break;
     case OPC_BMZI_B:
-        gen_helper_msa_bmzi_b(tcg_ctx, tcg_ctx->cpu_env, twd, tws, ti8);
+        gen_helper_msa_bmzi_b(tcg_ctx, uc->cpu_env, twd, tws, ti8);
         break;
     case OPC_BSELI_B:
-        gen_helper_msa_bseli_b(tcg_ctx, tcg_ctx->cpu_env, twd, tws, ti8);
+        gen_helper_msa_bseli_b(tcg_ctx, uc->cpu_env, twd, tws, ti8);
         break;
     case OPC_SHF_B:
     case OPC_SHF_H:
@@ -18713,7 +18749,7 @@ static void gen_msa_i8(CPUMIPSState *env, DisasContext *ctx)
                 generate_exception_end(ctx, EXCP_RI);
             } else {
                 TCGv_i32 tdf = tcg_const_i32(tcg_ctx, df);
-                gen_helper_msa_shf_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, ti8);
+                gen_helper_msa_shf_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, ti8);
                 tcg_temp_free_i32(tcg_ctx, tdf);
             }
         }
@@ -18732,7 +18768,8 @@ static void gen_msa_i8(CPUMIPSState *env, DisasContext *ctx)
 static void gen_msa_i5(CPUMIPSState *env, DisasContext *ctx)
 {
 #define MASK_MSA_I5(op)    (MASK_MSA_MINOR(op) | (op & (0x7 << 23)))
-    TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
+    struct uc_struct *uc = ctx->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     uint8_t df = (ctx->opcode >> 21) & 0x3;
     int8_t s5 = (int8_t) sextract32(ctx->opcode, 16, 5);
     uint8_t u5 = (ctx->opcode >> 16) & 0x1f;
@@ -18747,48 +18784,48 @@ static void gen_msa_i5(CPUMIPSState *env, DisasContext *ctx)
 
     switch (MASK_MSA_I5(ctx->opcode)) {
     case OPC_ADDVI_df:
-        gen_helper_msa_addvi_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, timm);
+        gen_helper_msa_addvi_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, timm);
         break;
     case OPC_SUBVI_df:
-        gen_helper_msa_subvi_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, timm);
+        gen_helper_msa_subvi_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, timm);
         break;
     case OPC_MAXI_S_df:
         tcg_gen_movi_i32(tcg_ctx, timm, s5);
-        gen_helper_msa_maxi_s_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, timm);
+        gen_helper_msa_maxi_s_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, timm);
         break;
     case OPC_MAXI_U_df:
-        gen_helper_msa_maxi_u_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, timm);
+        gen_helper_msa_maxi_u_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, timm);
         break;
     case OPC_MINI_S_df:
         tcg_gen_movi_i32(tcg_ctx, timm, s5);
-        gen_helper_msa_mini_s_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, timm);
+        gen_helper_msa_mini_s_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, timm);
         break;
     case OPC_MINI_U_df:
-        gen_helper_msa_mini_u_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, timm);
+        gen_helper_msa_mini_u_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, timm);
         break;
     case OPC_CEQI_df:
         tcg_gen_movi_i32(tcg_ctx, timm, s5);
-        gen_helper_msa_ceqi_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, timm);
+        gen_helper_msa_ceqi_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, timm);
         break;
     case OPC_CLTI_S_df:
         tcg_gen_movi_i32(tcg_ctx, timm, s5);
-        gen_helper_msa_clti_s_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, timm);
+        gen_helper_msa_clti_s_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, timm);
         break;
     case OPC_CLTI_U_df:
-        gen_helper_msa_clti_u_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, timm);
+        gen_helper_msa_clti_u_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, timm);
         break;
     case OPC_CLEI_S_df:
         tcg_gen_movi_i32(tcg_ctx, timm, s5);
-        gen_helper_msa_clei_s_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, timm);
+        gen_helper_msa_clei_s_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, timm);
         break;
     case OPC_CLEI_U_df:
-        gen_helper_msa_clei_u_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, timm);
+        gen_helper_msa_clei_u_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, timm);
         break;
     case OPC_LDI_df:
         {
             int32_t s10 = sextract32(ctx->opcode, 11, 10);
             tcg_gen_movi_i32(tcg_ctx, timm, s10);
-            gen_helper_msa_ldi_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, timm);
+            gen_helper_msa_ldi_df(tcg_ctx, uc->cpu_env, tdf, twd, timm);
         }
         break;
     default:
@@ -18806,7 +18843,8 @@ static void gen_msa_i5(CPUMIPSState *env, DisasContext *ctx)
 static void gen_msa_bit(CPUMIPSState *env, DisasContext *ctx)
 {
 #define MASK_MSA_BIT(op)    (MASK_MSA_MINOR(op) | (op & (0x7 << 23)))
-    TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
+    struct uc_struct *uc = ctx->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     uint8_t dfm = (ctx->opcode >> 16) & 0x7f;
     uint32_t df = 0, m = 0;
     uint8_t ws = (ctx->opcode >> 11) & 0x1f;
@@ -18841,40 +18879,40 @@ static void gen_msa_bit(CPUMIPSState *env, DisasContext *ctx)
 
     switch (MASK_MSA_BIT(ctx->opcode)) {
     case OPC_SLLI_df:
-        gen_helper_msa_slli_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, tm);
+        gen_helper_msa_slli_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, tm);
         break;
     case OPC_SRAI_df:
-        gen_helper_msa_srai_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, tm);
+        gen_helper_msa_srai_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, tm);
         break;
     case OPC_SRLI_df:
-        gen_helper_msa_srli_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, tm);
+        gen_helper_msa_srli_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, tm);
         break;
     case OPC_BCLRI_df:
-        gen_helper_msa_bclri_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, tm);
+        gen_helper_msa_bclri_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, tm);
         break;
     case OPC_BSETI_df:
-        gen_helper_msa_bseti_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, tm);
+        gen_helper_msa_bseti_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, tm);
         break;
     case OPC_BNEGI_df:
-        gen_helper_msa_bnegi_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, tm);
+        gen_helper_msa_bnegi_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, tm);
         break;
     case OPC_BINSLI_df:
-        gen_helper_msa_binsli_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, tm);
+        gen_helper_msa_binsli_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, tm);
         break;
     case OPC_BINSRI_df:
-        gen_helper_msa_binsri_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, tm);
+        gen_helper_msa_binsri_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, tm);
         break;
     case OPC_SAT_S_df:
-        gen_helper_msa_sat_s_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, tm);
+        gen_helper_msa_sat_s_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, tm);
         break;
     case OPC_SAT_U_df:
-        gen_helper_msa_sat_u_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, tm);
+        gen_helper_msa_sat_u_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, tm);
         break;
     case OPC_SRARI_df:
-        gen_helper_msa_srari_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, tm);
+        gen_helper_msa_srari_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, tm);
         break;
     case OPC_SRLRI_df:
-        gen_helper_msa_srlri_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, tm);
+        gen_helper_msa_srlri_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, tm);
         break;
     default:
         MIPS_INVAL("MSA instruction");
@@ -18891,7 +18929,8 @@ static void gen_msa_bit(CPUMIPSState *env, DisasContext *ctx)
 static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
 {
 #define MASK_MSA_3R(op)    (MASK_MSA_MINOR(op) | (op & (0x7 << 23)))
-    TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
+    struct uc_struct *uc = ctx->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     uint8_t df = (ctx->opcode >> 21) & 0x3;
     uint8_t wt = (ctx->opcode >> 16) & 0x1f;
     uint8_t ws = (ctx->opcode >> 11) & 0x1f;
@@ -18904,163 +18943,163 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
 
     switch (MASK_MSA_3R(ctx->opcode)) {
     case OPC_SLL_df:
-        gen_helper_msa_sll_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_sll_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_ADDV_df:
-        gen_helper_msa_addv_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_addv_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_CEQ_df:
-        gen_helper_msa_ceq_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_ceq_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_ADD_A_df:
-        gen_helper_msa_add_a_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_add_a_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_SUBS_S_df:
-        gen_helper_msa_subs_s_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_subs_s_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_MULV_df:
-        gen_helper_msa_mulv_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_mulv_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_SLD_df:
-        gen_helper_msa_sld_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_sld_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_VSHF_df:
-        gen_helper_msa_vshf_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_vshf_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_SRA_df:
-        gen_helper_msa_sra_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_sra_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_SUBV_df:
-        gen_helper_msa_subv_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_subv_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_ADDS_A_df:
-        gen_helper_msa_adds_a_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_adds_a_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_SUBS_U_df:
-        gen_helper_msa_subs_u_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_subs_u_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_MADDV_df:
-        gen_helper_msa_maddv_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_maddv_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_SPLAT_df:
-        gen_helper_msa_splat_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_splat_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_SRAR_df:
-        gen_helper_msa_srar_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_srar_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_SRL_df:
-        gen_helper_msa_srl_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_srl_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_MAX_S_df:
-        gen_helper_msa_max_s_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_max_s_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_CLT_S_df:
-        gen_helper_msa_clt_s_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_clt_s_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_ADDS_S_df:
-        gen_helper_msa_adds_s_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_adds_s_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_SUBSUS_U_df:
-        gen_helper_msa_subsus_u_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_subsus_u_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_MSUBV_df:
-        gen_helper_msa_msubv_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_msubv_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_PCKEV_df:
-        gen_helper_msa_pckev_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_pckev_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_SRLR_df:
-        gen_helper_msa_srlr_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_srlr_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_BCLR_df:
-        gen_helper_msa_bclr_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_bclr_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_MAX_U_df:
-        gen_helper_msa_max_u_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_max_u_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_CLT_U_df:
-        gen_helper_msa_clt_u_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_clt_u_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_ADDS_U_df:
-        gen_helper_msa_adds_u_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_adds_u_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_SUBSUU_S_df:
-        gen_helper_msa_subsuu_s_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_subsuu_s_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_PCKOD_df:
-        gen_helper_msa_pckod_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_pckod_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_BSET_df:
-        gen_helper_msa_bset_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_bset_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_MIN_S_df:
-        gen_helper_msa_min_s_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_min_s_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_CLE_S_df:
-        gen_helper_msa_cle_s_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_cle_s_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_AVE_S_df:
-        gen_helper_msa_ave_s_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_ave_s_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_ASUB_S_df:
-        gen_helper_msa_asub_s_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_asub_s_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_DIV_S_df:
-        gen_helper_msa_div_s_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_div_s_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_ILVL_df:
-        gen_helper_msa_ilvl_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_ilvl_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_BNEG_df:
-        gen_helper_msa_bneg_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_bneg_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_MIN_U_df:
-        gen_helper_msa_min_u_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_min_u_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_CLE_U_df:
-        gen_helper_msa_cle_u_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_cle_u_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_AVE_U_df:
-        gen_helper_msa_ave_u_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_ave_u_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_ASUB_U_df:
-        gen_helper_msa_asub_u_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_asub_u_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_DIV_U_df:
-        gen_helper_msa_div_u_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_div_u_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_ILVR_df:
-        gen_helper_msa_ilvr_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_ilvr_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_BINSL_df:
-        gen_helper_msa_binsl_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_binsl_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_MAX_A_df:
-        gen_helper_msa_max_a_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_max_a_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_AVER_S_df:
-        gen_helper_msa_aver_s_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_aver_s_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_MOD_S_df:
-        gen_helper_msa_mod_s_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_mod_s_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_ILVEV_df:
-        gen_helper_msa_ilvev_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_ilvev_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_BINSR_df:
-        gen_helper_msa_binsr_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_binsr_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_MIN_A_df:
-        gen_helper_msa_min_a_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_min_a_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_AVER_U_df:
-        gen_helper_msa_aver_u_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_aver_u_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_MOD_U_df:
-        gen_helper_msa_mod_u_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_mod_u_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_ILVOD_df:
-        gen_helper_msa_ilvod_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_ilvod_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
 
     case OPC_DOTP_S_df:
@@ -19079,34 +19118,34 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
         }
         switch (MASK_MSA_3R(ctx->opcode)) {
         case OPC_DOTP_S_df:
-            gen_helper_msa_dotp_s_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+            gen_helper_msa_dotp_s_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
             break;
         case OPC_DOTP_U_df:
-            gen_helper_msa_dotp_u_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+            gen_helper_msa_dotp_u_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
             break;
         case OPC_DPADD_S_df:
-            gen_helper_msa_dpadd_s_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+            gen_helper_msa_dpadd_s_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
             break;
         case OPC_DPADD_U_df:
-            gen_helper_msa_dpadd_u_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+            gen_helper_msa_dpadd_u_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
             break;
         case OPC_DPSUB_S_df:
-            gen_helper_msa_dpsub_s_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+            gen_helper_msa_dpsub_s_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
             break;
         case OPC_HADD_S_df:
-            gen_helper_msa_hadd_s_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+            gen_helper_msa_hadd_s_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
             break;
         case OPC_DPSUB_U_df:
-            gen_helper_msa_dpsub_u_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+            gen_helper_msa_dpsub_u_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
             break;
         case OPC_HADD_U_df:
-            gen_helper_msa_hadd_u_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+            gen_helper_msa_hadd_u_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
             break;
         case OPC_HSUB_S_df:
-            gen_helper_msa_hsub_s_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+            gen_helper_msa_hsub_s_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
             break;
         case OPC_HSUB_U_df:
-            gen_helper_msa_hsub_u_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+            gen_helper_msa_hsub_u_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
             break;
         }
         break;
@@ -19124,7 +19163,8 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
 static void gen_msa_elm_3e(CPUMIPSState *env, DisasContext *ctx)
 {
 #define MASK_MSA_ELM_DF3E(op)   (MASK_MSA_MINOR(op) | (op & (0x3FF << 16)))
-    TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
+    struct uc_struct *uc = ctx->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     uint8_t source = (ctx->opcode >> 11) & 0x1f;
     uint8_t dest = (ctx->opcode >> 6) & 0x1f;
     TCGv telm = tcg_temp_new(tcg_ctx);
@@ -19134,14 +19174,14 @@ static void gen_msa_elm_3e(CPUMIPSState *env, DisasContext *ctx)
     switch (MASK_MSA_ELM_DF3E(ctx->opcode)) {
     case OPC_CTCMSA:
         gen_load_gpr(ctx, telm, source);
-        gen_helper_msa_ctcmsa(tcg_ctx, tcg_ctx->cpu_env, telm, tdt);
+        gen_helper_msa_ctcmsa(tcg_ctx, uc->cpu_env, telm, tdt);
         break;
     case OPC_CFCMSA:
-        gen_helper_msa_cfcmsa(tcg_ctx, telm, tcg_ctx->cpu_env, tsr);
+        gen_helper_msa_cfcmsa(tcg_ctx, telm, uc->cpu_env, tsr);
         gen_store_gpr(tcg_ctx, telm, dest);
         break;
     case OPC_MOVE_V:
-        gen_helper_msa_move_v(tcg_ctx, tcg_ctx->cpu_env, tdt, tsr);
+        gen_helper_msa_move_v(tcg_ctx, uc->cpu_env, tdt, tsr);
         break;
     default:
         MIPS_INVAL("MSA instruction");
@@ -19158,7 +19198,8 @@ static void gen_msa_elm_df(CPUMIPSState *env, DisasContext *ctx, uint32_t df,
         uint32_t n)
 {
 #define MASK_MSA_ELM(op)    (MASK_MSA_MINOR(op) | (op & (0xf << 22)))
-    TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
+    struct uc_struct *uc = ctx->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     uint8_t ws = (ctx->opcode >> 11) & 0x1f;
     uint8_t wd = (ctx->opcode >> 6) & 0x1f;
 
@@ -19169,13 +19210,13 @@ static void gen_msa_elm_df(CPUMIPSState *env, DisasContext *ctx, uint32_t df,
 
     switch (MASK_MSA_ELM(ctx->opcode)) {
     case OPC_SLDI_df:
-        gen_helper_msa_sldi_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, tn);
+        gen_helper_msa_sldi_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, tn);
         break;
     case OPC_SPLATI_df:
-        gen_helper_msa_splati_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, tn);
+        gen_helper_msa_splati_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, tn);
         break;
     case OPC_INSVE_df:
-        gen_helper_msa_insve_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, tn);
+        gen_helper_msa_insve_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, tn);
         break;
     case OPC_COPY_S_df:
     case OPC_COPY_U_df:
@@ -19190,16 +19231,16 @@ static void gen_msa_elm_df(CPUMIPSState *env, DisasContext *ctx, uint32_t df,
         switch (MASK_MSA_ELM(ctx->opcode)) {
         case OPC_COPY_S_df:
             if (likely(wd != 0)) {
-                gen_helper_msa_copy_s_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, tn);
+                gen_helper_msa_copy_s_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, tn);
             }
             break;
         case OPC_COPY_U_df:
             if (likely(wd != 0)) {
-                gen_helper_msa_copy_u_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, tn);
+                gen_helper_msa_copy_u_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, tn);
             }
             break;
         case OPC_INSERT_df:
-            gen_helper_msa_insert_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, tn);
+            gen_helper_msa_insert_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, tn);
             break;
         }
         break;
@@ -19245,7 +19286,8 @@ static void gen_msa_elm(CPUMIPSState *env, DisasContext *ctx)
 static void gen_msa_3rf(CPUMIPSState *env, DisasContext *ctx)
 {
 #define MASK_MSA_3RF(op)    (MASK_MSA_MINOR(op) | (op & (0xf << 22)))
-    TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
+    struct uc_struct *uc = ctx->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     uint8_t df = (ctx->opcode >> 21) & 0x1;
     uint8_t wt = (ctx->opcode >> 16) & 0x1f;
     uint8_t ws = (ctx->opcode >> 11) & 0x1f;
@@ -19261,133 +19303,133 @@ static void gen_msa_3rf(CPUMIPSState *env, DisasContext *ctx)
 
     switch (MASK_MSA_3RF(ctx->opcode)) {
     case OPC_FCAF_df:
-        gen_helper_msa_fcaf_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_fcaf_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_FADD_df:
-        gen_helper_msa_fadd_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_fadd_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_FCUN_df:
-        gen_helper_msa_fcun_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_fcun_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_FSUB_df:
-        gen_helper_msa_fsub_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_fsub_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_FCOR_df:
-        gen_helper_msa_fcor_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_fcor_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_FCEQ_df:
-        gen_helper_msa_fceq_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_fceq_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_FMUL_df:
-        gen_helper_msa_fmul_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_fmul_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_FCUNE_df:
-        gen_helper_msa_fcune_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_fcune_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_FCUEQ_df:
-        gen_helper_msa_fcueq_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_fcueq_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_FDIV_df:
-        gen_helper_msa_fdiv_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_fdiv_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_FCNE_df:
-        gen_helper_msa_fcne_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_fcne_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_FCLT_df:
-        gen_helper_msa_fclt_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_fclt_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_FMADD_df:
-        gen_helper_msa_fmadd_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_fmadd_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_MUL_Q_df:
         tcg_gen_movi_i32(tcg_ctx, tdf, df + 1);
-        gen_helper_msa_mul_q_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_mul_q_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_FCULT_df:
-        gen_helper_msa_fcult_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_fcult_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_FMSUB_df:
-        gen_helper_msa_fmsub_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_fmsub_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_MADD_Q_df:
         tcg_gen_movi_i32(tcg_ctx, tdf, df + 1);
-        gen_helper_msa_madd_q_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_madd_q_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_FCLE_df:
-        gen_helper_msa_fcle_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_fcle_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_MSUB_Q_df:
         tcg_gen_movi_i32(tcg_ctx, tdf, df + 1);
-        gen_helper_msa_msub_q_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_msub_q_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_FCULE_df:
-        gen_helper_msa_fcule_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_fcule_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_FEXP2_df:
-        gen_helper_msa_fexp2_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_fexp2_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_FSAF_df:
-        gen_helper_msa_fsaf_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_fsaf_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_FEXDO_df:
-        gen_helper_msa_fexdo_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_fexdo_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_FSUN_df:
-        gen_helper_msa_fsun_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_fsun_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_FSOR_df:
-        gen_helper_msa_fsor_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_fsor_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_FSEQ_df:
-        gen_helper_msa_fseq_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_fseq_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_FTQ_df:
-        gen_helper_msa_ftq_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_ftq_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_FSUNE_df:
-        gen_helper_msa_fsune_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_fsune_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_FSUEQ_df:
-        gen_helper_msa_fsueq_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_fsueq_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_FSNE_df:
-        gen_helper_msa_fsne_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_fsne_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_FSLT_df:
-        gen_helper_msa_fslt_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_fslt_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_FMIN_df:
-        gen_helper_msa_fmin_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_fmin_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_MULR_Q_df:
         tcg_gen_movi_i32(tcg_ctx, tdf, df + 1);
-        gen_helper_msa_mulr_q_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_mulr_q_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_FSULT_df:
-        gen_helper_msa_fsult_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_fsult_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_FMIN_A_df:
-        gen_helper_msa_fmin_a_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_fmin_a_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_MADDR_Q_df:
         tcg_gen_movi_i32(tcg_ctx, tdf, df + 1);
-        gen_helper_msa_maddr_q_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_maddr_q_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_FSLE_df:
-        gen_helper_msa_fsle_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_fsle_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_FMAX_df:
-        gen_helper_msa_fmax_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_fmax_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_MSUBR_Q_df:
         tcg_gen_movi_i32(tcg_ctx, tdf, df + 1);
-        gen_helper_msa_msubr_q_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_msubr_q_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_FSULE_df:
-        gen_helper_msa_fsule_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_fsule_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     case OPC_FMAX_A_df:
-        gen_helper_msa_fmax_a_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, twt);
+        gen_helper_msa_fmax_a_df(tcg_ctx, uc->cpu_env, tdf, twd, tws, twt);
         break;
     default:
         MIPS_INVAL("MSA instruction");
@@ -19405,7 +19447,8 @@ static void gen_msa_2r(CPUMIPSState *env, DisasContext *ctx)
 {
 #define MASK_MSA_2R(op)     (MASK_MSA_MINOR(op) | (op & (0x1f << 21)) | \
                             (op & (0x7 << 18)))
-    TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
+    struct uc_struct *uc = ctx->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     uint8_t wt = (ctx->opcode >> 16) & 0x1f;
     uint8_t ws = (ctx->opcode >> 11) & 0x1f;
     uint8_t wd = (ctx->opcode >> 6) & 0x1f;
@@ -19424,16 +19467,16 @@ static void gen_msa_2r(CPUMIPSState *env, DisasContext *ctx)
             break;
         }
 #endif
-        gen_helper_msa_fill_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws); /* trs */
+        gen_helper_msa_fill_df(tcg_ctx, uc->cpu_env, tdf, twd, tws); /* trs */
         break;
     case OPC_PCNT_df:
-        gen_helper_msa_pcnt_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws);
+        gen_helper_msa_pcnt_df(tcg_ctx, uc->cpu_env, tdf, twd, tws);
         break;
     case OPC_NLOC_df:
-        gen_helper_msa_nloc_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws);
+        gen_helper_msa_nloc_df(tcg_ctx, uc->cpu_env, tdf, twd, tws);
         break;
     case OPC_NLZC_df:
-        gen_helper_msa_nlzc_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws);
+        gen_helper_msa_nlzc_df(tcg_ctx, uc->cpu_env, tdf, twd, tws);
         break;
     default:
         MIPS_INVAL("MSA instruction");
@@ -19451,7 +19494,8 @@ static void gen_msa_2rf(CPUMIPSState *env, DisasContext *ctx)
 {
 #define MASK_MSA_2RF(op)    (MASK_MSA_MINOR(op) | (op & (0x1f << 21)) | \
                             (op & (0xf << 17)))
-    TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
+    struct uc_struct *uc = ctx->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     uint8_t wt = (ctx->opcode >> 16) & 0x1f;
     uint8_t ws = (ctx->opcode >> 11) & 0x1f;
     uint8_t wd = (ctx->opcode >> 6) & 0x1f;
@@ -19464,52 +19508,52 @@ static void gen_msa_2rf(CPUMIPSState *env, DisasContext *ctx)
 
     switch (MASK_MSA_2RF(ctx->opcode)) {
     case OPC_FCLASS_df:
-        gen_helper_msa_fclass_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws);
+        gen_helper_msa_fclass_df(tcg_ctx, uc->cpu_env, tdf, twd, tws);
         break;
     case OPC_FTRUNC_S_df:
-        gen_helper_msa_ftrunc_s_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws);
+        gen_helper_msa_ftrunc_s_df(tcg_ctx, uc->cpu_env, tdf, twd, tws);
         break;
     case OPC_FTRUNC_U_df:
-        gen_helper_msa_ftrunc_u_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws);
+        gen_helper_msa_ftrunc_u_df(tcg_ctx, uc->cpu_env, tdf, twd, tws);
         break;
     case OPC_FSQRT_df:
-        gen_helper_msa_fsqrt_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws);
+        gen_helper_msa_fsqrt_df(tcg_ctx, uc->cpu_env, tdf, twd, tws);
         break;
     case OPC_FRSQRT_df:
-        gen_helper_msa_frsqrt_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws);
+        gen_helper_msa_frsqrt_df(tcg_ctx, uc->cpu_env, tdf, twd, tws);
         break;
     case OPC_FRCP_df:
-        gen_helper_msa_frcp_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws);
+        gen_helper_msa_frcp_df(tcg_ctx, uc->cpu_env, tdf, twd, tws);
         break;
     case OPC_FRINT_df:
-        gen_helper_msa_frint_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws);
+        gen_helper_msa_frint_df(tcg_ctx, uc->cpu_env, tdf, twd, tws);
         break;
     case OPC_FLOG2_df:
-        gen_helper_msa_flog2_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws);
+        gen_helper_msa_flog2_df(tcg_ctx, uc->cpu_env, tdf, twd, tws);
         break;
     case OPC_FEXUPL_df:
-        gen_helper_msa_fexupl_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws);
+        gen_helper_msa_fexupl_df(tcg_ctx, uc->cpu_env, tdf, twd, tws);
         break;
     case OPC_FEXUPR_df:
-        gen_helper_msa_fexupr_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws);
+        gen_helper_msa_fexupr_df(tcg_ctx, uc->cpu_env, tdf, twd, tws);
         break;
     case OPC_FFQL_df:
-        gen_helper_msa_ffql_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws);
+        gen_helper_msa_ffql_df(tcg_ctx, uc->cpu_env, tdf, twd, tws);
         break;
     case OPC_FFQR_df:
-        gen_helper_msa_ffqr_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws);
+        gen_helper_msa_ffqr_df(tcg_ctx, uc->cpu_env, tdf, twd, tws);
         break;
     case OPC_FTINT_S_df:
-        gen_helper_msa_ftint_s_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws);
+        gen_helper_msa_ftint_s_df(tcg_ctx, uc->cpu_env, tdf, twd, tws);
         break;
     case OPC_FTINT_U_df:
-        gen_helper_msa_ftint_u_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws);
+        gen_helper_msa_ftint_u_df(tcg_ctx, uc->cpu_env, tdf, twd, tws);
         break;
     case OPC_FFINT_S_df:
-        gen_helper_msa_ffint_s_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws);
+        gen_helper_msa_ffint_s_df(tcg_ctx, uc->cpu_env, tdf, twd, tws);
         break;
     case OPC_FFINT_U_df:
-        gen_helper_msa_ffint_u_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws);
+        gen_helper_msa_ffint_u_df(tcg_ctx, uc->cpu_env, tdf, twd, tws);
         break;
     }
 
@@ -19522,7 +19566,8 @@ static void gen_msa_2rf(CPUMIPSState *env, DisasContext *ctx)
 static void gen_msa_vec_v(CPUMIPSState *env, DisasContext *ctx)
 {
 #define MASK_MSA_VEC(op)    (MASK_MSA_MINOR(op) | (op & (0x1f << 21)))
-    TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
+    struct uc_struct *uc = ctx->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     uint8_t wt = (ctx->opcode >> 16) & 0x1f;
     uint8_t ws = (ctx->opcode >> 11) & 0x1f;
     uint8_t wd = (ctx->opcode >> 6) & 0x1f;
@@ -19532,25 +19577,25 @@ static void gen_msa_vec_v(CPUMIPSState *env, DisasContext *ctx)
 
     switch (MASK_MSA_VEC(ctx->opcode)) {
     case OPC_AND_V:
-        gen_helper_msa_and_v(tcg_ctx, tcg_ctx->cpu_env, twd, tws, twt);
+        gen_helper_msa_and_v(tcg_ctx, uc->cpu_env, twd, tws, twt);
         break;
     case OPC_OR_V:
-        gen_helper_msa_or_v(tcg_ctx, tcg_ctx->cpu_env, twd, tws, twt);
+        gen_helper_msa_or_v(tcg_ctx, uc->cpu_env, twd, tws, twt);
         break;
     case OPC_NOR_V:
-        gen_helper_msa_nor_v(tcg_ctx, tcg_ctx->cpu_env, twd, tws, twt);
+        gen_helper_msa_nor_v(tcg_ctx, uc->cpu_env, twd, tws, twt);
         break;
     case OPC_XOR_V:
-        gen_helper_msa_xor_v(tcg_ctx, tcg_ctx->cpu_env, twd, tws, twt);
+        gen_helper_msa_xor_v(tcg_ctx, uc->cpu_env, twd, tws, twt);
         break;
     case OPC_BMNZ_V:
-        gen_helper_msa_bmnz_v(tcg_ctx, tcg_ctx->cpu_env, twd, tws, twt);
+        gen_helper_msa_bmnz_v(tcg_ctx, uc->cpu_env, twd, tws, twt);
         break;
     case OPC_BMZ_V:
-        gen_helper_msa_bmz_v(tcg_ctx, tcg_ctx->cpu_env, twd, tws, twt);
+        gen_helper_msa_bmz_v(tcg_ctx, uc->cpu_env, twd, tws, twt);
         break;
     case OPC_BSEL_V:
-        gen_helper_msa_bsel_v(tcg_ctx, tcg_ctx->cpu_env, twd, tws, twt);
+        gen_helper_msa_bsel_v(tcg_ctx, uc->cpu_env, twd, tws, twt);
         break;
     default:
         MIPS_INVAL("MSA instruction");
@@ -19590,7 +19635,8 @@ static void gen_msa_vec(CPUMIPSState *env, DisasContext *ctx)
 
 static void gen_msa(CPUMIPSState *env, DisasContext *ctx)
 {
-    TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
+    struct uc_struct *uc = ctx->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     uint32_t opcode = ctx->opcode;
     check_insn(ctx, ASE_MSA);
     check_msa_access(ctx);
@@ -19651,28 +19697,28 @@ static void gen_msa(CPUMIPSState *env, DisasContext *ctx)
 
             switch (MASK_MSA_MINOR(opcode)) {
             case OPC_LD_B:
-                gen_helper_msa_ld_b(tcg_ctx, tcg_ctx->cpu_env, twd, taddr);
+                gen_helper_msa_ld_b(tcg_ctx, uc->cpu_env, twd, taddr);
                 break;
             case OPC_LD_H:
-                gen_helper_msa_ld_h(tcg_ctx, tcg_ctx->cpu_env, twd, taddr);
+                gen_helper_msa_ld_h(tcg_ctx, uc->cpu_env, twd, taddr);
                 break;
             case OPC_LD_W:
-                gen_helper_msa_ld_w(tcg_ctx, tcg_ctx->cpu_env, twd, taddr);
+                gen_helper_msa_ld_w(tcg_ctx, uc->cpu_env, twd, taddr);
                 break;
             case OPC_LD_D:
-                gen_helper_msa_ld_d(tcg_ctx, tcg_ctx->cpu_env, twd, taddr);
+                gen_helper_msa_ld_d(tcg_ctx, uc->cpu_env, twd, taddr);
                 break;
             case OPC_ST_B:
-                gen_helper_msa_st_b(tcg_ctx, tcg_ctx->cpu_env, twd, taddr);
+                gen_helper_msa_st_b(tcg_ctx, uc->cpu_env, twd, taddr);
                 break;
             case OPC_ST_H:
-                gen_helper_msa_st_h(tcg_ctx, tcg_ctx->cpu_env, twd, taddr);
+                gen_helper_msa_st_h(tcg_ctx, uc->cpu_env, twd, taddr);
                 break;
             case OPC_ST_W:
-                gen_helper_msa_st_w(tcg_ctx, tcg_ctx->cpu_env, twd, taddr);
+                gen_helper_msa_st_w(tcg_ctx, uc->cpu_env, twd, taddr);
                 break;
             case OPC_ST_D:
-                gen_helper_msa_st_d(tcg_ctx, tcg_ctx->cpu_env, twd, taddr);
+                gen_helper_msa_st_d(tcg_ctx, uc->cpu_env, twd, taddr);
                 break;
             }
 
@@ -19702,7 +19748,8 @@ static void hook_insn(CPUMIPSState *env, DisasContext *ctx, bool *insn_need_patc
 
 static void decode_opc(CPUMIPSState *env, DisasContext *ctx, bool *insn_need_patch, int *insn_patch_offset)
 {
-    TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
+    struct uc_struct *uc = ctx->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
 #if defined(TARGET_MIPS64)
     TCGv *cpu_gpr = tcg_ctx->cpu_gpr;
 #endif
@@ -19862,32 +19909,32 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx, bool *insn_need_pat
                     break;
                 case OPC_DVPE:
                     check_insn(ctx, ASE_MT);
-                    gen_helper_dvpe(tcg_ctx, t0, tcg_ctx->cpu_env);
+                    gen_helper_dvpe(tcg_ctx, t0, uc->cpu_env);
                     gen_store_gpr(tcg_ctx, t0, rt);
                     break;
                 case OPC_EVPE:
                     check_insn(ctx, ASE_MT);
-                    gen_helper_evpe(tcg_ctx, t0, tcg_ctx->cpu_env);
+                    gen_helper_evpe(tcg_ctx, t0, uc->cpu_env);
                     gen_store_gpr(tcg_ctx, t0, rt);
                     break;
                 case OPC_DVP:
                     check_insn(ctx, ISA_MIPS32R6);
                     if (ctx->vp) {
-                        gen_helper_dvp(tcg_ctx, t0, tcg_ctx->cpu_env);
+                        gen_helper_dvp(tcg_ctx, t0, uc->cpu_env);
                         gen_store_gpr(tcg_ctx, t0, rt);
                     }
                     break;
                 case OPC_EVP:
                     check_insn(ctx, ISA_MIPS32R6);
                     if (ctx->vp) {
-                        gen_helper_evp(tcg_ctx, t0, tcg_ctx->cpu_env);
+                        gen_helper_evp(tcg_ctx, t0, uc->cpu_env);
                         gen_store_gpr(tcg_ctx, t0, rt);
                     }
                     break;
                 case OPC_DI:
                     check_insn(ctx, ISA_MIPS32R2);
                     save_cpu_state(ctx, 1);
-                    gen_helper_di(tcg_ctx, t0, tcg_ctx->cpu_env);
+                    gen_helper_di(tcg_ctx, t0, uc->cpu_env);
                     gen_store_gpr(tcg_ctx, t0, rt);
                     /* Stop translation as we may have switched
                        the execution mode.  */
@@ -19896,7 +19943,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx, bool *insn_need_pat
                 case OPC_EI:
                     check_insn(ctx, ISA_MIPS32R2);
                     save_cpu_state(ctx, 1);
-                    gen_helper_ei(tcg_ctx, t0, tcg_ctx->cpu_env);
+                    gen_helper_ei(tcg_ctx, t0, uc->cpu_env);
                     gen_store_gpr(tcg_ctx, t0, rt);
                     /* BS_STOP isn't sufficient, we need to ensure we break out
                        of translated code to check for pending interrupts.  */
@@ -20387,6 +20434,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx, bool *insn_need_pat
 void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
 {
     CPUMIPSState *env = cs->env_ptr;
+    struct uc_struct *uc = env->uc;
     DisasContext ctx;
     target_ulong pc_start;
     target_ulong next_page_start;
@@ -20452,7 +20500,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
     // Unicorn: early check to see if the address of this block is the until address
     if (tb->pc == env->uc->addr_end) {
         gen_tb_start(tcg_ctx, tb);
-        gen_helper_wait(tcg_ctx, tcg_ctx->cpu_env);
+        gen_helper_wait(tcg_ctx, uc->cpu_env);
         ctx.bstate = BS_EXCP;
         goto done_generating;
     }
@@ -20481,7 +20529,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
         if (unlikely(cpu_breakpoint_test(cs, ctx.pc, BP_ANY))) {
             save_cpu_state(&ctx, 1);
             ctx.bstate = BS_BRANCH;
-            gen_helper_raise_exception_debug(tcg_ctx, tcg_ctx->cpu_env);
+            gen_helper_raise_exception_debug(tcg_ctx, uc->cpu_env);
             /* The address covered by the breakpoint must be included in
                [tb->pc, tb->pc + tb->size) in order to for it to be
                properly cleared -- thus we increment the PC here so that
@@ -20499,7 +20547,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
 
         // Unicorn: end address tells us to stop emulation
         if (ctx.pc == ctx.uc->addr_end) {
-            gen_helper_wait(tcg_ctx, tcg_ctx->cpu_env);
+            gen_helper_wait(tcg_ctx, uc->cpu_env);
             ctx.bstate = BS_EXCP;
             break;
         } else {
@@ -20509,7 +20557,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
             // Unicorn: save param buffer
             // Unicorn: FIXME: Amend to work with new TCG API
             #if 0
-            if (HOOK_EXISTS(env->uc, UC_HOOK_CODE)) {
+            if (HOOK_EXISTS(uc, UC_HOOK_CODE)) {
                 save_opparam_idx = tcg_ctx->gen_next_op_idx;
             }
             #endif
@@ -20598,7 +20646,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
 #endif
     if (cs->singlestep_enabled && ctx.bstate != BS_BRANCH) {
         save_cpu_state(&ctx, ctx.bstate != BS_EXCP);
-        gen_helper_raise_exception_debug(tcg_ctx, tcg_ctx->cpu_env);
+        gen_helper_raise_exception_debug(tcg_ctx, uc->cpu_env);
     } else {
         switch (ctx.bstate) {
         case BS_STOP:
@@ -20674,11 +20722,8 @@ void mips_tcg_init(struct uc_struct *uc)
     TCGv *cpu_gpr = tcg_ctx->cpu_gpr;
     int i;
 
-    tcg_ctx->cpu_env = tcg_global_reg_new_ptr(uc->tcg_ctx, TCG_AREG0, "env");
-    tcg_ctx->tcg_env = tcg_ctx->cpu_env;
-
     for (i = 0; i < 32; i++) {
-        tcg_ctx->cpu_gpr[i] = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env,
+        tcg_ctx->cpu_gpr[i] = tcg_global_mem_new(tcg_ctx, uc->cpu_env,
                 offsetof(CPUMIPSState, active_tc.gpr[i]),
                 regnames[i]);
     }
@@ -20688,44 +20733,44 @@ void mips_tcg_init(struct uc_struct *uc)
     for (i = 0; i < 32; i++) {
         int off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]);
         tcg_ctx->msa_wr_d[i * 2] =
-                tcg_global_mem_new_i64(tcg_ctx, tcg_ctx->cpu_env, off, msaregnames[i * 2]);
+                tcg_global_mem_new_i64(tcg_ctx, uc->cpu_env, off, msaregnames[i * 2]);
         /* The scalar floating-point unit (FPU) registers are mapped on
          * the MSA vector registers. */
         tcg_ctx->fpu_f64[i] = tcg_ctx->msa_wr_d[i * 2];
         off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]);
         tcg_ctx->msa_wr_d[i * 2 + 1] =
-                tcg_global_mem_new_i64(tcg_ctx, tcg_ctx->cpu_env, off, msaregnames[i * 2 + 1]);
+                tcg_global_mem_new_i64(tcg_ctx, uc->cpu_env, off, msaregnames[i * 2 + 1]);
     }
 
-    tcg_ctx->cpu_PC = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env,
+    tcg_ctx->cpu_PC = tcg_global_mem_new(tcg_ctx, uc->cpu_env,
                                 offsetof(CPUMIPSState, active_tc.PC), "PC");
 
     for (i = 0; i < MIPS_DSP_ACC; i++) {
-        tcg_ctx->cpu_HI[i] = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env,
+        tcg_ctx->cpu_HI[i] = tcg_global_mem_new(tcg_ctx, uc->cpu_env,
                 offsetof(CPUMIPSState, active_tc.HI[i]),
                 regnames_HI[i]);
-        tcg_ctx->cpu_LO[i] = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env,
+        tcg_ctx->cpu_LO[i] = tcg_global_mem_new(tcg_ctx, uc->cpu_env,
                 offsetof(CPUMIPSState, active_tc.LO[i]),
                 regnames_LO[i]);
     }
 
-    tcg_ctx->cpu_dspctrl = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env,
+    tcg_ctx->cpu_dspctrl = tcg_global_mem_new(tcg_ctx, uc->cpu_env,
                                      offsetof(CPUMIPSState, active_tc.DSPControl),
                                      "DSPControl");
 
-    tcg_ctx->bcond = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env,
+    tcg_ctx->bcond = tcg_global_mem_new(tcg_ctx, uc->cpu_env,
                                offsetof(CPUMIPSState, bcond), "bcond");
 
-    tcg_ctx->btarget = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env,
+    tcg_ctx->btarget = tcg_global_mem_new(tcg_ctx, uc->cpu_env,
                                  offsetof(CPUMIPSState, btarget), "btarget");
 
-    tcg_ctx->hflags = tcg_global_mem_new_i32(tcg_ctx, tcg_ctx->cpu_env,
+    tcg_ctx->hflags = tcg_global_mem_new_i32(tcg_ctx, uc->cpu_env,
                                     offsetof(CPUMIPSState, hflags), "hflags");
 
-    //tcg_ctx->fpu_fcr0 = tcg_global_mem_new_i32(tcg_ctx, tcg_ctx->cpu_env,
+    //tcg_ctx->fpu_fcr0 = tcg_global_mem_new_i32(tcg_ctx, uc->cpu_env,
     //                                  offsetof(CPUMIPSState, active_fpu.fcr0),
     //                                  "fcr0");
-    tcg_ctx->fpu_fcr31 = tcg_global_mem_new_i32(tcg_ctx, tcg_ctx->cpu_env,
+    tcg_ctx->fpu_fcr31 = tcg_global_mem_new_i32(tcg_ctx, uc->cpu_env,
                                        offsetof(CPUMIPSState, active_fpu.fcr31),
                                        "fcr31");
     uc->init_tcg = true;
diff --git a/qemu/target/sparc/translate.c b/qemu/target/sparc/translate.c
index b2d9e778..7f49bf06 100644
--- a/qemu/target/sparc/translate.c
+++ b/qemu/target/sparc/translate.c
@@ -201,28 +201,31 @@ static TCGv_i64 gen_dest_fpr_D(DisasContext *dc, unsigned int dst)
 
 static void gen_op_load_fpr_QT0(DisasContext *dc, unsigned int src)
 {
-    TCGContext *tcg_ctx = dc->uc->tcg_ctx;
-    tcg_gen_st_i64(tcg_ctx, tcg_ctx->cpu_fpr[src / 2], tcg_ctx->cpu_env, offsetof(CPUSPARCState, qt0) +
+    struct uc_struct *uc = dc->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
+    tcg_gen_st_i64(tcg_ctx, tcg_ctx->cpu_fpr[src / 2], uc->cpu_env, offsetof(CPUSPARCState, qt0) +
                    offsetof(CPU_QuadU, ll.upper));
-    tcg_gen_st_i64(tcg_ctx, tcg_ctx->cpu_fpr[src/2 + 1], tcg_ctx->cpu_env, offsetof(CPUSPARCState, qt0) +
+    tcg_gen_st_i64(tcg_ctx, tcg_ctx->cpu_fpr[src/2 + 1], uc->cpu_env, offsetof(CPUSPARCState, qt0) +
                    offsetof(CPU_QuadU, ll.lower));
 }
 
 static void gen_op_load_fpr_QT1(DisasContext *dc, unsigned int src)
 {
-    TCGContext *tcg_ctx = dc->uc->tcg_ctx;
-    tcg_gen_st_i64(tcg_ctx, tcg_ctx->cpu_fpr[src / 2], tcg_ctx->cpu_env, offsetof(CPUSPARCState, qt1) +
+    struct uc_struct *uc = dc->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
+    tcg_gen_st_i64(tcg_ctx, tcg_ctx->cpu_fpr[src / 2], uc->cpu_env, offsetof(CPUSPARCState, qt1) +
                    offsetof(CPU_QuadU, ll.upper));
-    tcg_gen_st_i64(tcg_ctx, tcg_ctx->cpu_fpr[src/2 + 1], tcg_ctx->cpu_env, offsetof(CPUSPARCState, qt1) +
+    tcg_gen_st_i64(tcg_ctx, tcg_ctx->cpu_fpr[src/2 + 1], uc->cpu_env, offsetof(CPUSPARCState, qt1) +
                    offsetof(CPU_QuadU, ll.lower));
 }
 
 static void gen_op_store_QT0_fpr(DisasContext *dc, unsigned int dst)
 {
-    TCGContext *tcg_ctx = dc->uc->tcg_ctx;
-    tcg_gen_ld_i64(tcg_ctx, tcg_ctx->cpu_fpr[dst / 2], tcg_ctx->cpu_env, offsetof(CPUSPARCState, qt0) +
+    struct uc_struct *uc = dc->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
+    tcg_gen_ld_i64(tcg_ctx, tcg_ctx->cpu_fpr[dst / 2], uc->cpu_env, offsetof(CPUSPARCState, qt0) +
                    offsetof(CPU_QuadU, ll.upper));
-    tcg_gen_ld_i64(tcg_ctx, tcg_ctx->cpu_fpr[dst/2 + 1], tcg_ctx->cpu_env, offsetof(CPUSPARCState, qt0) +
+    tcg_gen_ld_i64(tcg_ctx, tcg_ctx->cpu_fpr[dst/2 + 1], uc->cpu_env, offsetof(CPUSPARCState, qt0) +
                    offsetof(CPU_QuadU, ll.lower));
 }
 
@@ -480,7 +483,8 @@ static TCGv_i32 gen_sub32_carry32(DisasContext *dc)
 static void gen_op_addx_int(DisasContext *dc, TCGv dst, TCGv src1,
                             TCGv src2, int update_cc)
 {
-    TCGContext *tcg_ctx = dc->uc->tcg_ctx;
+    struct uc_struct *uc = dc->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv_i32 carry_32;
     TCGv carry;
 
@@ -520,7 +524,7 @@ static void gen_op_addx_int(DisasContext *dc, TCGv dst, TCGv src1,
     default:
         /* We need external help to produce the carry.  */
         carry_32 = tcg_temp_new_i32(tcg_ctx);
-        gen_helper_compute_C_icc(tcg_ctx, carry_32, tcg_ctx->cpu_env);
+        gen_helper_compute_C_icc(tcg_ctx, carry_32, uc->cpu_env);
         break;
     }
 
@@ -580,7 +584,8 @@ static inline void gen_op_sub_cc(DisasContext *dc, TCGv dst, TCGv src1, TCGv src
 static void gen_op_subx_int(DisasContext *dc, TCGv dst, TCGv src1,
                             TCGv src2, int update_cc)
 {
-    TCGContext *tcg_ctx = dc->uc->tcg_ctx;
+    struct uc_struct *uc = dc->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv_i32 carry_32;
     TCGv carry;
 
@@ -620,7 +625,7 @@ static void gen_op_subx_int(DisasContext *dc, TCGv dst, TCGv src1,
     default:
         /* We need external help to produce the carry.  */
         carry_32 = tcg_temp_new_i32(tcg_ctx);
-        gen_helper_compute_C_icc(tcg_ctx, carry_32, tcg_ctx->cpu_env);
+        gen_helper_compute_C_icc(tcg_ctx, carry_32, uc->cpu_env);
         break;
     }
 
@@ -1136,10 +1141,11 @@ static inline void save_npc(DisasContext *dc)
 
 static inline void update_psr(DisasContext *dc)
 {
-    TCGContext *tcg_ctx = dc->uc->tcg_ctx;
+    struct uc_struct *uc = dc->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     if (dc->cc_op != CC_OP_FLAGS) {
         dc->cc_op = CC_OP_FLAGS;
-        gen_helper_compute_psr(tcg_ctx, tcg_ctx->cpu_env);
+        gen_helper_compute_psr(tcg_ctx, uc->cpu_env);
     }
 }
 
@@ -1153,21 +1159,23 @@ static inline void save_state(DisasContext *dc)
 static void gen_exception(DisasContext *dc, int which)
 {
     TCGv_i32 t;
-    TCGContext *tcg_ctx = dc->uc->tcg_ctx;
+    struct uc_struct *uc = dc->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
 
     save_state(dc);
     t = tcg_const_i32(tcg_ctx, which);
-    gen_helper_raise_exception(tcg_ctx, tcg_ctx->cpu_env, t);
+    gen_helper_raise_exception(tcg_ctx, uc->cpu_env, t);
     tcg_temp_free_i32(tcg_ctx, t);
     dc->is_br = 1;
 }
 
 static void gen_check_align(DisasContext *dc, TCGv addr, int mask)
 {
-    TCGContext *tcg_ctx = dc->uc->tcg_ctx;
+    struct uc_struct *uc = dc->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv_i32 r_mask = tcg_const_i32(tcg_ctx, mask);
 
-    gen_helper_check_align(tcg_ctx, tcg_ctx->cpu_env, addr, r_mask);
+    gen_helper_check_align(tcg_ctx, uc->cpu_env, addr, r_mask);
     tcg_temp_free_i32(tcg_ctx, r_mask);
 }
 
@@ -1205,7 +1213,8 @@ static void free_compare(TCGContext *tcg_ctx, DisasCompare *cmp)
 
 static void gen_compare(DisasContext *dc, DisasCompare *cmp, bool xcc, unsigned int cond)
 {
-    TCGContext *tcg_ctx = dc->uc->tcg_ctx;
+    struct uc_struct *uc = dc->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     static int subcc_cond[16] = {
         TCG_COND_NEVER,
         TCG_COND_EQ,
@@ -1311,7 +1320,7 @@ static void gen_compare(DisasContext *dc, DisasCompare *cmp, bool xcc, unsigned
 
     default:
     do_dynamic:
-        gen_helper_compute_psr(tcg_ctx, tcg_ctx->cpu_env);
+        gen_helper_compute_psr(tcg_ctx, uc->cpu_env);
         dc->cc_op = CC_OP_FLAGS;
         /* FALLTHRU */
 
@@ -1631,130 +1640,142 @@ static void do_branch_reg(DisasContext *dc, int32_t offset, uint32_t insn,
 
 static inline void gen_op_fcmps(DisasContext *dc, int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2)
 {
-    TCGContext *tcg_ctx = dc->uc->tcg_ctx;
+    struct uc_struct *uc = dc->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
+
     switch (fccno) {
     case 0:
         gen_helper_fcmps(tcg_ctx, tcg_ctx->cpu_fsr,
-                         tcg_ctx->cpu_env, r_rs1, r_rs2);
+                         uc->cpu_env, r_rs1, r_rs2);
         break;
     case 1:
         gen_helper_fcmps_fcc1(tcg_ctx, tcg_ctx->cpu_fsr,
-                              tcg_ctx->cpu_env, r_rs1, r_rs2);
+                              uc->cpu_env, r_rs1, r_rs2);
         break;
     case 2:
         gen_helper_fcmps_fcc2(tcg_ctx, tcg_ctx->cpu_fsr,
-                              tcg_ctx->cpu_env, r_rs1, r_rs2);
+                              uc->cpu_env, r_rs1, r_rs2);
         break;
     case 3:
         gen_helper_fcmps_fcc3(tcg_ctx, tcg_ctx->cpu_fsr,
-                              tcg_ctx->cpu_env, r_rs1, r_rs2);
+                              uc->cpu_env, r_rs1, r_rs2);
         break;
     }
 }
 
 static inline void gen_op_fcmpd(DisasContext *dc, int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
 {
-    TCGContext *tcg_ctx = dc->uc->tcg_ctx;
+    struct uc_struct *uc = dc->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
+
     switch (fccno) {
     case 0:
         gen_helper_fcmpd(tcg_ctx, tcg_ctx->cpu_fsr,
-                         tcg_ctx->cpu_env, r_rs1, r_rs2);
+                         uc->cpu_env, r_rs1, r_rs2);
         break;
     case 1:
         gen_helper_fcmpd_fcc1(tcg_ctx, tcg_ctx->cpu_fsr,
-                              tcg_ctx->cpu_env, r_rs1, r_rs2);
+                              uc->cpu_env, r_rs1, r_rs2);
         break;
     case 2:
         gen_helper_fcmpd_fcc2(tcg_ctx, tcg_ctx->cpu_fsr,
-                              tcg_ctx->cpu_env, r_rs1, r_rs2);
+                              uc->cpu_env, r_rs1, r_rs2);
         break;
     case 3:
         gen_helper_fcmpd_fcc3(tcg_ctx, tcg_ctx->cpu_fsr,
-                              tcg_ctx->cpu_env, r_rs1, r_rs2);
+                              uc->cpu_env, r_rs1, r_rs2);
         break;
     }
 }
 
 static inline void gen_op_fcmpq(DisasContext *dc, int fccno)
 {
-    TCGContext *tcg_ctx = dc->uc->tcg_ctx;
+    struct uc_struct *uc = dc->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
+
     switch (fccno) {
     case 0:
-        gen_helper_fcmpq(tcg_ctx, tcg_ctx->cpu_fsr, tcg_ctx->cpu_env);
+        gen_helper_fcmpq(tcg_ctx, tcg_ctx->cpu_fsr, uc->cpu_env);
         break;
     case 1:
-        gen_helper_fcmpq_fcc1(tcg_ctx, tcg_ctx->cpu_fsr, tcg_ctx->cpu_env);
+        gen_helper_fcmpq_fcc1(tcg_ctx, tcg_ctx->cpu_fsr, uc->cpu_env);
         break;
     case 2:
-        gen_helper_fcmpq_fcc2(tcg_ctx, tcg_ctx->cpu_fsr, tcg_ctx->cpu_env);
+        gen_helper_fcmpq_fcc2(tcg_ctx, tcg_ctx->cpu_fsr, uc->cpu_env);
         break;
     case 3:
-        gen_helper_fcmpq_fcc3(tcg_ctx, tcg_ctx->cpu_fsr, tcg_ctx->cpu_env);
+        gen_helper_fcmpq_fcc3(tcg_ctx, tcg_ctx->cpu_fsr, uc->cpu_env);
         break;
     }
 }
 
 static inline void gen_op_fcmpes(DisasContext *dc, int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2)
 {
-    TCGContext *tcg_ctx = dc->uc->tcg_ctx;
+    struct uc_struct *uc = dc->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
+
     switch (fccno) {
     case 0:
         gen_helper_fcmpes(tcg_ctx, tcg_ctx->cpu_fsr,
-                          tcg_ctx->cpu_env, r_rs1, r_rs2);
+                          uc->cpu_env, r_rs1, r_rs2);
         break;
     case 1:
         gen_helper_fcmpes_fcc1(tcg_ctx, tcg_ctx->cpu_fsr,
-                               tcg_ctx->cpu_env, r_rs1, r_rs2);
+                               uc->cpu_env, r_rs1, r_rs2);
         break;
     case 2:
         gen_helper_fcmpes_fcc2(tcg_ctx, tcg_ctx->cpu_fsr,
-                               tcg_ctx->cpu_env, r_rs1, r_rs2);
+                               uc->cpu_env, r_rs1, r_rs2);
         break;
     case 3:
         gen_helper_fcmpes_fcc3(tcg_ctx, tcg_ctx->cpu_fsr,
-                               tcg_ctx->cpu_env, r_rs1, r_rs2);
+                               uc->cpu_env, r_rs1, r_rs2);
         break;
     }
 }
 
 static inline void gen_op_fcmped(DisasContext *dc, int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
 {
-    TCGContext *tcg_ctx = dc->uc->tcg_ctx;
+    struct uc_struct *uc = dc->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
+
     switch (fccno) {
     case 0:
         gen_helper_fcmped(tcg_ctx, tcg_ctx->cpu_fsr,
-                          tcg_ctx->cpu_env, r_rs1, r_rs2);
+                          uc->cpu_env, r_rs1, r_rs2);
         break;
     case 1:
         gen_helper_fcmped_fcc1(tcg_ctx, tcg_ctx->cpu_fsr,
-                               tcg_ctx->cpu_env, r_rs1, r_rs2);
+                               uc->cpu_env, r_rs1, r_rs2);
         break;
     case 2:
         gen_helper_fcmped_fcc2(tcg_ctx, tcg_ctx->cpu_fsr,
-                               tcg_ctx->cpu_env, r_rs1, r_rs2);
+                               uc->cpu_env, r_rs1, r_rs2);
         break;
     case 3:
         gen_helper_fcmped_fcc3(tcg_ctx, tcg_ctx->cpu_fsr,
-                               tcg_ctx->cpu_env, r_rs1, r_rs2);
+                               uc->cpu_env, r_rs1, r_rs2);
         break;
     }
 }
 
 static inline void gen_op_fcmpeq(DisasContext *dc, int fccno)
 {
-    TCGContext *tcg_ctx = dc->uc->tcg_ctx;
+    struct uc_struct *uc = dc->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
+
     switch (fccno) {
     case 0:
-        gen_helper_fcmpeq(tcg_ctx, tcg_ctx->cpu_fsr, tcg_ctx->cpu_env);
+        gen_helper_fcmpeq(tcg_ctx, tcg_ctx->cpu_fsr, uc->cpu_env);
         break;
     case 1:
-        gen_helper_fcmpeq_fcc1(tcg_ctx, tcg_ctx->cpu_fsr, tcg_ctx->cpu_env);
+        gen_helper_fcmpeq_fcc1(tcg_ctx, tcg_ctx->cpu_fsr, uc->cpu_env);
         break;
     case 2:
-        gen_helper_fcmpeq_fcc2(tcg_ctx, tcg_ctx->cpu_fsr, tcg_ctx->cpu_env);
+        gen_helper_fcmpeq_fcc2(tcg_ctx, tcg_ctx->cpu_fsr, uc->cpu_env);
         break;
     case 3:
-        gen_helper_fcmpeq_fcc3(tcg_ctx, tcg_ctx->cpu_fsr, tcg_ctx->cpu_env);
+        gen_helper_fcmpeq_fcc3(tcg_ctx, tcg_ctx->cpu_fsr, uc->cpu_env);
         break;
     }
 }
@@ -1763,40 +1784,52 @@ static inline void gen_op_fcmpeq(DisasContext *dc, int fccno)
 
 static inline void gen_op_fcmps(DisasContext *dc, int fccno, TCGv r_rs1, TCGv r_rs2)
 {
-    TCGContext *tcg_ctx = dc->uc->tcg_ctx;
-    gen_helper_fcmps(tcg_ctx, tcg_ctx->cpu_fsr, tcg_ctx->cpu_env, r_rs1, r_rs2);
+    struct uc_struct *uc = dc->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
+
+    gen_helper_fcmps(tcg_ctx, tcg_ctx->cpu_fsr, uc->cpu_env, r_rs1, r_rs2);
 }
 
 static inline void gen_op_fcmpd(DisasContext *dc, int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
 {
-    TCGContext *tcg_ctx = dc->uc->tcg_ctx;
+    struct uc_struct *uc = dc->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
+
     gen_helper_fcmpd(tcg_ctx, tcg_ctx->cpu_fsr,
-                     tcg_ctx->cpu_env, r_rs1, r_rs2);
+                     uc->cpu_env, r_rs1, r_rs2);
 }
 
 static inline void gen_op_fcmpq(DisasContext *dc, int fccno)
 {
-    TCGContext *tcg_ctx = dc->uc->tcg_ctx;
-    gen_helper_fcmpq(tcg_ctx, tcg_ctx->cpu_fsr, tcg_ctx->cpu_env);
+    struct uc_struct *uc = dc->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
+
+    gen_helper_fcmpq(tcg_ctx, tcg_ctx->cpu_fsr, uc->cpu_env);
 }
 
 static inline void gen_op_fcmpes(DisasContext *dc, int fccno, TCGv r_rs1, TCGv r_rs2)
 {
-    TCGContext *tcg_ctx = dc->uc->tcg_ctx;
+    struct uc_struct *uc = dc->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
+
     gen_helper_fcmpes(tcg_ctx, tcg_ctx->cpu_fsr,
-                      tcg_ctx->cpu_env, r_rs1, r_rs2);
+                      uc->cpu_env, r_rs1, r_rs2);
 }
 
 static inline void gen_op_fcmped(DisasContext *dc, int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
 {
-    TCGContext *tcg_ctx = dc->uc->tcg_ctx;
-    gen_helper_fcmped(tcg_ctx, tcg_ctx->cpu_fsr, tcg_ctx->cpu_env, r_rs1, r_rs2);
+    struct uc_struct *uc = dc->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
+
+    gen_helper_fcmped(tcg_ctx, tcg_ctx->cpu_fsr, uc->cpu_env, r_rs1, r_rs2);
 }
 
 static inline void gen_op_fcmpeq(DisasContext *dc, int fccno)
 {
-    TCGContext *tcg_ctx = dc->uc->tcg_ctx;
-    gen_helper_fcmpeq(tcg_ctx, tcg_ctx->cpu_fsr, tcg_ctx->cpu_env);
+    struct uc_struct *uc = dc->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
+
+    gen_helper_fcmpeq(tcg_ctx, tcg_ctx->cpu_fsr, uc->cpu_env);
 }
 #endif
 
@@ -1829,14 +1862,15 @@ static inline void gen_op_clear_ieee_excp_and_FTT(DisasContext *dc)
 static inline void gen_fop_FF(DisasContext *dc, int rd, int rs,
                               void (*gen)(TCGContext *tcg_ctx, TCGv_i32, TCGv_ptr, TCGv_i32))
 {
-    TCGContext *tcg_ctx = dc->uc->tcg_ctx;
+    struct uc_struct *uc = dc->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv_i32 dst, src;
 
     src = gen_load_fpr_F(dc, rs);
     dst = gen_dest_fpr_F(dc);
 
-    gen(tcg_ctx, dst, tcg_ctx->cpu_env, src);
-    gen_helper_check_ieee_exceptions(tcg_ctx, tcg_ctx->cpu_fsr, tcg_ctx->cpu_env);
+    gen(tcg_ctx, dst, uc->cpu_env, src);
+    gen_helper_check_ieee_exceptions(tcg_ctx, tcg_ctx->cpu_fsr, uc->cpu_env);
 
     gen_store_fpr_F(dc, rd, dst);
 }
@@ -1858,15 +1892,16 @@ static inline void gen_ne_fop_FF(DisasContext *dc, int rd, int rs,
 static inline void gen_fop_FFF(DisasContext *dc, int rd, int rs1, int rs2,
                         void (*gen)(TCGContext *tcg_ctx, TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32))
 {
-    TCGContext *tcg_ctx = dc->uc->tcg_ctx;
+    struct uc_struct *uc = dc->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv_i32 dst, src1, src2;
 
     src1 = gen_load_fpr_F(dc, rs1);
     src2 = gen_load_fpr_F(dc, rs2);
     dst = gen_dest_fpr_F(dc);
 
-    gen(tcg_ctx, dst, tcg_ctx->cpu_env, src1, src2);
-    gen_helper_check_ieee_exceptions(tcg_ctx, tcg_ctx->cpu_fsr, tcg_ctx->cpu_env);
+    gen(tcg_ctx, dst, uc->cpu_env, src1, src2);
+    gen_helper_check_ieee_exceptions(tcg_ctx, tcg_ctx->cpu_fsr, uc->cpu_env);
 
     gen_store_fpr_F(dc, rd, dst);
 }
@@ -1891,14 +1926,15 @@ static inline void gen_ne_fop_FFF(DisasContext *dc, int rd, int rs1, int rs2,
 static inline void gen_fop_DD(DisasContext *dc, int rd, int rs,
                               void (*gen)(TCGContext *tcg_ctx, TCGv_i64, TCGv_ptr, TCGv_i64))
 {
-    TCGContext *tcg_ctx = dc->uc->tcg_ctx;
+    struct uc_struct *uc = dc->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv_i64 dst, src;
 
     src = gen_load_fpr_D(dc, rs);
     dst = gen_dest_fpr_D(dc, rd);
 
-    gen(tcg_ctx, dst, tcg_ctx->cpu_env, src);
-    gen_helper_check_ieee_exceptions(tcg_ctx, tcg_ctx->cpu_fsr, tcg_ctx->cpu_env);
+    gen(tcg_ctx, dst, uc->cpu_env, src);
+    gen_helper_check_ieee_exceptions(tcg_ctx, tcg_ctx->cpu_fsr, uc->cpu_env);
 
     gen_store_fpr_D(dc, rd, dst);
 }
@@ -1922,15 +1958,16 @@ static inline void gen_ne_fop_DD(DisasContext *dc, int rd, int rs,
 static inline void gen_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2,
                         void (*gen)(TCGContext *tcg_ctx, TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64))
 {
-    TCGContext *tcg_ctx = dc->uc->tcg_ctx;
+    struct uc_struct *uc = dc->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv_i64 dst, src1, src2;
 
     src1 = gen_load_fpr_D(dc, rs1);
     src2 = gen_load_fpr_D(dc, rs2);
     dst = gen_dest_fpr_D(dc, rd);
 
-    gen(tcg_ctx, dst, tcg_ctx->cpu_env, src1, src2);
-    gen_helper_check_ieee_exceptions(tcg_ctx, tcg_ctx->cpu_fsr, tcg_ctx->cpu_env);
+    gen(tcg_ctx, dst, uc->cpu_env, src1, src2);
+    gen_helper_check_ieee_exceptions(tcg_ctx, tcg_ctx->cpu_fsr, uc->cpu_env);
 
     gen_store_fpr_D(dc, rd, dst);
 }
@@ -1986,11 +2023,12 @@ static inline void gen_ne_fop_DDDD(DisasContext *dc, int rd, int rs1, int rs2,
 static inline void gen_fop_QQ(DisasContext *dc, int rd, int rs,
                               void (*gen)(TCGContext *tcg_ctx, TCGv_ptr))
 {
-    TCGContext *tcg_ctx = dc->uc->tcg_ctx;
+    struct uc_struct *uc = dc->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     gen_op_load_fpr_QT1(dc, QFPREG(rs));
 
-    gen(tcg_ctx, tcg_ctx->cpu_env);
-    gen_helper_check_ieee_exceptions(tcg_ctx, tcg_ctx->cpu_fsr, tcg_ctx->cpu_env);
+    gen(tcg_ctx, uc->cpu_env);
+    gen_helper_check_ieee_exceptions(tcg_ctx, tcg_ctx->cpu_fsr, uc->cpu_env);
 
     gen_op_store_QT0_fpr(dc, QFPREG(rd));
     gen_update_fprs_dirty(dc, QFPREG(rd));
@@ -2000,10 +2038,11 @@ static inline void gen_fop_QQ(DisasContext *dc, int rd, int rs,
 static inline void gen_ne_fop_QQ(DisasContext *dc, int rd, int rs,
                                  void (*gen)(TCGContext *tcg_ctx, TCGv_ptr))
 {
-    TCGContext *tcg_ctx = dc->uc->tcg_ctx;
+    struct uc_struct *uc = dc->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     gen_op_load_fpr_QT1(dc, QFPREG(rs));
 
-    gen(tcg_ctx, tcg_ctx->cpu_env);
+    gen(tcg_ctx, uc->cpu_env);
 
     gen_op_store_QT0_fpr(dc, QFPREG(rd));
     gen_update_fprs_dirty(dc, QFPREG(rd));
@@ -2013,12 +2052,13 @@ static inline void gen_ne_fop_QQ(DisasContext *dc, int rd, int rs,
 static inline void gen_fop_QQQ(DisasContext *dc, int rd, int rs1, int rs2,
                                void (*gen)(TCGContext *tcg_ctx, TCGv_ptr))
 {
-    TCGContext *tcg_ctx = dc->uc->tcg_ctx;
+    struct uc_struct *uc = dc->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     gen_op_load_fpr_QT0(dc, QFPREG(rs1));
     gen_op_load_fpr_QT1(dc, QFPREG(rs2));
 
-    gen(tcg_ctx, tcg_ctx->cpu_env);
-    gen_helper_check_ieee_exceptions(tcg_ctx, tcg_ctx->cpu_fsr, tcg_ctx->cpu_env);
+    gen(tcg_ctx, uc->cpu_env);
+    gen_helper_check_ieee_exceptions(tcg_ctx, tcg_ctx->cpu_fsr, uc->cpu_env);
 
     gen_op_store_QT0_fpr(dc, QFPREG(rd));
     gen_update_fprs_dirty(dc, QFPREG(rd));
@@ -2027,7 +2067,8 @@ static inline void gen_fop_QQQ(DisasContext *dc, int rd, int rs1, int rs2,
 static inline void gen_fop_DFF(DisasContext *dc, int rd, int rs1, int rs2,
                         void (*gen)(TCGContext *tcg_ctx, TCGv_i64, TCGv_ptr, TCGv_i32, TCGv_i32))
 {
-    TCGContext *tcg_ctx = dc->uc->tcg_ctx;
+    struct uc_struct *uc = dc->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv_i64 dst;
     TCGv_i32 src1, src2;
 
@@ -2035,8 +2076,8 @@ static inline void gen_fop_DFF(DisasContext *dc, int rd, int rs1, int rs2,
     src2 = gen_load_fpr_F(dc, rs2);
     dst = gen_dest_fpr_D(dc, rd);
 
-    gen(tcg_ctx, dst, tcg_ctx->cpu_env, src1, src2);
-    gen_helper_check_ieee_exceptions(tcg_ctx, tcg_ctx->cpu_fsr, tcg_ctx->cpu_env);
+    gen(tcg_ctx, dst, uc->cpu_env, src1, src2);
+    gen_helper_check_ieee_exceptions(tcg_ctx, tcg_ctx->cpu_fsr, uc->cpu_env);
 
     gen_store_fpr_D(dc, rd, dst);
 }
@@ -2044,14 +2085,15 @@ static inline void gen_fop_DFF(DisasContext *dc, int rd, int rs1, int rs2,
 static inline void gen_fop_QDD(DisasContext *dc, int rd, int rs1, int rs2,
                                void (*gen)(TCGContext *tcg_ctx, TCGv_ptr, TCGv_i64, TCGv_i64))
 {
-    TCGContext *tcg_ctx = dc->uc->tcg_ctx;
+    struct uc_struct *uc = dc->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv_i64 src1, src2;
 
     src1 = gen_load_fpr_D(dc, rs1);
     src2 = gen_load_fpr_D(dc, rs2);
 
-    gen(tcg_ctx, tcg_ctx->cpu_env, src1, src2);
-    gen_helper_check_ieee_exceptions(tcg_ctx, tcg_ctx->cpu_fsr, tcg_ctx->cpu_env);
+    gen(tcg_ctx, uc->cpu_env, src1, src2);
+    gen_helper_check_ieee_exceptions(tcg_ctx, tcg_ctx->cpu_fsr, uc->cpu_env);
 
     gen_op_store_QT0_fpr(dc, QFPREG(rd));
     gen_update_fprs_dirty(dc, QFPREG(rd));
@@ -2061,15 +2103,16 @@ static inline void gen_fop_QDD(DisasContext *dc, int rd, int rs1, int rs2,
 static inline void gen_fop_DF(DisasContext *dc, int rd, int rs,
                               void (*gen)(TCGContext *tcg_ctx, TCGv_i64, TCGv_ptr, TCGv_i32))
 {
-    TCGContext *tcg_ctx = dc->uc->tcg_ctx;
+    struct uc_struct *uc = dc->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv_i64 dst;
     TCGv_i32 src;
 
     src = gen_load_fpr_F(dc, rs);
     dst = gen_dest_fpr_D(dc, rd);
 
-    gen(tcg_ctx, dst, tcg_ctx->cpu_env, src);
-    gen_helper_check_ieee_exceptions(tcg_ctx, tcg_ctx->cpu_fsr, tcg_ctx->cpu_env);
+    gen(tcg_ctx, dst, uc->cpu_env, src);
+    gen_helper_check_ieee_exceptions(tcg_ctx, tcg_ctx->cpu_fsr, uc->cpu_env);
 
     gen_store_fpr_D(dc, rd, dst);
 }
@@ -2078,14 +2121,15 @@ static inline void gen_fop_DF(DisasContext *dc, int rd, int rs,
 static inline void gen_ne_fop_DF(DisasContext *dc, int rd, int rs,
                                  void (*gen)(TCGContext *tcg_ctx, TCGv_i64, TCGv_ptr, TCGv_i32))
 {
-    TCGContext *tcg_ctx = dc->uc->tcg_ctx;
+    struct uc_struct *uc = dc->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv_i64 dst;
     TCGv_i32 src;
 
     src = gen_load_fpr_F(dc, rs);
     dst = gen_dest_fpr_D(dc, rd);
 
-    gen(tcg_ctx, dst, tcg_ctx->cpu_env, src);
+    gen(tcg_ctx, dst, uc->cpu_env, src);
 
     gen_store_fpr_D(dc, rd, dst);
 }
@@ -2093,15 +2137,16 @@ static inline void gen_ne_fop_DF(DisasContext *dc, int rd, int rs,
 static inline void gen_fop_FD(DisasContext *dc, int rd, int rs,
                               void (*gen)(TCGContext *tcg_ctx, TCGv_i32, TCGv_ptr, TCGv_i64))
 {
-    TCGContext *tcg_ctx = dc->uc->tcg_ctx;
+    struct uc_struct *uc = dc->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv_i32 dst;
     TCGv_i64 src;
 
     src = gen_load_fpr_D(dc, rs);
     dst = gen_dest_fpr_F(dc);
 
-    gen(tcg_ctx, dst, tcg_ctx->cpu_env, src);
-    gen_helper_check_ieee_exceptions(tcg_ctx, tcg_ctx->cpu_fsr, tcg_ctx->cpu_env);
+    gen(tcg_ctx, dst, uc->cpu_env, src);
+    gen_helper_check_ieee_exceptions(tcg_ctx, tcg_ctx->cpu_fsr, uc->cpu_env);
 
     gen_store_fpr_F(dc, rd, dst);
 }
@@ -2109,14 +2154,15 @@ static inline void gen_fop_FD(DisasContext *dc, int rd, int rs,
 static inline void gen_fop_FQ(DisasContext *dc, int rd, int rs,
                               void (*gen)(TCGContext *tcg_ctx, TCGv_i32, TCGv_ptr))
 {
-    TCGContext *tcg_ctx = dc->uc->tcg_ctx;
+    struct uc_struct *uc = dc->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv_i32 dst;
 
     gen_op_load_fpr_QT1(dc, QFPREG(rs));
     dst = gen_dest_fpr_F(dc);
 
-    gen(tcg_ctx, dst, tcg_ctx->cpu_env);
-    gen_helper_check_ieee_exceptions(tcg_ctx, tcg_ctx->cpu_fsr, tcg_ctx->cpu_env);
+    gen(tcg_ctx, dst, uc->cpu_env);
+    gen_helper_check_ieee_exceptions(tcg_ctx, tcg_ctx->cpu_fsr, uc->cpu_env);
 
     gen_store_fpr_F(dc, rd, dst);
 }
@@ -2124,14 +2170,15 @@ static inline void gen_fop_FQ(DisasContext *dc, int rd, int rs,
 static inline void gen_fop_DQ(DisasContext *dc, int rd, int rs,
                               void (*gen)(TCGContext *tcg_ctx, TCGv_i64, TCGv_ptr))
 {
-    TCGContext *tcg_ctx = dc->uc->tcg_ctx;
+    struct uc_struct *uc = dc->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv_i64 dst;
 
     gen_op_load_fpr_QT1(dc, QFPREG(rs));
     dst = gen_dest_fpr_D(dc, rd);
 
-    gen(tcg_ctx, dst, tcg_ctx->cpu_env);
-    gen_helper_check_ieee_exceptions(tcg_ctx, tcg_ctx->cpu_fsr, tcg_ctx->cpu_env);
+    gen(tcg_ctx, dst, uc->cpu_env);
+    gen_helper_check_ieee_exceptions(tcg_ctx, tcg_ctx->cpu_fsr, uc->cpu_env);
 
     gen_store_fpr_D(dc, rd, dst);
 }
@@ -2139,12 +2186,13 @@ static inline void gen_fop_DQ(DisasContext *dc, int rd, int rs,
 static inline void gen_ne_fop_QF(DisasContext *dc, int rd, int rs,
                                  void (*gen)(TCGContext *tcg_ctx, TCGv_ptr, TCGv_i32))
 {
-    TCGContext *tcg_ctx = dc->uc->tcg_ctx;
+    struct uc_struct *uc = dc->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv_i32 src;
 
     src = gen_load_fpr_F(dc, rs);
 
-    gen(tcg_ctx, tcg_ctx->cpu_env, src);
+    gen(tcg_ctx, uc->cpu_env, src);
 
     gen_op_store_QT0_fpr(dc, QFPREG(rd));
     gen_update_fprs_dirty(dc, QFPREG(rd));
@@ -2153,12 +2201,13 @@ static inline void gen_ne_fop_QF(DisasContext *dc, int rd, int rs,
 static inline void gen_ne_fop_QD(DisasContext *dc, int rd, int rs,
                                  void (*gen)(TCGContext *tcg_ctx, TCGv_ptr, TCGv_i64))
 {
-    TCGContext *tcg_ctx = dc->uc->tcg_ctx;
+    struct uc_struct *uc = dc->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv_i64 src;
 
     src = gen_load_fpr_D(dc, rs);
 
-    gen(tcg_ctx, tcg_ctx->cpu_env, src);
+    gen(tcg_ctx, uc->cpu_env, src);
 
     gen_op_store_QT0_fpr(dc, QFPREG(rd));
     gen_update_fprs_dirty(dc, QFPREG(rd));
@@ -2423,7 +2472,8 @@ static DisasASI get_asi(DisasContext *dc, int insn, TCGMemOp memop)
 static void gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr,
                        int insn, TCGMemOp memop)
 {
-    TCGContext *tcg_ctx = dc->uc->tcg_ctx;
+    struct uc_struct *uc = dc->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     DisasASI da = get_asi(dc, insn, memop);
 
     switch (da.type) {
@@ -2434,7 +2484,7 @@ static void gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr,
         break;
     case GET_ASI_DIRECT:
         gen_address_mask(dc, addr);
-        tcg_gen_qemu_ld_tl(dc->uc, dst, addr, da.mem_idx, da.memop);
+        tcg_gen_qemu_ld_tl(uc, dst, addr, da.mem_idx, da.memop);
         break;
     default:
         {
@@ -2443,11 +2493,11 @@ static void gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr,
 
             save_state(dc);
 #ifdef TARGET_SPARC64
-            gen_helper_ld_asi(tcg_ctx, dst, tcg_ctx->cpu_env, addr, r_asi, r_mop);
+            gen_helper_ld_asi(tcg_ctx, dst, uc->cpu_env, addr, r_asi, r_mop);
 #else
             {
                 TCGv_i64 t64 = tcg_temp_new_i64(tcg_ctx);
-                gen_helper_ld_asi(tcg_ctx, t64, tcg_ctx->cpu_env, addr, r_asi, r_mop);
+                gen_helper_ld_asi(tcg_ctx, t64, uc->cpu_env, addr, r_asi, r_mop);
                 tcg_gen_trunc_i64_tl(tcg_ctx, dst, t64);
                 tcg_temp_free_i64(tcg_ctx, t64);
             }
@@ -2462,7 +2512,8 @@ static void gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr,
 static void gen_st_asi(DisasContext *dc, TCGv src, TCGv addr,
                        int insn, TCGMemOp memop)
 {
-    TCGContext *tcg_ctx = dc->uc->tcg_ctx;
+    struct uc_struct *uc = dc->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     DisasASI da = get_asi(dc, insn, memop);
 
     switch (da.type) {
@@ -2484,7 +2535,7 @@ static void gen_st_asi(DisasContext *dc, TCGv src, TCGv addr,
 #endif
     case GET_ASI_DIRECT:
         gen_address_mask(dc, addr);
-        tcg_gen_qemu_st_tl(dc->uc, src, addr, da.mem_idx, da.memop);
+        tcg_gen_qemu_st_tl(uc, src, addr, da.mem_idx, da.memop);
         break;
 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
     case GET_ASI_BCOPY:
@@ -2505,8 +2556,8 @@ static void gen_st_asi(DisasContext *dc, TCGv src, TCGv addr,
             for (i = 0; i < 32; i += 4) {
                 /* Since the loads and stores are paired, allow the
                    copy to happen in the host endianness.  */
-                tcg_gen_qemu_ld_i32(dc->uc, tmp, saddr, da.mem_idx, MO_UL);
-                tcg_gen_qemu_st_i32(dc->uc, tmp, daddr, da.mem_idx, MO_UL);
+                tcg_gen_qemu_ld_i32(uc, tmp, saddr, da.mem_idx, MO_UL);
+                tcg_gen_qemu_st_i32(uc, tmp, daddr, da.mem_idx, MO_UL);
                 tcg_gen_add_tl(tcg_ctx, saddr, saddr, four);
                 tcg_gen_add_tl(tcg_ctx, daddr, daddr, four);
             }
@@ -2525,12 +2576,12 @@ static void gen_st_asi(DisasContext *dc, TCGv src, TCGv addr,
 
             save_state(dc);
 #ifdef TARGET_SPARC64
-            gen_helper_st_asi(tcg_ctx, tcg_ctx->cpu_env, addr, src, r_asi, r_mop);
+            gen_helper_st_asi(tcg_ctx, uc->cpu_env, addr, src, r_asi, r_mop);
 #else
             {
                 TCGv_i64 t64 = tcg_temp_new_i64(tcg_ctx);
                 tcg_gen_extu_tl_i64(tcg_ctx, t64, src);
-                gen_helper_st_asi(tcg_ctx, tcg_ctx->cpu_env, addr, t64, r_asi, r_mop);
+                gen_helper_st_asi(tcg_ctx, uc->cpu_env, addr, t64, r_asi, r_mop);
                 tcg_temp_free_i64(tcg_ctx, t64);
             }
 #endif
@@ -2588,7 +2639,8 @@ static void gen_cas_asi(DisasContext *dc, TCGv addr, TCGv cmpv,
 
 static void gen_ldstub_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn)
 {
-    TCGContext *tcg_ctx = dc->uc->tcg_ctx;
+    struct uc_struct *uc = dc->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     DisasASI da = get_asi(dc, insn, MO_UB);
 
     switch (da.type) {
@@ -2601,7 +2653,7 @@ static void gen_ldstub_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn)
         /* ??? In theory, this should be raise DAE_invalid_asi.
            But the SS-20 roms do ldstuba [%l0] #ASI_M_CTL, %o1.  */
         if (tb_cflags(dc->tb) & CF_PARALLEL) {
-            gen_helper_exit_atomic(tcg_ctx, tcg_ctx->cpu_env);
+            gen_helper_exit_atomic(tcg_ctx, uc->cpu_env);
         } else {
             TCGv_i32 r_asi = tcg_const_i32(tcg_ctx, da.asi);
             TCGv_i32 r_mop = tcg_const_i32(tcg_ctx, MO_UB);
@@ -2609,10 +2661,10 @@ static void gen_ldstub_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn)
 
             save_state(dc);
             t64 = tcg_temp_new_i64(tcg_ctx);
-            gen_helper_ld_asi(tcg_ctx, t64, tcg_ctx->cpu_env, addr, r_asi, r_mop);
+            gen_helper_ld_asi(tcg_ctx, t64, uc->cpu_env, addr, r_asi, r_mop);
 
             s64 = tcg_const_i64(tcg_ctx, 0xff);
-            gen_helper_st_asi(tcg_ctx, tcg_ctx->cpu_env, addr, s64, r_asi, r_mop);
+            gen_helper_st_asi(tcg_ctx, uc->cpu_env, addr, s64, r_asi, r_mop);
             tcg_temp_free_i64(tcg_ctx, s64);
             tcg_temp_free_i32(tcg_ctx, r_mop);
             tcg_temp_free_i32(tcg_ctx, r_asi);
@@ -2632,7 +2684,8 @@ static void gen_ldstub_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn)
 static void gen_ldf_asi(DisasContext *dc, TCGv addr,
                         int insn, int size, int rd)
 {
-    TCGContext *tcg_ctx = dc->uc->tcg_ctx;
+    struct uc_struct *uc = dc->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     DisasASI da = get_asi(dc, insn, (size == 4 ? MO_TEUL : MO_TEQ));
     TCGv_i32 d32;
     TCGv_i64 d64;
@@ -2646,18 +2699,18 @@ static void gen_ldf_asi(DisasContext *dc, TCGv addr,
         switch (size) {
         case 4:
             d32 = gen_dest_fpr_F(dc);
-            tcg_gen_qemu_ld_i32(dc->uc, d32, addr, da.mem_idx, da.memop);
+            tcg_gen_qemu_ld_i32(uc, d32, addr, da.mem_idx, da.memop);
             gen_store_fpr_F(dc, rd, d32);
             break;
         case 8:
-            tcg_gen_qemu_ld_i64(dc->uc, tcg_ctx->cpu_fpr[rd / 2], addr, da.mem_idx,
+            tcg_gen_qemu_ld_i64(uc, tcg_ctx->cpu_fpr[rd / 2], addr, da.mem_idx,
                                 da.memop | MO_ALIGN_4);
             break;
         case 16:
             d64 = tcg_temp_new_i64(tcg_ctx);
-            tcg_gen_qemu_ld_i64(dc->uc, d64, addr, da.mem_idx, da.memop | MO_ALIGN_4);
+            tcg_gen_qemu_ld_i64(uc, d64, addr, da.mem_idx, da.memop | MO_ALIGN_4);
             tcg_gen_addi_tl(tcg_ctx, addr, addr, 8);
-            tcg_gen_qemu_ld_i64(dc->uc, tcg_ctx->cpu_fpr[rd/2+1], addr, da.mem_idx,
+            tcg_gen_qemu_ld_i64(uc, tcg_ctx->cpu_fpr[rd/2+1], addr, da.mem_idx,
                                 da.memop | MO_ALIGN_4);
             tcg_gen_mov_i64(tcg_ctx, tcg_ctx->cpu_fpr[rd / 2], d64);
             tcg_temp_free_i64(tcg_ctx, d64);
@@ -2680,7 +2733,7 @@ static void gen_ldf_asi(DisasContext *dc, TCGv addr,
             memop = da.memop | MO_ALIGN_64;
             eight = tcg_const_tl(tcg_ctx, 8);
             for (i = 0; ; ++i) {
-                tcg_gen_qemu_ld_i64(dc->uc, tcg_ctx->cpu_fpr[rd / 2 + i], addr,
+                tcg_gen_qemu_ld_i64(uc, tcg_ctx->cpu_fpr[rd / 2 + i], addr,
                                     da.mem_idx, memop);
                 if (i == 7) {
                     break;
@@ -2698,7 +2751,7 @@ static void gen_ldf_asi(DisasContext *dc, TCGv addr,
         /* Valid for lddfa only.  */
         if (size == 8) {
             gen_address_mask(dc, addr);
-            tcg_gen_qemu_ld_i64(dc->uc, tcg_ctx->cpu_fpr[rd / 2], addr, da.mem_idx, da.memop);
+            tcg_gen_qemu_ld_i64(uc, tcg_ctx->cpu_fpr[rd / 2], addr, da.mem_idx, da.memop);
         } else {
             gen_exception(dc, TT_ILL_INSN);
         }
@@ -2717,7 +2770,7 @@ static void gen_ldf_asi(DisasContext *dc, TCGv addr,
             switch (size) {
             case 4:
                 d64 = tcg_temp_new_i64(tcg_ctx);
-                gen_helper_ld_asi(tcg_ctx, d64, tcg_ctx->cpu_env, addr, r_asi, r_mop);
+                gen_helper_ld_asi(tcg_ctx, d64, uc->cpu_env, addr, r_asi, r_mop);
                 d32 = gen_dest_fpr_F(dc);
                 tcg_gen_extrl_i64_i32(tcg_ctx, d32, d64);
                 tcg_temp_free_i64(tcg_ctx, d64);
@@ -2725,11 +2778,11 @@ static void gen_ldf_asi(DisasContext *dc, TCGv addr,
                 break;
             case 8:
                 gen_helper_ld_asi(tcg_ctx, tcg_ctx->cpu_fpr[rd / 2],
-                                  tcg_ctx->cpu_env, addr, r_asi, r_mop);
+                                  uc->cpu_env, addr, r_asi, r_mop);
                 break;
             case 16:
                 d64 = tcg_temp_new_i64(tcg_ctx);
-                gen_helper_ld_asi(tcg_ctx, d64, tcg_ctx->cpu_env, addr, r_asi, r_mop);
+                gen_helper_ld_asi(tcg_ctx, d64, uc->cpu_env, addr, r_asi, r_mop);
                 tcg_gen_addi_tl(tcg_ctx, addr, addr, 8);
                 tcg_gen_mov_i64(tcg_ctx, tcg_ctx->cpu_fpr[rd / 2], d64);
                 tcg_temp_free_i64(tcg_ctx, d64);
@@ -2830,7 +2883,8 @@ static void gen_stf_asi(DisasContext *dc, TCGv addr,
 
 static void gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd)
 {
-    TCGContext *tcg_ctx = dc->uc->tcg_ctx;
+    struct uc_struct *uc = dc->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     DisasASI da = get_asi(dc, insn, MO_TEQ);
     TCGv_i64 hi = gen_dest_gpr(dc, rd);
     TCGv_i64 lo = gen_dest_gpr(dc, rd + 1);
@@ -2841,9 +2895,9 @@ static void gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd)
 
     case GET_ASI_DTWINX:
         gen_address_mask(dc, addr);
-        tcg_gen_qemu_ld_i64(dc->uc, hi, addr, da.mem_idx, da.memop | MO_ALIGN_16);
+        tcg_gen_qemu_ld_i64(uc, hi, addr, da.mem_idx, da.memop | MO_ALIGN_16);
         tcg_gen_addi_tl(tcg_ctx, addr, addr, 8);
-        tcg_gen_qemu_ld_i64(dc->uc, lo, addr, da.mem_idx, da.memop);
+        tcg_gen_qemu_ld_i64(uc, lo, addr, da.mem_idx, da.memop);
         break;
 
     case GET_ASI_DIRECT:
@@ -2851,7 +2905,7 @@ static void gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd)
             TCGv_i64 tmp = tcg_temp_new_i64(tcg_ctx);
 
             gen_address_mask(dc, addr);
-            tcg_gen_qemu_ld_i64(dc->uc, tmp, addr, da.mem_idx, da.memop);
+            tcg_gen_qemu_ld_i64(uc, tmp, addr, da.mem_idx, da.memop);
 
             /* Note that LE ldda acts as if each 32-bit register
                result is byte swapped.  Having just performed one
@@ -2876,7 +2930,7 @@ static void gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd)
             TCGv_i64 tmp = tcg_temp_new_i64(tcg_ctx);
 
             save_state(dc);
-            gen_helper_ld_asi(tcg_ctx, tmp, tcg_ctx->cpu_env, addr, r_asi, r_mop);
+            gen_helper_ld_asi(tcg_ctx, tmp, uc->cpu_env, addr, r_asi, r_mop);
             tcg_temp_free_i32(tcg_ctx, r_asi);
             tcg_temp_free_i32(tcg_ctx, r_mop);
 
@@ -2898,7 +2952,8 @@ static void gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd)
 static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr,
                          int insn, int rd)
 {
-    TCGContext *tcg_ctx = dc->uc->tcg_ctx;
+    struct uc_struct *uc = dc->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     DisasASI da = get_asi(dc, insn, MO_TEQ);
     TCGv lo = gen_load_gpr(dc, rd + 1);
 
@@ -2908,9 +2963,9 @@ static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr,
 
     case GET_ASI_DTWINX:
         gen_address_mask(dc, addr);
-        tcg_gen_qemu_st_i64(dc->uc, hi, addr, da.mem_idx, da.memop | MO_ALIGN_16);
+        tcg_gen_qemu_st_i64(uc, hi, addr, da.mem_idx, da.memop | MO_ALIGN_16);
         tcg_gen_addi_tl(tcg_ctx, addr, addr, 8);
-        tcg_gen_qemu_st_i64(dc->uc, lo, addr, da.mem_idx, da.memop);
+        tcg_gen_qemu_st_i64(uc, lo, addr, da.mem_idx, da.memop);
         break;
 
     case GET_ASI_DIRECT:
@@ -2926,7 +2981,7 @@ static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr,
                 tcg_gen_concat32_i64(tcg_ctx, t64, hi, lo);
             }
             gen_address_mask(dc, addr);
-            tcg_gen_qemu_st_i64(dc->uc, t64, addr, da.mem_idx, da.memop);
+            tcg_gen_qemu_st_i64(uc, t64, addr, da.mem_idx, da.memop);
             tcg_temp_free_i64(tcg_ctx, t64);
         }
         break;
@@ -2947,7 +3002,7 @@ static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr,
             }
 
             save_state(dc);
-            gen_helper_st_asi(tcg_ctx, tcg_ctx->cpu_env, addr, t64, r_asi, r_mop);
+            gen_helper_st_asi(tcg_ctx, uc->cpu_env, addr, t64, r_asi, r_mop);
             tcg_temp_free_i32(tcg_ctx, r_mop);
             tcg_temp_free_i32(tcg_ctx, r_asi);
             tcg_temp_free_i64(tcg_ctx, t64);
@@ -2988,7 +3043,8 @@ static void gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd)
        whereby "rd + 1" elicits "error: array subscript is above array".
        Since we have already asserted that rd is even, the semantics
        are unchanged.  */
-    TCGContext *tcg_ctx = dc->uc->tcg_ctx;
+    struct uc_struct *uc = dc->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     TCGv lo = gen_dest_gpr(dc, rd | 1);
     TCGv hi = gen_dest_gpr(dc, rd);
     TCGv_i64 t64 = tcg_temp_new_i64(tcg_ctx);
@@ -3000,7 +3056,7 @@ static void gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd)
         return;
     case GET_ASI_DIRECT:
         gen_address_mask(dc, addr);
-        tcg_gen_qemu_ld_i64(dc->uc, t64, addr, da.mem_idx, da.memop);
+        tcg_gen_qemu_ld_i64(uc, t64, addr, da.mem_idx, da.memop);
         break;
     default:
         {
@@ -3008,7 +3064,7 @@ static void gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd)
             TCGv_i32 r_mop = tcg_const_i32(tcg_ctx, MO_Q);
 
             save_state(dc);
-            gen_helper_ld_asi(tcg_ctx, t64, tcg_ctx->cpu_env, addr, r_asi, r_mop);
+            gen_helper_ld_asi(tcg_ctx, t64, uc->cpu_env, addr, r_asi, r_mop);
             tcg_temp_free_i32(tcg_ctx, r_mop);
             tcg_temp_free_i32(tcg_ctx, r_asi);
         }
@@ -3024,7 +3080,8 @@ static void gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd)
 static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr,
                          int insn, int rd)
 {
-    TCGContext *tcg_ctx = dc->uc->tcg_ctx;
+    struct uc_struct *uc = dc->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     DisasASI da = get_asi(dc, insn, MO_TEQ);
     TCGv lo = gen_load_gpr(dc, rd + 1);
     TCGv_i64 t64 = tcg_temp_new_i64(tcg_ctx);
@@ -3036,7 +3093,7 @@ static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr,
         break;
     case GET_ASI_DIRECT:
         gen_address_mask(dc, addr);
-        tcg_gen_qemu_st_i64(dc->uc, t64, addr, da.mem_idx, da.memop);
+        tcg_gen_qemu_st_i64(uc, t64, addr, da.mem_idx, da.memop);
         break;
     case GET_ASI_BFILL:
         /* Store 32 bytes of T64 to ADDR.  */
@@ -3051,7 +3108,7 @@ static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr,
 
             tcg_gen_andi_tl(tcg_ctx, d_addr, addr, -8);
             for (i = 0; i < 32; i += 8) {
-                tcg_gen_qemu_st_i64(dc->uc, t64, d_addr, da.mem_idx, da.memop);
+                tcg_gen_qemu_st_i64(uc, t64, d_addr, da.mem_idx, da.memop);
                 tcg_gen_add_tl(tcg_ctx, d_addr, d_addr, eight);
             }
 
@@ -3065,7 +3122,7 @@ static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr,
             TCGv_i32 r_mop = tcg_const_i32(tcg_ctx, MO_Q);
 
             save_state(dc);
-            gen_helper_st_asi(tcg_ctx, tcg_ctx->cpu_env, addr, t64, r_asi, r_mop);
+            gen_helper_st_asi(tcg_ctx, uc->cpu_env, addr, t64, r_asi, r_mop);
             tcg_temp_free_i32(tcg_ctx, r_mop);
             tcg_temp_free_i32(tcg_ctx, r_asi);
         }
@@ -3332,7 +3389,8 @@ static void gen_faligndata(TCGContext *tcg_ctx, TCGv dst, TCGv gsr, TCGv s1, TCG
 /* before an instruction, dc->pc must be static */
 static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_insn)
 {
-    TCGContext *tcg_ctx = dc->uc->tcg_ctx;
+    struct uc_struct *uc = dc->uc;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     unsigned int opc, rs1, rs2, rd;
     TCGv cpu_src1, cpu_src2;
     TCGv_i32 cpu_src1_32, cpu_src2_32, cpu_dst_32;
@@ -3340,8 +3398,8 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
     target_long simm;
 
     // Unicorn: trace this instruction on request
-    if (hook_insn && HOOK_EXISTS_BOUNDED(dc->uc, UC_HOOK_CODE, dc->pc)) {
-        gen_uc_tracecode(tcg_ctx, 4, UC_HOOK_CODE_IDX, dc->uc, dc->pc);
+    if (hook_insn && HOOK_EXISTS_BOUNDED(uc, UC_HOOK_CODE, dc->pc)) {
+        gen_uc_tracecode(tcg_ctx, 4, UC_HOOK_CODE_IDX, uc, dc->pc);
         // the callback might want to stop emulation immediately
         check_exit_request(tcg_ctx);
     }
@@ -3526,7 +3584,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
                     tcg_gen_addi_i32(tcg_ctx, trap, trap, TT_TRAP);
                 }
 
-                gen_helper_raise_exception(tcg_ctx, tcg_ctx->cpu_env, trap);
+                gen_helper_raise_exception(tcg_ctx, uc->cpu_env, trap);
                 tcg_temp_free_i32(tcg_ctx, trap);
 
                 if (cond == 8) {
@@ -3565,7 +3623,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
 #ifdef TARGET_SPARC64
                 case 0x2: /* V9 rdccr */
                     update_psr(dc);
-                    gen_helper_rdccr(tcg_ctx, cpu_dst, tcg_ctx->cpu_env);
+                    gen_helper_rdccr(tcg_ctx, cpu_dst, uc->cpu_env);
                     gen_store_gpr(dc, rd, cpu_dst);
                     break;
                 case 0x3: /* V9 rdasi */
@@ -3579,9 +3637,9 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
 
                         r_tickptr = tcg_temp_new_ptr(tcg_ctx);
                         r_const = tcg_const_i32(tcg_ctx, dc->mem_idx);
-                        tcg_gen_ld_ptr(tcg_ctx, r_tickptr, tcg_ctx->cpu_env,
+                        tcg_gen_ld_ptr(tcg_ctx, r_tickptr, uc->cpu_env,
                                        offsetof(CPUSPARCState, tick));
-                        gen_helper_tick_get_count(tcg_ctx, cpu_dst, tcg_ctx->cpu_env, r_tickptr,
+                        gen_helper_tick_get_count(tcg_ctx, cpu_dst, uc->cpu_env, r_tickptr,
                                                   r_const);
                         tcg_temp_free_ptr(tcg_ctx, r_tickptr);
                         tcg_temp_free_i32(tcg_ctx, r_const);
@@ -3612,7 +3670,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
                     gen_store_gpr(dc, rd, tcg_ctx->cpu_gsr);
                     break;
                 case 0x16: /* Softint */
-                    tcg_gen_ld32s_tl(tcg_ctx, cpu_dst, tcg_ctx->cpu_env,
+                    tcg_gen_ld32s_tl(tcg_ctx, cpu_dst, uc->cpu_env,
                                      offsetof(CPUSPARCState, softint));
                     gen_store_gpr(dc, rd, cpu_dst);
                     break;
@@ -3626,9 +3684,9 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
 
                         r_tickptr = tcg_temp_new_ptr(tcg_ctx);
                         r_const = tcg_const_i32(tcg_ctx, dc->mem_idx);
-                        tcg_gen_ld_ptr(tcg_ctx, r_tickptr, tcg_ctx->cpu_env,
+                        tcg_gen_ld_ptr(tcg_ctx, r_tickptr, uc->cpu_env,
                                        offsetof(CPUSPARCState, stick));
-                        gen_helper_tick_get_count(tcg_ctx, cpu_dst, tcg_ctx->cpu_env, r_tickptr,
+                        gen_helper_tick_get_count(tcg_ctx, cpu_dst, uc->cpu_env, r_tickptr,
                                                   r_const);
                         tcg_temp_free_ptr(tcg_ctx, r_tickptr);
                         tcg_temp_free_i32(tcg_ctx, r_const);
@@ -3665,7 +3723,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
                     goto priv_insn;
                 }
                 update_psr(dc);
-                gen_helper_rdpsr(tcg_ctx, cpu_dst, tcg_ctx->cpu_env);
+                gen_helper_rdpsr(tcg_ctx, cpu_dst, uc->cpu_env);
 #else
                 CHECK_IU_FEATURE(dc, HYPV);
                 if (!hypervisor(dc))
@@ -3673,7 +3731,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
                 rs1 = GET_FIELD(insn, 13, 17);
                 switch (rs1) {
                 case 0: // hpstate
-                    tcg_gen_ld_i64(tcg_ctx, cpu_dst, tcg_ctx->cpu_env,
+                    tcg_gen_ld_i64(tcg_ctx, cpu_dst, uc->cpu_env,
                                    offsetof(CPUSPARCState, hpstate));
                     break;
                 case 1: // htstate
@@ -3710,7 +3768,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
                         TCGv_ptr r_tsptr;
 
                         r_tsptr = tcg_temp_new_ptr(tcg_ctx);
-                        gen_load_trap_state_at_tl(dc, r_tsptr, tcg_ctx->cpu_env);
+                        gen_load_trap_state_at_tl(dc, r_tsptr, uc->cpu_env);
                         tcg_gen_ld_tl(tcg_ctx, cpu_tmp0, r_tsptr,
                                       offsetof(trap_state, tpc));
                         tcg_temp_free_ptr(tcg_ctx, r_tsptr);
@@ -3721,7 +3779,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
                         TCGv_ptr r_tsptr;
 
                         r_tsptr = tcg_temp_new_ptr(tcg_ctx);
-                        gen_load_trap_state_at_tl(dc, r_tsptr, tcg_ctx->cpu_env);
+                        gen_load_trap_state_at_tl(dc, r_tsptr, uc->cpu_env);
                         tcg_gen_ld_tl(tcg_ctx, cpu_tmp0, r_tsptr,
                                       offsetof(trap_state, tnpc));
                         tcg_temp_free_ptr(tcg_ctx, r_tsptr);
@@ -3732,7 +3790,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
                         TCGv_ptr r_tsptr;
 
                         r_tsptr = tcg_temp_new_ptr(tcg_ctx);
-                        gen_load_trap_state_at_tl(dc, r_tsptr, tcg_ctx->cpu_env);
+                        gen_load_trap_state_at_tl(dc, r_tsptr, uc->cpu_env);
                         tcg_gen_ld_tl(tcg_ctx, cpu_tmp0, r_tsptr,
                                       offsetof(trap_state, tstate));
                         tcg_temp_free_ptr(tcg_ctx, r_tsptr);
@@ -3742,7 +3800,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
                     {
                         TCGv_ptr r_tsptr = tcg_temp_new_ptr(tcg_ctx);
 
-                        gen_load_trap_state_at_tl(dc, r_tsptr, tcg_ctx->cpu_env);
+                        gen_load_trap_state_at_tl(dc, r_tsptr, uc->cpu_env);
                         tcg_gen_ld32s_tl(tcg_ctx, cpu_tmp0, r_tsptr,
                                          offsetof(trap_state, tt));
                         tcg_temp_free_ptr(tcg_ctx, r_tsptr);
@@ -3755,9 +3813,9 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
 
                         r_tickptr = tcg_temp_new_ptr(tcg_ctx);
                         r_const = tcg_const_i32(tcg_ctx, dc->mem_idx);
-                        tcg_gen_ld_ptr(tcg_ctx, r_tickptr, tcg_ctx->cpu_env,
+                        tcg_gen_ld_ptr(tcg_ctx, r_tickptr, uc->cpu_env,
                                        offsetof(CPUSPARCState, tick));
-                        gen_helper_tick_get_count(tcg_ctx, cpu_tmp0, tcg_ctx->cpu_env,
+                        gen_helper_tick_get_count(tcg_ctx, cpu_tmp0, uc->cpu_env,
                                                   r_tickptr, r_const);
                         tcg_temp_free_ptr(tcg_ctx, r_tickptr);
                         tcg_temp_free_i32(tcg_ctx, r_const);
@@ -3767,43 +3825,43 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
                     tcg_gen_mov_tl(tcg_ctx, cpu_tmp0, tcg_ctx->cpu_tbr);
                     break;
                 case 6: // pstate
-                    tcg_gen_ld32s_tl(tcg_ctx, cpu_tmp0, tcg_ctx->cpu_env,
+                    tcg_gen_ld32s_tl(tcg_ctx, cpu_tmp0, uc->cpu_env,
                                      offsetof(CPUSPARCState, pstate));
                     break;
                 case 7: // tl
-                    tcg_gen_ld32s_tl(tcg_ctx, cpu_tmp0, tcg_ctx->cpu_env,
+                    tcg_gen_ld32s_tl(tcg_ctx, cpu_tmp0, uc->cpu_env,
                                      offsetof(CPUSPARCState, tl));
                     break;
                 case 8: // pil
-                    tcg_gen_ld32s_tl(tcg_ctx, cpu_tmp0, tcg_ctx->cpu_env,
+                    tcg_gen_ld32s_tl(tcg_ctx, cpu_tmp0, uc->cpu_env,
                                      offsetof(CPUSPARCState, psrpil));
                     break;
                 case 9: // cwp
-                    gen_helper_rdcwp(tcg_ctx, cpu_tmp0, tcg_ctx->cpu_env);
+                    gen_helper_rdcwp(tcg_ctx, cpu_tmp0, uc->cpu_env);
                     break;
                 case 10: // cansave
-                    tcg_gen_ld32s_tl(tcg_ctx, cpu_tmp0, tcg_ctx->cpu_env,
+                    tcg_gen_ld32s_tl(tcg_ctx, cpu_tmp0, uc->cpu_env,
                                      offsetof(CPUSPARCState, cansave));
                     break;
                 case 11: // canrestore
-                    tcg_gen_ld32s_tl(tcg_ctx, cpu_tmp0, tcg_ctx->cpu_env,
+                    tcg_gen_ld32s_tl(tcg_ctx, cpu_tmp0, uc->cpu_env,
                                      offsetof(CPUSPARCState, canrestore));
                     break;
                 case 12: // cleanwin
-                    tcg_gen_ld32s_tl(tcg_ctx, cpu_tmp0, tcg_ctx->cpu_env,
+                    tcg_gen_ld32s_tl(tcg_ctx, cpu_tmp0, uc->cpu_env,
                                      offsetof(CPUSPARCState, cleanwin));
                     break;
                 case 13: // otherwin
-                    tcg_gen_ld32s_tl(tcg_ctx, cpu_tmp0, tcg_ctx->cpu_env,
+                    tcg_gen_ld32s_tl(tcg_ctx, cpu_tmp0, uc->cpu_env,
                                      offsetof(CPUSPARCState, otherwin));
                     break;
                 case 14: // wstate
-                    tcg_gen_ld32s_tl(tcg_ctx, cpu_tmp0, tcg_ctx->cpu_env,
+                    tcg_gen_ld32s_tl(tcg_ctx, cpu_tmp0, uc->cpu_env,
                                      offsetof(CPUSPARCState, wstate));
                     break;
                 case 16: // UA2005 gl
                     CHECK_IU_FEATURE(dc, GL);
-                    tcg_gen_ld32s_tl(tcg_ctx, cpu_tmp0, tcg_ctx->cpu_env,
+                    tcg_gen_ld32s_tl(tcg_ctx, cpu_tmp0, uc->cpu_env,
                                      offsetof(CPUSPARCState, gl));
                     break;
                 case 26: // UA2005 strand status
@@ -3826,7 +3884,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
                 break;
             } else if (xop == 0x2b) { /* rdtbr / V9 flushw */
 #ifdef TARGET_SPARC64
-                gen_helper_flushw(tcg_ctx, tcg_ctx->cpu_env);
+                gen_helper_flushw(tcg_ctx, uc->cpu_env);
 #else
                 if (!supervisor(dc))
                     goto priv_insn;
@@ -4373,28 +4431,28 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
                         break;
 #ifdef TARGET_SPARC64
                     case 0xd: /* V9 udivx */
-                        gen_helper_udivx(tcg_ctx, cpu_dst, tcg_ctx->cpu_env, cpu_src1, cpu_src2);
+                        gen_helper_udivx(tcg_ctx, cpu_dst, uc->cpu_env, cpu_src1, cpu_src2);
                         break;
 #endif
                     case 0xe: /* udiv */
                         CHECK_IU_FEATURE(dc, DIV);
                         if (xop & 0x10) {
-                            gen_helper_udiv_cc(tcg_ctx, cpu_dst, tcg_ctx->cpu_env, cpu_src1,
+                            gen_helper_udiv_cc(tcg_ctx, cpu_dst, uc->cpu_env, cpu_src1,
                                                cpu_src2);
                             dc->cc_op = CC_OP_DIV;
                         } else {
-                            gen_helper_udiv(tcg_ctx, cpu_dst, tcg_ctx->cpu_env, cpu_src1,
+                            gen_helper_udiv(tcg_ctx, cpu_dst, uc->cpu_env, cpu_src1,
                                             cpu_src2);
                         }
                         break;
                     case 0xf: /* sdiv */
                         CHECK_IU_FEATURE(dc, DIV);
                         if (xop & 0x10) {
-                            gen_helper_sdiv_cc(tcg_ctx, cpu_dst, tcg_ctx->cpu_env, cpu_src1,
+                            gen_helper_sdiv_cc(tcg_ctx, cpu_dst, uc->cpu_env, cpu_src1,
                                                cpu_src2);
                             dc->cc_op = CC_OP_DIV;
                         } else {
-                            gen_helper_sdiv(tcg_ctx, cpu_dst, tcg_ctx->cpu_env, cpu_src1,
+                            gen_helper_sdiv(tcg_ctx, cpu_dst, uc->cpu_env, cpu_src1,
                                             cpu_src2);
                         }
                         break;
@@ -4419,13 +4477,13 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
                         dc->cc_op = CC_OP_TSUB;
                         break;
                     case 0x22: /* taddcctv */
-                        gen_helper_taddcctv(tcg_ctx, cpu_dst, tcg_ctx->cpu_env,
+                        gen_helper_taddcctv(tcg_ctx, cpu_dst, uc->cpu_env,
                                             cpu_src1, cpu_src2);
                         gen_store_gpr(dc, rd, cpu_dst);
                         dc->cc_op = CC_OP_TADDTV;
                         break;
                     case 0x23: /* tsubcctv */
-                        gen_helper_tsubcctv(tcg_ctx, cpu_dst, tcg_ctx->cpu_env,
+                        gen_helper_tsubcctv(tcg_ctx, cpu_dst, uc->cpu_env,
                                             cpu_src1, cpu_src2);
                         gen_store_gpr(dc, rd, cpu_dst);
                         dc->cc_op = CC_OP_TSUBTV;
@@ -4492,20 +4550,20 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
                                                      CPU_FEATURE_POWERDOWN)) {
                                     /* LEON3 power-down */
                                     save_state(dc);
-                                    gen_helper_power_down(tcg_ctx, tcg_ctx->cpu_env);
+                                    gen_helper_power_down(tcg_ctx, uc->cpu_env);
                                 }
                                 break;
 #else
                             case 0x2: /* V9 wrccr */
                                 tcg_gen_xor_tl(tcg_ctx, cpu_tmp0, cpu_src1, cpu_src2);
-                                gen_helper_wrccr(tcg_ctx, tcg_ctx->cpu_env, cpu_tmp0);
+                                gen_helper_wrccr(tcg_ctx, uc->cpu_env, cpu_tmp0);
                                 tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_cc_op, CC_OP_FLAGS);
                                 dc->cc_op = CC_OP_FLAGS;
                                 break;
                             case 0x3: /* V9 wrasi */
                                 tcg_gen_xor_tl(tcg_ctx, cpu_tmp0, cpu_src1, cpu_src2);
                                 tcg_gen_andi_tl(tcg_ctx, cpu_tmp0, cpu_tmp0, 0xff);
-                                tcg_gen_st32_tl(tcg_ctx, cpu_tmp0, tcg_ctx->cpu_env,
+                                tcg_gen_st32_tl(tcg_ctx, cpu_tmp0, uc->cpu_env,
                                                 offsetof(CPUSPARCState, asi));
                                 /* End TB to notice changed ASI.  */
                                 save_state(dc);
@@ -4539,19 +4597,19 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
                                 if (!supervisor(dc))
                                     goto illegal_insn;
                                 tcg_gen_xor_tl(tcg_ctx, cpu_tmp0, cpu_src1, cpu_src2);
-                                gen_helper_set_softint(tcg_ctx, tcg_ctx->cpu_env, cpu_tmp0);
+                                gen_helper_set_softint(tcg_ctx, uc->cpu_env, cpu_tmp0);
                                 break;
                             case 0x15: /* Softint clear */
                                 if (!supervisor(dc))
                                     goto illegal_insn;
                                 tcg_gen_xor_tl(tcg_ctx, cpu_tmp0, cpu_src1, cpu_src2);
-                                gen_helper_clear_softint(tcg_ctx, tcg_ctx->cpu_env, cpu_tmp0);
+                                gen_helper_clear_softint(tcg_ctx, uc->cpu_env, cpu_tmp0);
                                 break;
                             case 0x16: /* Softint write */
                                 if (!supervisor(dc))
                                     goto illegal_insn;
                                 tcg_gen_xor_tl(tcg_ctx, cpu_tmp0, cpu_src1, cpu_src2);
-                                gen_helper_write_softint(tcg_ctx, tcg_ctx->cpu_env, cpu_tmp0);
+                                gen_helper_write_softint(tcg_ctx, uc->cpu_env, cpu_tmp0);
                                 break;
                             case 0x17: /* Tick compare */
 #if !defined(CONFIG_USER_ONLY)
@@ -4564,7 +4622,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
                                     tcg_gen_xor_tl(tcg_ctx, tcg_ctx->cpu_tick_cmpr, cpu_src1,
                                                    cpu_src2);
                                     r_tickptr = tcg_temp_new_ptr(tcg_ctx);
-                                    tcg_gen_ld_ptr(tcg_ctx, r_tickptr, tcg_ctx->cpu_env,
+                                    tcg_gen_ld_ptr(tcg_ctx, r_tickptr, uc->cpu_env,
                                                    offsetof(CPUSPARCState, tick));
                                     gen_helper_tick_set_limit(tcg_ctx, r_tickptr,
                                                               tcg_ctx->cpu_tick_cmpr);
@@ -4582,7 +4640,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
                                     tcg_gen_xor_tl(tcg_ctx, cpu_tmp0, cpu_src1,
                                                    cpu_src2);
                                     r_tickptr = tcg_temp_new_ptr(tcg_ctx);
-                                    tcg_gen_ld_ptr(tcg_ctx, r_tickptr, tcg_ctx->cpu_env,
+                                    tcg_gen_ld_ptr(tcg_ctx, r_tickptr, uc->cpu_env,
                                                    offsetof(CPUSPARCState, stick));
                                     gen_helper_tick_set_count(tcg_ctx, r_tickptr,
                                                               cpu_tmp0);
@@ -4600,7 +4658,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
                                     tcg_gen_xor_tl(tcg_ctx, tcg_ctx->cpu_stick_cmpr, cpu_src1,
                                                    cpu_src2);
                                     r_tickptr = tcg_temp_new_ptr(tcg_ctx);
-                                    tcg_gen_ld_ptr(tcg_ctx, r_tickptr, tcg_ctx->cpu_env,
+                                    tcg_gen_ld_ptr(tcg_ctx, r_tickptr, uc->cpu_env,
                                                    offsetof(CPUSPARCState, stick));
                                     gen_helper_tick_set_limit(tcg_ctx, r_tickptr,
                                                               tcg_ctx->cpu_stick_cmpr);
@@ -4626,10 +4684,10 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
 #ifdef TARGET_SPARC64
                             switch (rd) {
                             case 0:
-                                gen_helper_saved(tcg_ctx, tcg_ctx->cpu_env);
+                                gen_helper_saved(tcg_ctx, uc->cpu_env);
                                 break;
                             case 1:
-                                gen_helper_restored(tcg_ctx, tcg_ctx->cpu_env);
+                                gen_helper_restored(tcg_ctx, uc->cpu_env);
                                 break;
                             case 2: /* UA2005 allclean */
                             case 3: /* UA2005 otherw */
@@ -4642,7 +4700,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
 #else
                             cpu_tmp0 = get_temp_tl(dc);
                             tcg_gen_xor_tl(tcg_ctx, cpu_tmp0, cpu_src1, cpu_src2);
-                            gen_helper_wrpsr(tcg_ctx, tcg_ctx->cpu_env, cpu_tmp0);
+                            gen_helper_wrpsr(tcg_ctx, uc->cpu_env, cpu_tmp0);
                             tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_cc_op, CC_OP_FLAGS);
                             dc->cc_op = CC_OP_FLAGS;
                             save_state(dc);
@@ -4665,7 +4723,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
                                     TCGv_ptr r_tsptr;
 
                                     r_tsptr = tcg_temp_new_ptr(tcg_ctx);
-                                    gen_load_trap_state_at_tl(dc, r_tsptr, tcg_ctx->cpu_env);
+                                    gen_load_trap_state_at_tl(dc, r_tsptr, uc->cpu_env);
                                     tcg_gen_st_tl(tcg_ctx, cpu_tmp0, r_tsptr,
                                                   offsetof(trap_state, tpc));
                                     tcg_temp_free_ptr(tcg_ctx, r_tsptr);
@@ -4676,7 +4734,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
                                     TCGv_ptr r_tsptr;
 
                                     r_tsptr = tcg_temp_new_ptr(tcg_ctx);
-                                    gen_load_trap_state_at_tl(dc, r_tsptr, tcg_ctx->cpu_env);
+                                    gen_load_trap_state_at_tl(dc, r_tsptr, uc->cpu_env);
                                     tcg_gen_st_tl(tcg_ctx, cpu_tmp0, r_tsptr,
                                                   offsetof(trap_state, tnpc));
                                     tcg_temp_free_ptr(tcg_ctx, r_tsptr);
@@ -4687,7 +4745,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
                                     TCGv_ptr r_tsptr;
 
                                     r_tsptr = tcg_temp_new_ptr(tcg_ctx);
-                                    gen_load_trap_state_at_tl(dc, r_tsptr, tcg_ctx->cpu_env);
+                                    gen_load_trap_state_at_tl(dc, r_tsptr, uc->cpu_env);
                                     tcg_gen_st_tl(tcg_ctx, cpu_tmp0, r_tsptr,
                                                   offsetof(trap_state,
                                                            tstate));
@@ -4699,7 +4757,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
                                     TCGv_ptr r_tsptr;
 
                                     r_tsptr = tcg_temp_new_ptr(tcg_ctx);
-                                    gen_load_trap_state_at_tl(dc, r_tsptr, tcg_ctx->cpu_env);
+                                    gen_load_trap_state_at_tl(dc, r_tsptr, uc->cpu_env);
                                     tcg_gen_st32_tl(tcg_ctx, cpu_tmp0, r_tsptr,
                                                     offsetof(trap_state, tt));
                                     tcg_temp_free_ptr(tcg_ctx, r_tsptr);
@@ -4710,7 +4768,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
                                     TCGv_ptr r_tickptr;
 
                                     r_tickptr = tcg_temp_new_ptr(tcg_ctx);
-                                    tcg_gen_ld_ptr(tcg_ctx, r_tickptr, tcg_ctx->cpu_env,
+                                    tcg_gen_ld_ptr(tcg_ctx, r_tickptr, uc->cpu_env,
                                                    offsetof(CPUSPARCState, tick));
                                     gen_helper_tick_set_count(tcg_ctx, r_tickptr,
                                                               cpu_tmp0);
@@ -4722,49 +4780,49 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
                                 break;
                             case 6: // pstate
                                 save_state(dc);
-                                gen_helper_wrpstate(tcg_ctx, tcg_ctx->cpu_env, cpu_tmp0);
+                                gen_helper_wrpstate(tcg_ctx, uc->cpu_env, cpu_tmp0);
                                 dc->npc = DYNAMIC_PC;
                                 break;
                             case 7: // tl
                                 save_state(dc);
-                                tcg_gen_st32_tl(tcg_ctx, cpu_tmp0, tcg_ctx->cpu_env,
+                                tcg_gen_st32_tl(tcg_ctx, cpu_tmp0, uc->cpu_env,
                                                offsetof(CPUSPARCState, tl));
                                 dc->npc = DYNAMIC_PC;
                                 break;
                             case 8: // pil
-                                gen_helper_wrpil(tcg_ctx, tcg_ctx->cpu_env, cpu_tmp0);
+                                gen_helper_wrpil(tcg_ctx, uc->cpu_env, cpu_tmp0);
                                 break;
                             case 9: // cwp
-                                gen_helper_wrcwp(tcg_ctx, tcg_ctx->cpu_env, cpu_tmp0);
+                                gen_helper_wrcwp(tcg_ctx, uc->cpu_env, cpu_tmp0);
                                 break;
                             case 10: // cansave
-                                tcg_gen_st32_tl(tcg_ctx, cpu_tmp0, tcg_ctx->cpu_env,
+                                tcg_gen_st32_tl(tcg_ctx, cpu_tmp0, uc->cpu_env,
                                                 offsetof(CPUSPARCState,
                                                          cansave));
                                 break;
                             case 11: // canrestore
-                                tcg_gen_st32_tl(tcg_ctx, cpu_tmp0, tcg_ctx->cpu_env,
+                                tcg_gen_st32_tl(tcg_ctx, cpu_tmp0, uc->cpu_env,
                                                 offsetof(CPUSPARCState,
                                                          canrestore));
                                 break;
                             case 12: // cleanwin
-                                tcg_gen_st32_tl(tcg_ctx, cpu_tmp0, tcg_ctx->cpu_env,
+                                tcg_gen_st32_tl(tcg_ctx, cpu_tmp0, uc->cpu_env,
                                                 offsetof(CPUSPARCState,
                                                          cleanwin));
                                 break;
                             case 13: // otherwin
-                                tcg_gen_st32_tl(tcg_ctx, cpu_tmp0, tcg_ctx->cpu_env,
+                                tcg_gen_st32_tl(tcg_ctx, cpu_tmp0, uc->cpu_env,
                                                 offsetof(CPUSPARCState,
                                                          otherwin));
                                 break;
                             case 14: // wstate
-                                tcg_gen_st32_tl(tcg_ctx, cpu_tmp0, tcg_ctx->cpu_env,
+                                tcg_gen_st32_tl(tcg_ctx, cpu_tmp0, uc->cpu_env,
                                                 offsetof(CPUSPARCState,
                                                          wstate));
                                 break;
                             case 16: // UA2005 gl
                                 CHECK_IU_FEATURE(dc, GL);
-                                gen_helper_wrgl(tcg_ctx, tcg_ctx->cpu_env, cpu_tmp0);
+                                gen_helper_wrgl(tcg_ctx, uc->cpu_env, cpu_tmp0);
                                 break;
                             case 26: // UA2005 strand status
                                 CHECK_IU_FEATURE(dc, HYPV);
@@ -4798,7 +4856,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
                             tcg_gen_xor_tl(tcg_ctx, cpu_tmp0, cpu_src1, cpu_src2);
                             switch (rd) {
                             case 0: // hpstate
-                                tcg_gen_st_i64(tcg_ctx, cpu_tmp0, tcg_ctx->cpu_env,
+                                tcg_gen_st_i64(tcg_ctx, cpu_tmp0, uc->cpu_env,
                                                offsetof(CPUSPARCState,
                                                         hpstate));
                                 save_state(dc);
@@ -4821,7 +4879,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
 
                                     tcg_gen_mov_tl(tcg_ctx, tcg_ctx->cpu_hstick_cmpr, cpu_tmp0);
                                     r_tickptr = tcg_temp_new_ptr(tcg_ctx);
-                                    tcg_gen_ld_ptr(tcg_ctx, r_tickptr, tcg_ctx->cpu_env,
+                                    tcg_gen_ld_ptr(tcg_ctx, r_tickptr, uc->cpu_env,
                                                    offsetof(CPUSPARCState, hstick));
                                     gen_helper_tick_set_limit(tcg_ctx, r_tickptr,
                                                               tcg_ctx->cpu_hstick_cmpr);
@@ -4873,7 +4931,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
                             break;
                         }
                     case 0x2d: /* V9 sdivx */
-                        gen_helper_sdivx(tcg_ctx, cpu_dst, tcg_ctx->cpu_env, cpu_src1, cpu_src2);
+                        gen_helper_sdivx(tcg_ctx, cpu_dst, uc->cpu_env, cpu_src1, cpu_src2);
                         gen_store_gpr(dc, rd, cpu_dst);
                         break;
                     case 0x2e: /* V9 popc */
@@ -5375,7 +5433,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
                         tcg_gen_mov_tl(tcg_ctx, cpu_tmp0, cpu_src1);
                     }
                 }
-                gen_helper_restore(tcg_ctx, tcg_ctx->cpu_env);
+                gen_helper_restore(tcg_ctx, uc->cpu_env);
                 gen_mov_pc_npc(dc);
                 gen_check_align(dc, cpu_tmp0, 3);
                 tcg_gen_mov_tl(tcg_ctx, tcg_ctx->cpu_npc, cpu_tmp0);
@@ -5420,7 +5478,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
                         gen_check_align(dc, cpu_tmp0, 3);
                         tcg_gen_mov_tl(tcg_ctx, tcg_ctx->cpu_npc, cpu_tmp0);
                         dc->npc = DYNAMIC_PC;
-                        gen_helper_rett(tcg_ctx, tcg_ctx->cpu_env);
+                        gen_helper_rett(tcg_ctx, uc->cpu_env);
                     }
                     goto jmp_insn;
 #endif
@@ -5430,11 +5488,11 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
                     /* nop */
                     break;
                 case 0x3c:      /* save */
-                    gen_helper_save(tcg_ctx, tcg_ctx->cpu_env);
+                    gen_helper_save(tcg_ctx, uc->cpu_env);
                     gen_store_gpr(dc, rd, cpu_tmp0);
                     break;
                 case 0x3d:      /* restore */
-                    gen_helper_restore(tcg_ctx, tcg_ctx->cpu_env);
+                    gen_helper_restore(tcg_ctx, uc->cpu_env);
                     gen_store_gpr(dc, rd, cpu_tmp0);
                     break;
 #if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
@@ -5446,14 +5504,14 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
                                 goto priv_insn;
                             dc->npc = DYNAMIC_PC;
                             dc->pc = DYNAMIC_PC;
-                            gen_helper_done(tcg_ctx, tcg_ctx->cpu_env);
+                            gen_helper_done(tcg_ctx, uc->cpu_env);
                             goto jmp_insn;
                         case 1:
                             if (!supervisor(dc))
                                 goto priv_insn;
                             dc->npc = DYNAMIC_PC;
                             dc->pc = DYNAMIC_PC;
-                            gen_helper_retry(tcg_ctx, tcg_ctx->cpu_env);
+                            gen_helper_retry(tcg_ctx, uc->cpu_env);
                             goto jmp_insn;
                         default:
                             goto illegal_insn;
@@ -5497,15 +5555,15 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
                 switch (xop) {
                 case 0x0:       /* ld, V9 lduw, load unsigned word */
                     gen_address_mask(dc, cpu_addr);
-                    tcg_gen_qemu_ld32u(dc->uc, cpu_val, cpu_addr, dc->mem_idx);
+                    tcg_gen_qemu_ld32u(uc, cpu_val, cpu_addr, dc->mem_idx);
                     break;
                 case 0x1:       /* ldub, load unsigned byte */
                     gen_address_mask(dc, cpu_addr);
-                    tcg_gen_qemu_ld8u(dc->uc, cpu_val, cpu_addr, dc->mem_idx);
+                    tcg_gen_qemu_ld8u(uc, cpu_val, cpu_addr, dc->mem_idx);
                     break;
                 case 0x2:       /* lduh, load unsigned halfword */
                     gen_address_mask(dc, cpu_addr);
-                    tcg_gen_qemu_ld16u(dc->uc, cpu_val, cpu_addr, dc->mem_idx);
+                    tcg_gen_qemu_ld16u(uc, cpu_val, cpu_addr, dc->mem_idx);
                     break;
                 case 0x3:       /* ldd, load double word */
                     if (rd & 1)
@@ -5515,7 +5573,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
 
                         gen_address_mask(dc, cpu_addr);
                         t64 = tcg_temp_new_i64(tcg_ctx);
-                        tcg_gen_qemu_ld64(dc->uc, t64, cpu_addr, dc->mem_idx);
+                        tcg_gen_qemu_ld64(uc, t64, cpu_addr, dc->mem_idx);
                         tcg_gen_trunc_i64_tl(tcg_ctx, cpu_val, t64);
                         tcg_gen_ext32u_tl(tcg_ctx, cpu_val, cpu_val);
                         gen_store_gpr(dc, rd + 1, cpu_val);
@@ -5527,11 +5585,11 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
                     break;
                 case 0x9:       /* ldsb, load signed byte */
                     gen_address_mask(dc, cpu_addr);
-                    tcg_gen_qemu_ld8s(dc->uc, cpu_val, cpu_addr, dc->mem_idx);
+                    tcg_gen_qemu_ld8s(uc, cpu_val, cpu_addr, dc->mem_idx);
                     break;
                 case 0xa:       /* ldsh, load signed halfword */
                     gen_address_mask(dc, cpu_addr);
-                    tcg_gen_qemu_ld16s(dc->uc, cpu_val, cpu_addr, dc->mem_idx);
+                    tcg_gen_qemu_ld16s(uc, cpu_val, cpu_addr, dc->mem_idx);
                     break;
                 case 0xd:       /* ldstub */
                     gen_ldstub(dc, cpu_val, cpu_addr, dc->mem_idx);
@@ -5585,11 +5643,11 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
 #ifdef TARGET_SPARC64
                 case 0x08: /* V9 ldsw */
                     gen_address_mask(dc, cpu_addr);
-                    tcg_gen_qemu_ld32s(dc->uc, cpu_val, cpu_addr, dc->mem_idx);
+                    tcg_gen_qemu_ld32s(uc, cpu_val, cpu_addr, dc->mem_idx);
                     break;
                 case 0x0b: /* V9 ldx */
                     gen_address_mask(dc, cpu_addr);
-                    tcg_gen_qemu_ld64(dc->uc, cpu_val, cpu_addr, dc->mem_idx);
+                    tcg_gen_qemu_ld64(uc, cpu_val, cpu_addr, dc->mem_idx);
                     break;
                 case 0x18: /* V9 ldswa */
                     gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TESL);
@@ -5640,7 +5698,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
                 case 0x20:      /* ldf, load fpreg */
                     gen_address_mask(dc, cpu_addr);
                     cpu_dst_32 = gen_dest_fpr_F(dc);
-                    tcg_gen_qemu_ld_i32(dc->uc, cpu_dst_32, cpu_addr,
+                    tcg_gen_qemu_ld_i32(uc, cpu_dst_32, cpu_addr,
                                         dc->mem_idx, MO_TEUL);
                     gen_store_fpr_F(dc, rd, cpu_dst_32);
                     break;
@@ -5649,27 +5707,27 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
                     gen_address_mask(dc, cpu_addr);
                     if (rd == 1) {
                         TCGv_i64 t64 = tcg_temp_new_i64(tcg_ctx);
-                        tcg_gen_qemu_ld_i64(dc->uc, t64, cpu_addr,
+                        tcg_gen_qemu_ld_i64(uc, t64, cpu_addr,
                                             dc->mem_idx, MO_TEQ);
-                        gen_helper_ldxfsr(tcg_ctx, tcg_ctx->cpu_fsr, tcg_ctx->cpu_env, tcg_ctx->cpu_fsr, t64);
+                        gen_helper_ldxfsr(tcg_ctx, tcg_ctx->cpu_fsr, uc->cpu_env, tcg_ctx->cpu_fsr, t64);
                         tcg_temp_free_i64(tcg_ctx, t64);
                         break;
                     }
 #endif
                     cpu_dst_32 = get_temp_i32(dc);
-                    tcg_gen_qemu_ld_i32(dc->uc, cpu_dst_32, cpu_addr,
+                    tcg_gen_qemu_ld_i32(uc, cpu_dst_32, cpu_addr,
                                         dc->mem_idx, MO_TEUL);
-                    gen_helper_ldfsr(tcg_ctx, tcg_ctx->cpu_fsr, tcg_ctx->cpu_env, tcg_ctx->cpu_fsr, cpu_dst_32);
+                    gen_helper_ldfsr(tcg_ctx, tcg_ctx->cpu_fsr, uc->cpu_env, tcg_ctx->cpu_fsr, cpu_dst_32);
                     break;
                 case 0x22:      /* ldqf, load quad fpreg */
                     CHECK_FPU_FEATURE(dc, FLOAT128);
                     gen_address_mask(dc, cpu_addr);
                     cpu_src1_64 = tcg_temp_new_i64(tcg_ctx);
-                    tcg_gen_qemu_ld_i64(dc->uc, cpu_src1_64, cpu_addr, dc->mem_idx,
+                    tcg_gen_qemu_ld_i64(uc, cpu_src1_64, cpu_addr, dc->mem_idx,
                                         MO_TEQ | MO_ALIGN_4);
                     tcg_gen_addi_tl(tcg_ctx, cpu_addr, cpu_addr, 8);
                     cpu_src2_64 = tcg_temp_new_i64(tcg_ctx);
-                    tcg_gen_qemu_ld_i64(dc->uc, cpu_src2_64, cpu_addr, dc->mem_idx,
+                    tcg_gen_qemu_ld_i64(uc, cpu_src2_64, cpu_addr, dc->mem_idx,
                                         MO_TEQ | MO_ALIGN_4);
                     gen_store_fpr_Q(dc, rd, cpu_src1_64, cpu_src2_64);
                     tcg_temp_free_i64(tcg_ctx, cpu_src1_64);
@@ -5678,7 +5736,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
                 case 0x23:      /* lddf, load double fpreg */
                     gen_address_mask(dc, cpu_addr);
                     cpu_dst_64 = gen_dest_fpr_D(dc, rd);
-                    tcg_gen_qemu_ld_i64(dc->uc, cpu_dst_64, cpu_addr, dc->mem_idx,
+                    tcg_gen_qemu_ld_i64(uc, cpu_dst_64, cpu_addr, dc->mem_idx,
                                         MO_TEQ | MO_ALIGN_4);
                     gen_store_fpr_D(dc, rd, cpu_dst_64);
                     break;
@@ -5692,15 +5750,15 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
                 switch (xop) {
                 case 0x4: /* st, store word */
                     gen_address_mask(dc, cpu_addr);
-                    tcg_gen_qemu_st32(dc->uc, cpu_val, cpu_addr, dc->mem_idx);
+                    tcg_gen_qemu_st32(uc, cpu_val, cpu_addr, dc->mem_idx);
                     break;
                 case 0x5: /* stb, store byte */
                     gen_address_mask(dc, cpu_addr);
-                    tcg_gen_qemu_st8(dc->uc, cpu_val, cpu_addr, dc->mem_idx);
+                    tcg_gen_qemu_st8(uc, cpu_val, cpu_addr, dc->mem_idx);
                     break;
                 case 0x6: /* sth, store halfword */
                     gen_address_mask(dc, cpu_addr);
-                    tcg_gen_qemu_st16(dc->uc, cpu_val, cpu_addr, dc->mem_idx);
+                    tcg_gen_qemu_st16(uc, cpu_val, cpu_addr, dc->mem_idx);
                     break;
                 case 0x7: /* std, store double word */
                     if (rd & 1)
@@ -5713,7 +5771,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
                         lo = gen_load_gpr(dc, rd + 1);
                         t64 = tcg_temp_new_i64(tcg_ctx);
                         tcg_gen_concat_tl_i64(tcg_ctx, t64, lo, cpu_val);
-                        tcg_gen_qemu_st64(dc->uc, t64, cpu_addr, dc->mem_idx);
+                        tcg_gen_qemu_st64(uc, t64, cpu_addr, dc->mem_idx);
                         tcg_temp_free_i64(tcg_ctx, t64);
                     }
                     break;
@@ -5737,7 +5795,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
 #ifdef TARGET_SPARC64
                 case 0x0e: /* V9 stx */
                     gen_address_mask(dc, cpu_addr);
-                    tcg_gen_qemu_st64(dc->uc, cpu_val, cpu_addr, dc->mem_idx);
+                    tcg_gen_qemu_st64(uc, cpu_val, cpu_addr, dc->mem_idx);
                     break;
                 case 0x1e: /* V9 stxa */
                     gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_TEQ);
@@ -5755,7 +5813,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
                 case 0x24: /* stf, store fpreg */
                     gen_address_mask(dc, cpu_addr);
                     cpu_src1_32 = gen_load_fpr_F(dc, rd);
-                    tcg_gen_qemu_st_i32(dc->uc, cpu_src1_32, cpu_addr,
+                    tcg_gen_qemu_st_i32(uc, cpu_src1_32, cpu_addr,
                                         dc->mem_idx, MO_TEUL);
                     break;
                 case 0x25: /* stfsr, V9 stxfsr */
@@ -5763,11 +5821,11 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
 #ifdef TARGET_SPARC64
                         gen_address_mask(dc, cpu_addr);
                         if (rd == 1) {
-                            tcg_gen_qemu_st64(dc->uc, tcg_ctx->cpu_fsr, cpu_addr, dc->mem_idx);
+                            tcg_gen_qemu_st64(uc, tcg_ctx->cpu_fsr, cpu_addr, dc->mem_idx);
                             break;
                         }
 #endif
-                        tcg_gen_qemu_st32(dc->uc, tcg_ctx->cpu_fsr, cpu_addr, dc->mem_idx);
+                        tcg_gen_qemu_st32(uc, tcg_ctx->cpu_fsr, cpu_addr, dc->mem_idx);
                     }
                     break;
                 case 0x26:
@@ -5781,11 +5839,11 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
                        For qemu, this avoids having to probe the second page
                        before performing the first write.  */
                     cpu_src1_64 = gen_load_fpr_Q0(dc, rd);
-                    tcg_gen_qemu_st_i64(dc->uc, cpu_src1_64, cpu_addr,
+                    tcg_gen_qemu_st_i64(uc, cpu_src1_64, cpu_addr,
                                         dc->mem_idx, MO_TEQ | MO_ALIGN_16);
                     tcg_gen_addi_tl(tcg_ctx, cpu_addr, cpu_addr, 8);
                     cpu_src2_64 = gen_load_fpr_Q1(dc, rd);
-                    tcg_gen_qemu_st_i64(dc->uc, cpu_src1_64, cpu_addr,
+                    tcg_gen_qemu_st_i64(uc, cpu_src1_64, cpu_addr,
                                         dc->mem_idx, MO_TEQ);
                     break;
 #else /* !TARGET_SPARC64 */
@@ -5804,7 +5862,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
                 case 0x27: /* stdf, store double fpreg */
                     gen_address_mask(dc, cpu_addr);
                     cpu_src1_64 = gen_load_fpr_D(dc, rd);
-                    tcg_gen_qemu_st_i64(dc->uc, cpu_src1_64, cpu_addr, dc->mem_idx,
+                    tcg_gen_qemu_st_i64(uc, cpu_src1_64, cpu_addr, dc->mem_idx,
                                         MO_TEQ | MO_ALIGN_4);
                     break;
                 default:
@@ -5924,16 +5982,17 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
 void gen_intermediate_code(CPUState *cs, TranslationBlock * tb)
 {
     CPUSPARCState *env = cs->env_ptr;
+    struct uc_struct *uc = env->uc;
     target_ulong pc_start, last_pc;
     DisasContext dc1, *dc = &dc1;
     int num_insns = 0;
     int max_insns;
     unsigned int insn;
-    TCGContext *tcg_ctx = env->uc->tcg_ctx;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     bool block_full = false;
 
     memset(dc, 0, sizeof(DisasContext));
-    dc->uc = env->uc;
+    dc->uc = uc;
     dc->tb = tb;
     pc_start = tb->pc;
     dc->pc = pc_start;
@@ -5957,9 +6016,9 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock * tb)
 #endif
 
     // early check to see if the address of this block is the until address
-    if (pc_start == env->uc->addr_end) {
+    if (pc_start == uc->addr_end) {
         gen_tb_start(tcg_ctx, tb);
-        gen_helper_power_down(tcg_ctx, tcg_ctx->cpu_env);
+        gen_helper_power_down(tcg_ctx, uc->cpu_env);
         goto done_generating;
     }
 
@@ -5972,10 +6031,10 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock * tb)
     }
 
     // Unicorn: early check to see if the address of this block is the until address
-    if (tb->pc == env->uc->addr_end) {
+    if (tb->pc == uc->addr_end) {
         gen_tb_start(tcg_ctx, tb);
         save_state(dc);
-        gen_helper_power_down(tcg_ctx, tcg_ctx->cpu_env);
+        gen_helper_power_down(tcg_ctx, uc->cpu_env);
         goto done_generating;
     }
 
@@ -5984,11 +6043,11 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock * tb)
     // Only hook this block if it is not broken from previous translation due to
     // full translation cache
 #if 0
-    if (!env->uc->block_full && HOOK_EXISTS_BOUNDED(env->uc, UC_HOOK_BLOCK, pc_start)) {
+    if (!env->uc->block_full && HOOK_EXISTS_BOUNDED(uc, UC_HOOK_BLOCK, pc_start)) {
         // save block address to see if we need to patch block size later
         env->uc->block_addr = pc_start;
         env->uc->size_arg = tcg_ctx->gen_op_buf[tcg_ctx->gen_op_buf[0].prev].args;
-        gen_uc_tracecode(tcg_ctx, 0xf8f8f8f8, UC_HOOK_BLOCK_IDX, env->uc, pc_start);
+        gen_uc_tracecode(tcg_ctx, 0xf8f8f8f8, UC_HOOK_BLOCK_IDX, uc, pc_start);
     }
 #endif
 
@@ -6007,7 +6066,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock * tb)
             if (dc->pc != pc_start) {
                 save_state(dc);
             }
-            gen_helper_debug(tcg_ctx, tcg_ctx->cpu_env);
+            gen_helper_debug(tcg_ctx, uc->cpu_env);
             tcg_gen_exit_tb(tcg_ctx, 0);
             dc->is_br = 1;
             goto exit_gen_loop;
@@ -6021,9 +6080,9 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock * tb)
 #endif
 
         // Unicorn: end address tells us to stop emulation
-        if (dc->pc == dc->uc->addr_end) {
+        if (dc->pc == uc->addr_end) {
             save_state(dc);
-            gen_helper_power_down(tcg_ctx, tcg_ctx->cpu_env);
+            gen_helper_power_down(tcg_ctx, uc->cpu_env);
             break;
         } else {
             insn = cpu_ldl_code(env, dc->pc);
@@ -6086,9 +6145,7 @@ done_generating:
 
 void sparc_tcg_init(struct uc_struct *uc)
 {
-    SPARCCPU *cpu = SPARC_CPU(s->uc, uc->cpu);
-    CPUSPARCState *env = &cpu->env;
-    TCGContext *tcg_ctx = env->uc->tcg_ctx;
+    TCGContext *tcg_ctx = uc->tcg_ctx;
     unsigned int i;
 
     static const char gregnames[32][4] = {
@@ -6108,87 +6165,85 @@ void sparc_tcg_init(struct uc_struct *uc)
     if (uc->init_tcg) {
         return;
     }
-    tcg_ctx->cpu_env = tcg_global_reg_new_ptr(tcg_ctx, TCG_AREG0, "env");
-    tcg_ctx->tcg_env = tcg_ctx->cpu_env;
 
-    tcg_ctx->cpu_regwptr = tcg_global_mem_new_ptr(tcg_ctx, tcg_ctx->cpu_env,
+    tcg_ctx->cpu_regwptr = tcg_global_mem_new_ptr(tcg_ctx, uc->cpu_env,
             offsetof(CPUSPARCState, regwptr),
             "regwptr");
 #ifdef TARGET_SPARC64
-    tcg_ctx->cpu_xcc = tcg_global_mem_new_i32(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPUSPARCState, xcc),
+    tcg_ctx->cpu_xcc = tcg_global_mem_new_i32(tcg_ctx, uc->cpu_env, offsetof(CPUSPARCState, xcc),
             "xcc");
-    tcg_ctx->cpu_fprs = tcg_global_mem_new_i32(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPUSPARCState, fprs),
+    tcg_ctx->cpu_fprs = tcg_global_mem_new_i32(tcg_ctx, uc->cpu_env, offsetof(CPUSPARCState, fprs),
             "fprs");
 
-    tcg_ctx->cpu_gsr = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPUSPARCState, gsr),
+    tcg_ctx->cpu_gsr = tcg_global_mem_new(tcg_ctx, uc->cpu_env, offsetof(CPUSPARCState, gsr),
             "gsr");
 
-    tcg_ctx->cpu_tick_cmpr = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env,
+    tcg_ctx->cpu_tick_cmpr = tcg_global_mem_new(tcg_ctx, uc->cpu_env,
             offsetof(CPUSPARCState, tick_cmpr),
             "tick_cmpr");
 
-    tcg_ctx->cpu_stick_cmpr = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env,
+    tcg_ctx->cpu_stick_cmpr = tcg_global_mem_new(tcg_ctx, uc->cpu_env,
             offsetof(CPUSPARCState, stick_cmpr),
             "stick_cmpr");
 
-    tcg_ctx->cpu_hstick_cmpr = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env,
+    tcg_ctx->cpu_hstick_cmpr = tcg_global_mem_new(tcg_ctx, uc->cpu_env,
             offsetof(CPUSPARCState, hstick_cmpr),
             "hstick_cmpr");
 
-    tcg_ctx->cpu_hintp = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPUSPARCState, hintp),
+    tcg_ctx->cpu_hintp = tcg_global_mem_new(tcg_ctx, uc->cpu_env, offsetof(CPUSPARCState, hintp),
             "hintp");
 
-    tcg_ctx->cpu_htba = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPUSPARCState, htba),
+    tcg_ctx->cpu_htba = tcg_global_mem_new(tcg_ctx, uc->cpu_env, offsetof(CPUSPARCState, htba),
             "htba");
 
-    tcg_ctx->cpu_hver = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPUSPARCState, hver),
+    tcg_ctx->cpu_hver = tcg_global_mem_new(tcg_ctx, uc->cpu_env, offsetof(CPUSPARCState, hver),
             "hver");
 
-    tcg_ctx->cpu_ssr = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env,
+    tcg_ctx->cpu_ssr = tcg_global_mem_new(tcg_ctx, uc->cpu_env,
             offsetof(CPUSPARCState, ssr), "ssr");
 
-    tcg_ctx->cpu_ver = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env,
+    tcg_ctx->cpu_ver = tcg_global_mem_new(tcg_ctx, uc->cpu_env,
             offsetof(CPUSPARCState, version), "ver");
 #else
-    tcg_ctx->cpu_wim = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPUSPARCState, wim),
+    tcg_ctx->cpu_wim = tcg_global_mem_new(tcg_ctx, uc->cpu_env, offsetof(CPUSPARCState, wim),
             "wim");
 #endif
-    tcg_ctx->cpu_cond = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPUSPARCState, cond),
+    tcg_ctx->cpu_cond = tcg_global_mem_new(tcg_ctx, uc->cpu_env, offsetof(CPUSPARCState, cond),
             "cond");
 
-    tcg_ctx->cpu_cc_src = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPUSPARCState, cc_src),
+    tcg_ctx->cpu_cc_src = tcg_global_mem_new(tcg_ctx, uc->cpu_env, offsetof(CPUSPARCState, cc_src),
             "cc_src");
 
-    tcg_ctx->cpu_cc_src2 = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env,
+    tcg_ctx->cpu_cc_src2 = tcg_global_mem_new(tcg_ctx, uc->cpu_env,
             offsetof(CPUSPARCState, cc_src2),
             "cc_src2");
 
-    tcg_ctx->cpu_cc_dst = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPUSPARCState, cc_dst),
+    tcg_ctx->cpu_cc_dst = tcg_global_mem_new(tcg_ctx, uc->cpu_env, offsetof(CPUSPARCState, cc_dst),
             "cc_dst");
 
-    tcg_ctx->cpu_cc_op = tcg_global_mem_new_i32(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPUSPARCState, cc_op),
+    tcg_ctx->cpu_cc_op = tcg_global_mem_new_i32(tcg_ctx, uc->cpu_env, offsetof(CPUSPARCState, cc_op),
             "cc_op");
-    tcg_ctx->cpu_psr = tcg_global_mem_new_i32(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPUSPARCState, psr),
+    tcg_ctx->cpu_psr = tcg_global_mem_new_i32(tcg_ctx, uc->cpu_env, offsetof(CPUSPARCState, psr),
             "psr");
 
-    tcg_ctx->cpu_fsr = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPUSPARCState, fsr),
+    tcg_ctx->cpu_fsr = tcg_global_mem_new(tcg_ctx, uc->cpu_env, offsetof(CPUSPARCState, fsr),
             "fsr");
 
-    tcg_ctx->sparc_cpu_pc = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPUSPARCState, pc),
+    tcg_ctx->sparc_cpu_pc = tcg_global_mem_new(tcg_ctx, uc->cpu_env, offsetof(CPUSPARCState, pc),
             "pc");
 
-    tcg_ctx->cpu_npc = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPUSPARCState, npc),
+    tcg_ctx->cpu_npc = tcg_global_mem_new(tcg_ctx, uc->cpu_env, offsetof(CPUSPARCState, npc),
             "npc");
 
-    tcg_ctx->cpu_y = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPUSPARCState, y), "y");
+    tcg_ctx->cpu_y = tcg_global_mem_new(tcg_ctx, uc->cpu_env, offsetof(CPUSPARCState, y), "y");
 #ifndef CONFIG_USER_ONLY
-    tcg_ctx->cpu_tbr = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPUSPARCState, tbr),
+    tcg_ctx->cpu_tbr = tcg_global_mem_new(tcg_ctx, uc->cpu_env, offsetof(CPUSPARCState, tbr),
             "tbr");
 #endif
 
     tcg_ctx->cpu_regs[0] = NULL;
     for (i = 1; i < 8; ++i) {
-        tcg_ctx->cpu_regs_sparc[i] = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env,
+        tcg_ctx->cpu_regs_sparc[i] = tcg_global_mem_new(tcg_ctx, uc->cpu_env,
                                                         offsetof(CPUSPARCState, gregs[i]),
                                                         gregnames[i]);
     }
@@ -6200,7 +6255,7 @@ void sparc_tcg_init(struct uc_struct *uc)
     }
 
     for (i = 0; i < TARGET_DPREGS; i++) {
-        tcg_ctx->cpu_fpr[i] = tcg_global_mem_new_i64(tcg_ctx, tcg_ctx->cpu_env,
+        tcg_ctx->cpu_fpr[i] = tcg_global_mem_new_i64(tcg_ctx, uc->cpu_env,
                 offsetof(CPUSPARCState, fpr[i]),
                 fregnames[i]);
     }
diff --git a/qemu/tcg/tcg-op-gvec.c b/qemu/tcg/tcg-op-gvec.c
index ef72f2c6..ff6a76fc 100644
--- a/qemu/tcg/tcg-op-gvec.c
+++ b/qemu/tcg/tcg-op-gvec.c
@@ -94,8 +94,8 @@ void tcg_gen_gvec_2_ool(TCGContext *s, uint32_t dofs, uint32_t aofs,
     a0 = tcg_temp_new_ptr(s);
     a1 = tcg_temp_new_ptr(s);
 
-    tcg_gen_addi_ptr(s, a0, s->cpu_env, dofs);
-    tcg_gen_addi_ptr(s, a1, s->cpu_env, aofs);
+    tcg_gen_addi_ptr(s, a0, s->uc->cpu_env, dofs);
+    tcg_gen_addi_ptr(s, a1, s->uc->cpu_env, aofs);
 
     fn(s, a0, a1, desc);
 
@@ -116,8 +116,8 @@ void tcg_gen_gvec_2i_ool(TCGContext *s, uint32_t dofs, uint32_t aofs, TCGv_i64 c
     a0 = tcg_temp_new_ptr(s);
     a1 = tcg_temp_new_ptr(s);
 
-    tcg_gen_addi_ptr(s, a0, s->cpu_env, dofs);
-    tcg_gen_addi_ptr(s, a1, s->cpu_env, aofs);
+    tcg_gen_addi_ptr(s, a0, s->uc->cpu_env, dofs);
+    tcg_gen_addi_ptr(s, a1, s->uc->cpu_env, aofs);
 
     fn(s, a0, a1, c, desc);
 
@@ -138,9 +138,9 @@ void tcg_gen_gvec_3_ool(TCGContext *s, uint32_t dofs, uint32_t aofs, uint32_t bo
     a1 = tcg_temp_new_ptr(s);
     a2 = tcg_temp_new_ptr(s);
 
-    tcg_gen_addi_ptr(s, a0, s->cpu_env, dofs);
-    tcg_gen_addi_ptr(s, a1, s->cpu_env, aofs);
-    tcg_gen_addi_ptr(s, a2, s->cpu_env, bofs);
+    tcg_gen_addi_ptr(s, a0, s->uc->cpu_env, dofs);
+    tcg_gen_addi_ptr(s, a1, s->uc->cpu_env, aofs);
+    tcg_gen_addi_ptr(s, a2, s->uc->cpu_env, bofs);
 
     fn(s, a0, a1, a2, desc);
 
@@ -163,10 +163,10 @@ void tcg_gen_gvec_4_ool(TCGContext *s, uint32_t dofs, uint32_t aofs, uint32_t bo
     a2 = tcg_temp_new_ptr(s);
     a3 = tcg_temp_new_ptr(s);
 
-    tcg_gen_addi_ptr(s, a0, s->cpu_env, dofs);
-    tcg_gen_addi_ptr(s, a1, s->cpu_env, aofs);
-    tcg_gen_addi_ptr(s, a2, s->cpu_env, bofs);
-    tcg_gen_addi_ptr(s, a3, s->cpu_env, cofs);
+    tcg_gen_addi_ptr(s, a0, s->uc->cpu_env, dofs);
+    tcg_gen_addi_ptr(s, a1, s->uc->cpu_env, aofs);
+    tcg_gen_addi_ptr(s, a2, s->uc->cpu_env, bofs);
+    tcg_gen_addi_ptr(s, a3, s->uc->cpu_env, cofs);
 
     fn(s, a0, a1, a2, a3, desc);
 
@@ -191,11 +191,11 @@ void tcg_gen_gvec_5_ool(TCGContext *s, uint32_t dofs, uint32_t aofs, uint32_t bo
     a3 = tcg_temp_new_ptr(s);
     a4 = tcg_temp_new_ptr(s);
 
-    tcg_gen_addi_ptr(s, a0, s->cpu_env, dofs);
-    tcg_gen_addi_ptr(s, a1, s->cpu_env, aofs);
-    tcg_gen_addi_ptr(s, a2, s->cpu_env, bofs);
-    tcg_gen_addi_ptr(s, a3, s->cpu_env, cofs);
-    tcg_gen_addi_ptr(s, a4, s->cpu_env, xofs);
+    tcg_gen_addi_ptr(s, a0, s->uc->cpu_env, dofs);
+    tcg_gen_addi_ptr(s, a1, s->uc->cpu_env, aofs);
+    tcg_gen_addi_ptr(s, a2, s->uc->cpu_env, bofs);
+    tcg_gen_addi_ptr(s, a3, s->uc->cpu_env, cofs);
+    tcg_gen_addi_ptr(s, a4, s->uc->cpu_env, xofs);
 
     fn(s, a0, a1, a2, a3, a4, desc);
 
@@ -219,8 +219,8 @@ void tcg_gen_gvec_2_ptr(TCGContext *s, uint32_t dofs, uint32_t aofs,
     a0 = tcg_temp_new_ptr(s);
     a1 = tcg_temp_new_ptr(s);
 
-    tcg_gen_addi_ptr(s, a0, s->cpu_env, dofs);
-    tcg_gen_addi_ptr(s, a1, s->cpu_env, aofs);
+    tcg_gen_addi_ptr(s, a0, s->uc->cpu_env, dofs);
+    tcg_gen_addi_ptr(s, a1, s->uc->cpu_env, aofs);
 
     fn(s, a0, a1, ptr, desc);
 
@@ -242,9 +242,9 @@ void tcg_gen_gvec_3_ptr(TCGContext *s, uint32_t dofs, uint32_t aofs, uint32_t bo
     a1 = tcg_temp_new_ptr(s);
     a2 = tcg_temp_new_ptr(s);
 
-    tcg_gen_addi_ptr(s, a0, s->cpu_env, dofs);
-    tcg_gen_addi_ptr(s, a1, s->cpu_env, aofs);
-    tcg_gen_addi_ptr(s, a2, s->cpu_env, bofs);
+    tcg_gen_addi_ptr(s, a0, s->uc->cpu_env, dofs);
+    tcg_gen_addi_ptr(s, a1, s->uc->cpu_env, aofs);
+    tcg_gen_addi_ptr(s, a2, s->uc->cpu_env, bofs);
 
     fn(s, a0, a1, a2, ptr, desc);
 
@@ -269,10 +269,10 @@ void tcg_gen_gvec_4_ptr(TCGContext *s, uint32_t dofs, uint32_t aofs, uint32_t bo
     a2 = tcg_temp_new_ptr(s);
     a3 = tcg_temp_new_ptr(s);
 
-    tcg_gen_addi_ptr(s, a0, s->cpu_env, dofs);
-    tcg_gen_addi_ptr(s, a1, s->cpu_env, aofs);
-    tcg_gen_addi_ptr(s, a2, s->cpu_env, bofs);
-    tcg_gen_addi_ptr(s, a3, s->cpu_env, cofs);
+    tcg_gen_addi_ptr(s, a0, s->uc->cpu_env, dofs);
+    tcg_gen_addi_ptr(s, a1, s->uc->cpu_env, aofs);
+    tcg_gen_addi_ptr(s, a2, s->uc->cpu_env, bofs);
+    tcg_gen_addi_ptr(s, a3, s->uc->cpu_env, cofs);
 
     fn(s, a0, a1, a2, a3, ptr, desc);
 
@@ -416,17 +416,17 @@ static void do_dup(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t oprsz,
         i = 0;
         if (TCG_TARGET_HAS_v256) {
             for (; i + 32 <= oprsz; i += 32) {
-                tcg_gen_stl_vec(s, t_vec, s->cpu_env, dofs + i, TCG_TYPE_V256);
+                tcg_gen_stl_vec(s, t_vec, s->uc->cpu_env, dofs + i, TCG_TYPE_V256);
             }
         }
         if (TCG_TARGET_HAS_v128) {
             for (; i + 16 <= oprsz; i += 16) {
-                tcg_gen_stl_vec(s, t_vec, s->cpu_env, dofs + i, TCG_TYPE_V128);
+                tcg_gen_stl_vec(s, t_vec, s->uc->cpu_env, dofs + i, TCG_TYPE_V128);
             }
         }
         if (TCG_TARGET_HAS_v64) {
             for (; i < oprsz; i += 8) {
-                tcg_gen_stl_vec(s, t_vec, s->cpu_env, dofs + i, TCG_TYPE_V64);
+                tcg_gen_stl_vec(s, t_vec, s->uc->cpu_env, dofs + i, TCG_TYPE_V64);
             }
         }
         tcg_temp_free_vec(s, t_vec);
@@ -473,14 +473,14 @@ static void do_dup(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t oprsz,
         /* Implement inline if we picked an implementation size above.  */
         if (t_32) {
             for (i = 0; i < oprsz; i += 4) {
-                tcg_gen_st_i32(s, t_32, s->cpu_env, dofs + i);
+                tcg_gen_st_i32(s, t_32, s->uc->cpu_env, dofs + i);
             }
             tcg_temp_free_i32(s, t_32);
             goto done;
         }
         if (t_64) {
             for (i = 0; i < oprsz; i += 8) {
-                tcg_gen_st_i64(s, t_64, s->cpu_env, dofs + i);
+                tcg_gen_st_i64(s, t_64, s->uc->cpu_env, dofs + i);
             }
             tcg_temp_free_i64(s, t_64);
             goto done;
@@ -489,7 +489,7 @@ static void do_dup(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t oprsz,
 
     /* Otherwise implement out of line.  */
     t_ptr = tcg_temp_new_ptr(s);
-    tcg_gen_addi_ptr(s, t_ptr, s->cpu_env, dofs);
+    tcg_gen_addi_ptr(s, t_ptr, s->uc->cpu_env, dofs);
     t_desc = tcg_const_i32(s, simd_desc(oprsz, maxsz, 0));
 
     if (vece == MO_64) {
@@ -550,9 +550,9 @@ static void expand_2_i32(TCGContext *s, uint32_t dofs, uint32_t aofs, uint32_t o
     uint32_t i;
 
     for (i = 0; i < oprsz; i += 4) {
-        tcg_gen_ld_i32(s, t0, s->cpu_env, aofs + i);
+        tcg_gen_ld_i32(s, t0, s->uc->cpu_env, aofs + i);
         fni(s, t0, t0);
-        tcg_gen_st_i32(s, t0, s->cpu_env, dofs + i);
+        tcg_gen_st_i32(s, t0, s->uc->cpu_env, dofs + i);
     }
     tcg_temp_free_i32(s, t0);
 }
@@ -566,12 +566,12 @@ static void expand_2i_i32(TCGContext *s, uint32_t dofs, uint32_t aofs, uint32_t
     uint32_t i;
 
     for (i = 0; i < oprsz; i += 4) {
-        tcg_gen_ld_i32(s, t0, s->cpu_env, aofs + i);
+        tcg_gen_ld_i32(s, t0, s->uc->cpu_env, aofs + i);
         if (load_dest) {
-            tcg_gen_ld_i32(s, t1, s->cpu_env, dofs + i);
+            tcg_gen_ld_i32(s, t1, s->uc->cpu_env, dofs + i);
         }
         fni(s, t1, t0, c);
-        tcg_gen_st_i32(s, t1, s->cpu_env, dofs + i);
+        tcg_gen_st_i32(s, t1, s->uc->cpu_env, dofs + i);
     }
     tcg_temp_free_i32(s, t0);
     tcg_temp_free_i32(s, t1);
@@ -586,13 +586,13 @@ static void expand_2s_i32(TCGContext *s, uint32_t dofs, uint32_t aofs, uint32_t
     uint32_t i;
 
     for (i = 0; i < oprsz; i += 4) {
-        tcg_gen_ld_i32(s, t0, s->cpu_env, aofs + i);
+        tcg_gen_ld_i32(s, t0, s->uc->cpu_env, aofs + i);
         if (scalar_first) {
             fni(s, t1, c, t0);
         } else {
             fni(s, t1, t0, c);
         }
-        tcg_gen_st_i32(s, t1, s->cpu_env, dofs + i);
+        tcg_gen_st_i32(s, t1, s->uc->cpu_env, dofs + i);
     }
     tcg_temp_free_i32(s, t0);
     tcg_temp_free_i32(s, t1);
@@ -609,13 +609,13 @@ static void expand_3_i32(TCGContext *s, uint32_t dofs, uint32_t aofs,
     uint32_t i;
 
     for (i = 0; i < oprsz; i += 4) {
-        tcg_gen_ld_i32(s, t0, s->cpu_env, aofs + i);
-        tcg_gen_ld_i32(s, t1, s->cpu_env, bofs + i);
+        tcg_gen_ld_i32(s, t0, s->uc->cpu_env, aofs + i);
+        tcg_gen_ld_i32(s, t1, s->uc->cpu_env, bofs + i);
         if (load_dest) {
-            tcg_gen_ld_i32(s, t2, s->cpu_env, dofs + i);
+            tcg_gen_ld_i32(s, t2, s->uc->cpu_env, dofs + i);
         }
         fni(s, t2, t0, t1);
-        tcg_gen_st_i32(s, t2, s->cpu_env, dofs + i);
+        tcg_gen_st_i32(s, t2, s->uc->cpu_env, dofs + i);
     }
     tcg_temp_free_i32(s, t2);
     tcg_temp_free_i32(s, t1);
@@ -634,11 +634,11 @@ static void expand_4_i32(TCGContext *s, uint32_t dofs, uint32_t aofs, uint32_t b
     uint32_t i;
 
     for (i = 0; i < oprsz; i += 4) {
-        tcg_gen_ld_i32(s, t1, s->cpu_env, aofs + i);
-        tcg_gen_ld_i32(s, t2, s->cpu_env, bofs + i);
-        tcg_gen_ld_i32(s, t3, s->cpu_env, cofs + i);
+        tcg_gen_ld_i32(s, t1, s->uc->cpu_env, aofs + i);
+        tcg_gen_ld_i32(s, t2, s->uc->cpu_env, bofs + i);
+        tcg_gen_ld_i32(s, t3, s->uc->cpu_env, cofs + i);
         fni(s, t0, t1, t2, t3);
-        tcg_gen_st_i32(s, t0, s->cpu_env, dofs + i);
+        tcg_gen_st_i32(s, t0, s->uc->cpu_env, dofs + i);
     }
     tcg_temp_free_i32(s, t3);
     tcg_temp_free_i32(s, t2);
@@ -654,9 +654,9 @@ static void expand_2_i64(TCGContext *s, uint32_t dofs, uint32_t aofs, uint32_t o
     uint32_t i;
 
     for (i = 0; i < oprsz; i += 8) {
-        tcg_gen_ld_i64(s, t0, s->cpu_env, aofs + i);
+        tcg_gen_ld_i64(s, t0, s->uc->cpu_env, aofs + i);
         fni(s, t0, t0);
-        tcg_gen_st_i64(s, t0, s->cpu_env, dofs + i);
+        tcg_gen_st_i64(s, t0, s->uc->cpu_env, dofs + i);
     }
     tcg_temp_free_i64(s, t0);
 }
@@ -670,12 +670,12 @@ static void expand_2i_i64(TCGContext *s, uint32_t dofs, uint32_t aofs, uint32_t
     uint32_t i;
 
     for (i = 0; i < oprsz; i += 8) {
-        tcg_gen_ld_i64(s, t0, s->cpu_env, aofs + i);
+        tcg_gen_ld_i64(s, t0, s->uc->cpu_env, aofs + i);
         if (load_dest) {
-            tcg_gen_ld_i64(s, t1, s->cpu_env, dofs + i);
+            tcg_gen_ld_i64(s, t1, s->uc->cpu_env, dofs + i);
         }
         fni(s, t1, t0, c);
-        tcg_gen_st_i64(s, t1, s->cpu_env, dofs + i);
+        tcg_gen_st_i64(s, t1, s->uc->cpu_env, dofs + i);
     }
     tcg_temp_free_i64(s, t0);
     tcg_temp_free_i64(s, t1);
@@ -690,13 +690,13 @@ static void expand_2s_i64(TCGContext *s, uint32_t dofs, uint32_t aofs, uint32_t
     uint32_t i;
 
     for (i = 0; i < oprsz; i += 8) {
-        tcg_gen_ld_i64(s, t0, s->cpu_env, aofs + i);
+        tcg_gen_ld_i64(s, t0, s->uc->cpu_env, aofs + i);
         if (scalar_first) {
             fni(s, t1, c, t0);
         } else {
             fni(s, t1, t0, c);
         }
-        tcg_gen_st_i64(s, t1, s->cpu_env, dofs + i);
+        tcg_gen_st_i64(s, t1, s->uc->cpu_env, dofs + i);
     }
     tcg_temp_free_i64(s, t0);
     tcg_temp_free_i64(s, t1);
@@ -713,13 +713,13 @@ static void expand_3_i64(TCGContext *s, uint32_t dofs, uint32_t aofs,
     uint32_t i;
 
     for (i = 0; i < oprsz; i += 8) {
-        tcg_gen_ld_i64(s, t0, s->cpu_env, aofs + i);
-        tcg_gen_ld_i64(s, t1, s->cpu_env, bofs + i);
+        tcg_gen_ld_i64(s, t0, s->uc->cpu_env, aofs + i);
+        tcg_gen_ld_i64(s, t1, s->uc->cpu_env, bofs + i);
         if (load_dest) {
-            tcg_gen_ld_i64(s, t2, s->cpu_env, dofs + i);
+            tcg_gen_ld_i64(s, t2, s->uc->cpu_env, dofs + i);
         }
         fni(s, t2, t0, t1);
-        tcg_gen_st_i64(s, t2, s->cpu_env, dofs + i);
+        tcg_gen_st_i64(s, t2, s->uc->cpu_env, dofs + i);
     }
     tcg_temp_free_i64(s, t2);
     tcg_temp_free_i64(s, t1);
@@ -738,11 +738,11 @@ static void expand_4_i64(TCGContext *s, uint32_t dofs, uint32_t aofs, uint32_t b
     uint32_t i;
 
     for (i = 0; i < oprsz; i += 8) {
-        tcg_gen_ld_i64(s, t1, s->cpu_env, aofs + i);
-        tcg_gen_ld_i64(s, t2, s->cpu_env, bofs + i);
-        tcg_gen_ld_i64(s, t3, s->cpu_env, cofs + i);
+        tcg_gen_ld_i64(s, t1, s->uc->cpu_env, aofs + i);
+        tcg_gen_ld_i64(s, t2, s->uc->cpu_env, bofs + i);
+        tcg_gen_ld_i64(s, t3, s->uc->cpu_env, cofs + i);
         fni(s, t0, t1, t2, t3);
-        tcg_gen_st_i64(s, t0, s->cpu_env, dofs + i);
+        tcg_gen_st_i64(s, t0, s->uc->cpu_env, dofs + i);
     }
     tcg_temp_free_i64(s, t3);
     tcg_temp_free_i64(s, t2);
@@ -759,9 +759,9 @@ static void expand_2_vec(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t a
     uint32_t i;
 
     for (i = 0; i < oprsz; i += tysz) {
-        tcg_gen_ld_vec(s, t0, s->cpu_env, aofs + i);
+        tcg_gen_ld_vec(s, t0, s->uc->cpu_env, aofs + i);
         fni(s, vece, t0, t0);
-        tcg_gen_st_vec(s, t0, s->cpu_env, dofs + i);
+        tcg_gen_st_vec(s, t0, s->uc->cpu_env, dofs + i);
     }
     tcg_temp_free_vec(s, t0);
 }
@@ -778,12 +778,12 @@ static void expand_2i_vec(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t
     uint32_t i;
 
     for (i = 0; i < oprsz; i += tysz) {
-        tcg_gen_ld_vec(s, t0, s->cpu_env, aofs + i);
+        tcg_gen_ld_vec(s, t0, s->uc->cpu_env, aofs + i);
         if (load_dest) {
-            tcg_gen_ld_vec(s, t1, s->cpu_env, dofs + i);
+            tcg_gen_ld_vec(s, t1, s->uc->cpu_env, dofs + i);
         }
         fni(s, vece, t1, t0, c);
-        tcg_gen_st_vec(s, t1, s->cpu_env, dofs + i);
+        tcg_gen_st_vec(s, t1, s->uc->cpu_env, dofs + i);
     }
     tcg_temp_free_vec(s, t0);
     tcg_temp_free_vec(s, t1);
@@ -799,13 +799,13 @@ static void expand_2s_vec(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t
     uint32_t i;
 
     for (i = 0; i < oprsz; i += tysz) {
-        tcg_gen_ld_vec(s, t0, s->cpu_env, aofs + i);
+        tcg_gen_ld_vec(s, t0, s->uc->cpu_env, aofs + i);
         if (scalar_first) {
             fni(s, vece, t1, c, t0);
         } else {
             fni(s, vece, t1, t0, c);
         }
-        tcg_gen_st_vec(s, t1, s->cpu_env, dofs + i);
+        tcg_gen_st_vec(s, t1, s->uc->cpu_env, dofs + i);
     }
     tcg_temp_free_vec(s, t0);
     tcg_temp_free_vec(s, t1);
@@ -823,13 +823,13 @@ static void expand_3_vec(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t a
     uint32_t i;
 
     for (i = 0; i < oprsz; i += tysz) {
-        tcg_gen_ld_vec(s, t0, s->cpu_env, aofs + i);
-        tcg_gen_ld_vec(s, t1, s->cpu_env, bofs + i);
+        tcg_gen_ld_vec(s, t0, s->uc->cpu_env, aofs + i);
+        tcg_gen_ld_vec(s, t1, s->uc->cpu_env, bofs + i);
         if (load_dest) {
-            tcg_gen_ld_vec(s, t2, s->cpu_env, dofs + i);
+            tcg_gen_ld_vec(s, t2, s->uc->cpu_env, dofs + i);
         }
         fni(s, vece, t2, t0, t1);
-        tcg_gen_st_vec(s, t2, s->cpu_env, dofs + i);
+        tcg_gen_st_vec(s, t2, s->uc->cpu_env, dofs + i);
     }
     tcg_temp_free_vec(s, t2);
     tcg_temp_free_vec(s, t1);
@@ -850,11 +850,11 @@ static void expand_4_vec(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t a
     uint32_t i;
 
     for (i = 0; i < oprsz; i += tysz) {
-        tcg_gen_ld_vec(s, t1, s->cpu_env, aofs + i);
-        tcg_gen_ld_vec(s, t2, s->cpu_env, bofs + i);
-        tcg_gen_ld_vec(s, t3, s->cpu_env, cofs + i);
+        tcg_gen_ld_vec(s, t1, s->uc->cpu_env, aofs + i);
+        tcg_gen_ld_vec(s, t2, s->uc->cpu_env, bofs + i);
+        tcg_gen_ld_vec(s, t3, s->uc->cpu_env, cofs + i);
         fni(s, vece, t0, t1, t2, t3);
-        tcg_gen_st_vec(s, t0, s->cpu_env, dofs + i);
+        tcg_gen_st_vec(s, t0, s->uc->cpu_env, dofs + i);
     }
     tcg_temp_free_vec(s, t3);
     tcg_temp_free_vec(s, t2);
@@ -1207,20 +1207,20 @@ void tcg_gen_gvec_dup_mem(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t
         TCGv_i32 in = tcg_temp_new_i32(s);
         switch (vece) {
         case MO_8:
-            tcg_gen_ld8u_i32(s, in, s->cpu_env, aofs);
+            tcg_gen_ld8u_i32(s, in, s->uc->cpu_env, aofs);
             break;
         case MO_16:
-            tcg_gen_ld16u_i32(s, in, s->cpu_env, aofs);
+            tcg_gen_ld16u_i32(s, in, s->uc->cpu_env, aofs);
             break;
         case MO_32:
-            tcg_gen_ld_i32(s, in, s->cpu_env, aofs);
+            tcg_gen_ld_i32(s, in, s->uc->cpu_env, aofs);
             break;
         }
         tcg_gen_gvec_dup_i32(s, vece, dofs, oprsz, maxsz, in);
         tcg_temp_free_i32(s, in);
     } else if (vece == MO_64) {
         TCGv_i64 in = tcg_temp_new_i64(s);
-        tcg_gen_ld_i64(s, in, s->cpu_env, aofs);
+        tcg_gen_ld_i64(s, in, s->uc->cpu_env, aofs);
         tcg_gen_gvec_dup_i64(s, MO_64, dofs, oprsz, maxsz, in);
         tcg_temp_free_i64(s, in);
     } else {
@@ -1233,20 +1233,20 @@ void tcg_gen_gvec_dup_mem(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t
         if (TCG_TARGET_HAS_v128) {
             TCGv_vec in = tcg_temp_new_vec(s, TCG_TYPE_V128);
 
-            tcg_gen_ld_vec(s, in, s->cpu_env, aofs);
+            tcg_gen_ld_vec(s, in, s->uc->cpu_env, aofs);
             for (i = 0; i < oprsz; i += 16) {
-                tcg_gen_st_vec(s, in, s->cpu_env, dofs + i);
+                tcg_gen_st_vec(s, in, s->uc->cpu_env, dofs + i);
             }
             tcg_temp_free_vec(s, in);
         } else {
             TCGv_i64 in0 = tcg_temp_new_i64(s);
             TCGv_i64 in1 = tcg_temp_new_i64(s);
 
-            tcg_gen_ld_i64(s, in0, s->cpu_env, aofs);
-            tcg_gen_ld_i64(s, in1, s->cpu_env, aofs + 8);
+            tcg_gen_ld_i64(s, in0, s->uc->cpu_env, aofs);
+            tcg_gen_ld_i64(s, in1, s->uc->cpu_env, aofs + 8);
             for (i = 0; i < oprsz; i += 16) {
-                tcg_gen_st_i64(s, in0, s->cpu_env, dofs + i);
-                tcg_gen_st_i64(s, in1, s->cpu_env, dofs + i + 8);
+                tcg_gen_st_i64(s, in0, s->uc->cpu_env, dofs + i);
+                tcg_gen_st_i64(s, in1, s->uc->cpu_env, dofs + i + 8);
             }
             tcg_temp_free_i64(s, in0);
             tcg_temp_free_i64(s, in1);
@@ -2073,11 +2073,11 @@ static void expand_cmp_i32(TCGContext *s, uint32_t dofs, uint32_t aofs, uint32_t
     uint32_t i;
 
     for (i = 0; i < oprsz; i += 4) {
-        tcg_gen_ld_i32(s, t0, s->cpu_env, aofs + i);
-        tcg_gen_ld_i32(s, t1, s->cpu_env, bofs + i);
+        tcg_gen_ld_i32(s, t0, s->uc->cpu_env, aofs + i);
+        tcg_gen_ld_i32(s, t1, s->uc->cpu_env, bofs + i);
         tcg_gen_setcond_i32(s, cond, t0, t0, t1);
         tcg_gen_neg_i32(s, t0, t0);
-        tcg_gen_st_i32(s, t0, s->cpu_env, dofs + i);
+        tcg_gen_st_i32(s, t0, s->uc->cpu_env, dofs + i);
     }
     tcg_temp_free_i32(s, t1);
     tcg_temp_free_i32(s, t0);
@@ -2091,11 +2091,11 @@ static void expand_cmp_i64(TCGContext *s, uint32_t dofs, uint32_t aofs, uint32_t
     uint32_t i;
 
     for (i = 0; i < oprsz; i += 8) {
-        tcg_gen_ld_i64(s, t0, s->cpu_env, aofs + i);
-        tcg_gen_ld_i64(s, t1, s->cpu_env, bofs + i);
+        tcg_gen_ld_i64(s, t0, s->uc->cpu_env, aofs + i);
+        tcg_gen_ld_i64(s, t1, s->uc->cpu_env, bofs + i);
         tcg_gen_setcond_i64(s, cond, t0, t0, t1);
         tcg_gen_neg_i64(s, t0, t0);
-        tcg_gen_st_i64(s, t0, s->cpu_env, dofs + i);
+        tcg_gen_st_i64(s, t0, s->uc->cpu_env, dofs + i);
     }
     tcg_temp_free_i64(s, t1);
     tcg_temp_free_i64(s, t0);
@@ -2110,10 +2110,10 @@ static void expand_cmp_vec(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t
     uint32_t i;
 
     for (i = 0; i < oprsz; i += tysz) {
-        tcg_gen_ld_vec(s, t0, s->cpu_env, aofs + i);
-        tcg_gen_ld_vec(s, t1, s->cpu_env, bofs + i);
+        tcg_gen_ld_vec(s, t0, s->uc->cpu_env, aofs + i);
+        tcg_gen_ld_vec(s, t1, s->uc->cpu_env, bofs + i);
         tcg_gen_cmp_vec(s, cond, vece, t0, t0, t1);
-        tcg_gen_st_vec(s, t0, s->cpu_env, dofs + i);
+        tcg_gen_st_vec(s, t0, s->uc->cpu_env, dofs + i);
     }
     tcg_temp_free_vec(s, t1);
     tcg_temp_free_vec(s, t0);
diff --git a/qemu/tcg/tcg-op.c b/qemu/tcg/tcg-op.c
index 8f4aa44f..89eacaff 100644
--- a/qemu/tcg/tcg-op.c
+++ b/qemu/tcg/tcg-op.c
@@ -2552,7 +2552,7 @@ void tcg_gen_lookup_and_goto_ptr(TCGContext *s)
 {
     if (TCG_TARGET_HAS_goto_ptr && !qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)) {
         TCGv_ptr ptr = tcg_temp_new_ptr(s);
-        gen_helper_lookup_tb_ptr(s, ptr, s->tcg_env);
+        gen_helper_lookup_tb_ptr(s, ptr, s->uc->cpu_env);
         tcg_gen_op1i(s, INDEX_op_goto_ptr, tcgv_ptr_arg(s, ptr));
         tcg_temp_free_ptr(s, ptr);
     } else {
@@ -2631,7 +2631,7 @@ void check_exit_request(TCGContext *tcg_ctx)
     TCGv_i32 flag;
 
     flag = tcg_temp_new_i32(tcg_ctx);
-    tcg_gen_ld_i32(tcg_ctx, flag, tcg_ctx->cpu_env,
+    tcg_gen_ld_i32(tcg_ctx, flag, tcg_ctx->uc->cpu_env,
             offsetof(CPUState, tcg_exit_req) - ENV_OFFSET);
     tcg_gen_brcondi_i32(tcg_ctx, TCG_COND_NE, flag, 0, tcg_ctx->exitreq_label);
     tcg_temp_free_i32(tcg_ctx, flag);
@@ -2845,11 +2845,11 @@ void tcg_gen_atomic_cmpxchg_i32(TCGContext *s,
 #ifdef CONFIG_SOFTMMU
         {
             TCGv_i32 oi = tcg_const_i32(s, make_memop_idx(memop & ~MO_SIGN, idx));
-            gen(s, retv, s->tcg_env, addr, cmpv, newv, oi);
+            gen(s, retv, s->uc->cpu_env, addr, cmpv, newv, oi);
             tcg_temp_free_i32(s, oi);
         }
 #else
-        gen(s, retv, s->tcg_env, addr, cmpv, newv);
+        gen(s, retv, s->uc->cpu_env, addr, cmpv, newv);
 #endif
 
         if (memop & MO_SIGN) {
@@ -2891,14 +2891,14 @@ void tcg_gen_atomic_cmpxchg_i64(TCGContext *s,
 #ifdef CONFIG_SOFTMMU
         {
             TCGv_i32 oi = tcg_const_i32(s, make_memop_idx(memop, idx));
-            gen(s, retv, s->tcg_env, addr, cmpv, newv, oi);
+            gen(s, retv, s->uc->cpu_env, addr, cmpv, newv, oi);
             tcg_temp_free_i32(s, oi);
         }
 #else
-        gen(s, retv, s->tcg_env, addr, cmpv, newv);
+        gen(s, retv, s->uc->cpu_env, addr, cmpv, newv);
 #endif
 #else
-        gen_helper_exit_atomic(s, s->tcg_env);
+        gen_helper_exit_atomic(s, s->uc->cpu_env);
         /* Produce a result, so that we have a well-formed opcode stream
            with respect to uses of the result in the (dead) code following.  */
         tcg_gen_movi_i64(s, retv, 0);
@@ -2956,11 +2956,11 @@ static void do_atomic_op_i32(TCGContext *s,
 #ifdef CONFIG_SOFTMMU
     {
         TCGv_i32 oi = tcg_const_i32(s, make_memop_idx(memop & ~MO_SIGN, idx));
-        gen(s, ret, s->tcg_env, addr, val, oi);
+        gen(s, ret, s->uc->cpu_env, addr, val, oi);
         tcg_temp_free_i32(s, oi);
     }
 #else
-    gen(s, ret, s->tcg_env, addr, val);
+    gen(s, ret, s->uc->cpu_env, addr, val);
 #endif
 
     if (memop & MO_SIGN) {
@@ -3003,14 +3003,14 @@ static void do_atomic_op_i64(TCGContext *s,
 #ifdef CONFIG_SOFTMMU
         {
             TCGv_i32 oi = tcg_const_i32(s, make_memop_idx(memop & ~MO_SIGN, idx));
-            gen(s, ret, s->tcg_env, addr, val, oi);
+            gen(s, ret, s->uc->cpu_env, addr, val, oi);
             tcg_temp_free_i32(s, oi);
         }
 #else
-        gen(s, ret, s->tcg_env, addr, val);
+        gen(s, ret, s->uc->cpu_env, addr, val);
 #endif
 #else
-        gen_helper_exit_atomic(s, s->tcg_env);
+        gen_helper_exit_atomic(s, s->uc->cpu_env);
         /* Produce a result, so that we have a well-formed opcode stream
            with respect to uses of the result in the (dead) code following.  */
         tcg_gen_movi_i64(s, ret, 0);
diff --git a/qemu/tcg/tcg.c b/qemu/tcg/tcg.c
index 4bd70bac..922d8d15 100644
--- a/qemu/tcg/tcg.c
+++ b/qemu/tcg/tcg.c
@@ -647,6 +647,8 @@ static const TCGHelperInfo all_helpers[] = {
 };
 
 static void process_op_defs(TCGContext *s);
+static TCGTemp *tcg_global_reg_new_internal(TCGContext *s, TCGType type,
+                                            TCGReg reg, const char *name);
 
 void tcg_context_init(struct uc_struct *uc, TCGContext *s)
 {
@@ -655,6 +657,7 @@ void tcg_context_init(struct uc_struct *uc, TCGContext *s)
     TCGArgConstraint *args_ct;
     int *sorted_args;
     GHashTable *helper_table;
+    TCGTemp *ts;
 
     memset(s, 0, sizeof(*s));
     s->nb_globals = 0;
@@ -726,6 +729,10 @@ void tcg_context_init(struct uc_struct *uc, TCGContext *s)
     //uc->tcg_ctxs = g_new(TCGContext *, max_cpus);
     uc->tcg_ctxs = g_new(TCGContext *, 1);
 #endif
+
+    tcg_debug_assert(!tcg_regset_test_reg(s->reserved_regs, TCG_AREG0));
+    ts = tcg_global_reg_new_internal(s, TCG_TYPE_PTR, TCG_AREG0, "env");
+    uc->cpu_env = temp_tcgv_ptr(s, ts);
 }
 
 /*
@@ -905,29 +912,6 @@ void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size)
         = tcg_global_reg_new_internal(s, TCG_TYPE_PTR, reg, "_frame");
 }
 
-TCGv_i32 tcg_global_reg_new_i32(TCGContext *s, TCGReg reg, const char *name)
-{
-    TCGTemp *t;
-
-    if (tcg_regset_test_reg(s->reserved_regs, reg)) {
-        tcg_abort();
-    }
-    t = tcg_global_reg_new_internal(s, TCG_TYPE_I32, reg, name);
-    return temp_tcgv_i32(s, t);
-}
-
-TCGv_i64 tcg_global_reg_new_i64(TCGContext *s, TCGReg reg, const char *name)
-{
-    TCGTemp *t;
-
-    if (tcg_regset_test_reg(s->reserved_regs, reg)) {
-        tcg_abort();
-    }
-
-    t = tcg_global_reg_new_internal(s, TCG_TYPE_I64, reg, name);
-    return temp_tcgv_i64(s, t);
-}
-
 TCGTemp *tcg_global_mem_new_internal(TCGContext *s, TCGType type, TCGv_ptr base,
                                      intptr_t offset, const char *name)
 {
diff --git a/qemu/tcg/tcg.h b/qemu/tcg/tcg.h
index 3949ff07..ef659f93 100644
--- a/qemu/tcg/tcg.h
+++ b/qemu/tcg/tcg.h
@@ -783,7 +783,6 @@ struct TCGContext {
 
     /* Track which vCPU triggers events */
     CPUState *cpu;                      /* *_trans */
-    TCGv_env tcg_env;                   /* *_exec  */
 
     /* These structures are private to tcg-target.inc.c.  */
 #ifdef TCG_TARGET_NEED_LDST_LABELS
@@ -812,7 +811,6 @@ struct TCGContext {
     // Unicorn engine variables
     struct uc_struct *uc;
     /* qemu/target-i386/translate.c: global register indexes */
-    TCGv_env cpu_env;
     TCGv_i32 cpu_cc_op;
     TCGv cpu_regs[16]; // 16 GRP for X86-64
     TCGv cpu_seg_base[6];
@@ -1047,9 +1045,6 @@ static inline bool tcg_op_buf_full(TCGContext *tcg_ctx)
 TCGTemp *tcg_global_mem_new_internal(TCGContext *s, TCGType type, TCGv_ptr base,
                                      intptr_t offset, const char *name);
 
-TCGv_i32 tcg_global_reg_new_i32(TCGContext *s, TCGReg reg, const char *name);
-TCGv_i64 tcg_global_reg_new_i64(TCGContext *s, TCGReg reg, const char *name);
-
 TCGv_i32 tcg_temp_new_internal_i32(TCGContext *s, int temp_local);
 TCGv_i64 tcg_temp_new_internal_i64(TCGContext *s, int temp_local);
 TCGv_vec tcg_temp_new_vec(TCGContext *s, TCGType type);
@@ -1113,8 +1108,6 @@ static inline TCGv_ptr TCGV_NAT_TO_PTR(TCGv_i32 n) { return (TCGv_ptr)n; }
 static inline TCGv_i32 TCGV_PTR_TO_NAT(TCGv_ptr n) { return (TCGv_i32)n; }
 
 #define tcg_const_ptr(t, V) TCGV_NAT_TO_PTR(tcg_const_i32(t, (intptr_t)(V)))
-#define tcg_global_reg_new_ptr(U, R, N) \
-    TCGV_NAT_TO_PTR(tcg_global_reg_new_i32(U, (R), (N)))
 #define tcg_global_mem_new_ptr(t, R, O, N) \
     TCGV_NAT_TO_PTR(tcg_global_mem_new_i32(t, (R), (O), (N)))
 #define tcg_temp_new_ptr(s) TCGV_NAT_TO_PTR(tcg_temp_new_i32(s))
@@ -1124,8 +1117,6 @@ static inline TCGv_ptr TCGV_NAT_TO_PTR(TCGv_i64 n) { return (TCGv_ptr)n; }
 static inline TCGv_i64 TCGV_PTR_TO_NAT(TCGv_ptr n) { return (TCGv_i64)n; }
 
 #define tcg_const_ptr(t, V) TCGV_NAT_TO_PTR(tcg_const_i64(t, (intptr_t)(V)))
-#define tcg_global_reg_new_ptr(U, R, N) \
-    TCGV_NAT_TO_PTR(tcg_global_reg_new_i64(U, (R), (N)))
 #define tcg_global_mem_new_ptr(t, R, O, N) \
     TCGV_NAT_TO_PTR(tcg_global_mem_new_i64(t, (R), (O), (N)))
 #define tcg_temp_new_ptr(s) TCGV_NAT_TO_PTR(tcg_temp_new_i64(s))
diff --git a/qemu/x86_64.h b/qemu/x86_64.h
index 3dda8a95..38060dd8 100644
--- a/qemu/x86_64.h
+++ b/qemu/x86_64.h
@@ -2799,8 +2799,6 @@
 #define tcg_global_mem_new_i32 tcg_global_mem_new_i32_x86_64
 #define tcg_global_mem_new_i64 tcg_global_mem_new_i64_x86_64
 #define tcg_global_mem_new_internal tcg_global_mem_new_internal_x86_64
-#define tcg_global_reg_new_i32 tcg_global_reg_new_i32_x86_64
-#define tcg_global_reg_new_i64 tcg_global_reg_new_i64_x86_64
 #define tcg_global_reg_new_internal tcg_global_reg_new_internal_x86_64
 #define tcg_handle_interrupt tcg_handle_interrupt_x86_64
 #define tcg_init tcg_init_x86_64