From cdcd026413a55738e352eb6adb584747689dc474 Mon Sep 17 00:00:00 2001
From: dmarxn <47157608+dmarxn@users.noreply.github.com>
Date: Thu, 28 Feb 2019 16:27:35 -0500
Subject: [PATCH] target/i386: Added MXCSR register, fixed writing to FPUCW.
 (#1059)

* Added MXCSR register for reading and writing
* Changed writing for fpucw register, now the qemu rounding status is updated as well

Backports commit 256e7782ceafb1f8915da167040d5368c38f9585 from unicorn
---
 include/unicorn/x86.h      |  2 +-
 qemu/target/i386/unicorn.c | 14 +++++++++++++-
 2 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/include/unicorn/x86.h b/include/unicorn/x86.h
index c4a97900..235dac6a 100644
--- a/include/unicorn/x86.h
+++ b/include/unicorn/x86.h
@@ -88,7 +88,7 @@ typedef enum uc_x86_reg {
 	UC_X86_REG_IDTR, UC_X86_REG_GDTR, UC_X86_REG_LDTR, UC_X86_REG_TR, UC_X86_REG_FPCW,
 	UC_X86_REG_FPTAG,
     UC_X86_REG_MSR, // Model-Specific Register
-
+    UC_X86_REG_MXCSR,
     UC_X86_REG_ENDING		// <-- mark the end of the list of registers
 } uc_x86_reg;
 
diff --git a/qemu/target/i386/unicorn.c b/qemu/target/i386/unicorn.c
index 5a3bea9d..14a3a7d8 100644
--- a/qemu/target/i386/unicorn.c
+++ b/qemu/target/i386/unicorn.c
@@ -240,7 +240,7 @@ int x86_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int coun
                 }
                 continue;
             case UC_X86_REG_FPCW:
-                *(uint16_t*) value = state->fpuc;
+                cpu_set_fpuc(&X86_CPU(uc, mycpu)->env, *(uint16_t *)value);
                 continue;
             case UC_X86_REG_FPTAG:
                 {
@@ -472,6 +472,9 @@ int x86_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int coun
                     case UC_X86_REG_MSR:
                         x86_msr_read(uc, (uc_x86_msr *)value);
                         break;
+                    case UC_X86_REG_MXCSR:
+                        *(uint32_t *)value = X86_CPU(uc, mycpu)->env.mxcsr;
+                        break;
                 }
                 break;
 
@@ -754,6 +757,9 @@ int x86_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int coun
                     case UC_X86_REG_MSR:
                         x86_msr_read(uc, (uc_x86_msr *)value);
                         break;
+                    case UC_X86_REG_MXCSR:
+                        *(uint32_t *)value = X86_CPU(uc, mycpu)->env.mxcsr;
+                        break;
                 }
                 break;
 #endif
@@ -1019,6 +1025,9 @@ int x86_reg_write(struct uc_struct *uc, unsigned int *regs, void *const *vals, i
                     case UC_X86_REG_MSR:
                         x86_msr_write(uc, (uc_x86_msr *)value);
                         break;
+                    case UC_X86_REG_MXCSR:
+                        cpu_set_mxcsr(&X86_CPU(uc, mycpu)->env, *(uint32_t *)value);
+                        break;
                 }
                 break;
 
@@ -1311,6 +1320,9 @@ int x86_reg_write(struct uc_struct *uc, unsigned int *regs, void *const *vals, i
                     case UC_X86_REG_MSR:
                         x86_msr_write(uc, (uc_x86_msr *)value);
                         break;
+                    case UC_X86_REG_MXCSR:
+                        cpu_set_mxcsr(&X86_CPU(uc, mycpu)->env, *(uint32_t *)value);
+                        break;
                 }
                 break;
 #endif