From d1e4ac045154fa34c5cb43971de2bccb1c09c1be Mon Sep 17 00:00:00 2001 From: Sergey Sorokin Date: Sun, 25 Feb 2018 03:52:50 -0500 Subject: [PATCH] Fix confusing argument names in some common functions There are functions tlb_fill(), cpu_unaligned_access() and do_unaligned_access() that are called with access type and mmu index arguments. But these arguments are named 'is_write' and 'is_user' in their declarations. The patches fix the arguments to avoid a confusion. Backports commit b35399bb4e9968296a12303b00f9f2066470e987 from qemu --- qemu/include/exec/cpu-common.h | 6 ------ qemu/include/exec/exec-all.h | 4 ++-- qemu/include/qom/cpu.h | 15 +++++++++++---- qemu/target-arm/internals.h | 5 +++-- qemu/target-arm/op_helper.c | 30 +++++++++++++++++------------- qemu/target-i386/mem_helper.c | 6 +++--- qemu/target-m68k/op_helper.c | 6 +++--- qemu/target-mips/cpu.h | 3 ++- qemu/target-mips/op_helper.c | 10 +++++----- qemu/target-sparc/cpu.h | 7 ++++--- qemu/target-sparc/ldst_helper.c | 13 +++++++------ 11 files changed, 57 insertions(+), 48 deletions(-) diff --git a/qemu/include/exec/cpu-common.h b/qemu/include/exec/cpu-common.h index 449aebe1..c6628077 100644 --- a/qemu/include/exec/cpu-common.h +++ b/qemu/include/exec/cpu-common.h @@ -14,12 +14,6 @@ struct uc_struct; #include "qemu/fprintf-fn.h" #include "qemu/typedefs.h" -typedef enum MMUAccessType { - MMU_DATA_LOAD = 0, - MMU_DATA_STORE = 1, - MMU_INST_FETCH = 2 -} MMUAccessType; - #if !defined(CONFIG_USER_ONLY) enum device_endian { diff --git a/qemu/include/exec/exec-all.h b/qemu/include/exec/exec-all.h index 9ed54958..f04492c0 100644 --- a/qemu/include/exec/exec-all.h +++ b/qemu/include/exec/exec-all.h @@ -371,8 +371,8 @@ void phys_mem_set_alloc(void *(*alloc)(size_t, uint64_t *align)); struct MemoryRegion *iotlb_to_region(CPUState *cpu, hwaddr index, MemTxAttrs attrs); -void tlb_fill(CPUState *cpu, target_ulong addr, int is_write, int mmu_idx, - uintptr_t retaddr); +void tlb_fill(CPUState *cpu, target_ulong addr, MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr); #endif #if defined(CONFIG_USER_ONLY) diff --git a/qemu/include/qom/cpu.h b/qemu/include/qom/cpu.h index f908f81e..a099b8fd 100644 --- a/qemu/include/qom/cpu.h +++ b/qemu/include/qom/cpu.h @@ -60,6 +60,12 @@ typedef uint64_t vaddr; #define CPU_CLASS(uc, class) OBJECT_CLASS_CHECK(uc, CPUClass, (class), TYPE_CPU) #define CPU_GET_CLASS(uc, obj) OBJECT_GET_CLASS(uc, CPUClass, (obj), TYPE_CPU) +typedef enum MMUAccessType { + MMU_DATA_LOAD = 0, + MMU_DATA_STORE = 1, + MMU_INST_FETCH = 2 +} MMUAccessType; + typedef struct CPUWatchpoint CPUWatchpoint; typedef void (*CPUUnassignedAccess)(CPUState *cpu, hwaddr addr, @@ -121,7 +127,8 @@ typedef struct CPUClass { void (*do_interrupt)(CPUState *cpu); CPUUnassignedAccess do_unassigned_access; void (*do_unaligned_access)(CPUState *cpu, vaddr addr, - int is_write, int is_user, uintptr_t retaddr); + MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr); int (*memory_rw_debug)(CPUState *cpu, vaddr addr, uint8_t *buf, int len, bool is_write); void (*dump_state)(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, @@ -607,12 +614,12 @@ static inline void cpu_unassigned_access(CPUState *cpu, hwaddr addr, } static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr, - int is_write, int is_user, - uintptr_t retaddr) + MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr) { CPUClass *cc = CPU_GET_CLASS(cpu->uc, cpu); - cc->do_unaligned_access(cpu, addr, is_write, is_user, retaddr); + cc->do_unaligned_access(cpu, addr, access_type, mmu_idx, retaddr); } #endif diff --git a/qemu/target-arm/internals.h b/qemu/target-arm/internals.h index 9c18a3ba..395e40b3 100644 --- a/qemu/target-arm/internals.h +++ b/qemu/target-arm/internals.h @@ -479,8 +479,9 @@ bool arm_tlb_fill(CPUState *cpu, vaddr address, int rw, int mmu_idx, bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx); /* Raise a data fault alignment exception for the specified virtual address */ -void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, int is_write, - int is_user, uintptr_t retaddr); +void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, + MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr); /* Call the EL change hook if one has been registered */ static inline void arm_call_el_change_hook(ARMCPU *cpu) diff --git a/qemu/target-arm/op_helper.c b/qemu/target-arm/op_helper.c index 0ccaf0fb..8d032cbb 100644 --- a/qemu/target-arm/op_helper.c +++ b/qemu/target-arm/op_helper.c @@ -79,7 +79,7 @@ uint32_t HELPER(neon_tbl)(CPUARMState *env, uint32_t ireg, uint32_t def, static inline uint32_t merge_syn_data_abort(uint32_t template_syn, unsigned int target_el, bool same_el, - bool s1ptw, int is_write, + bool s1ptw, bool is_write, int fsc) { uint32_t syn; @@ -97,7 +97,7 @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn, */ if (!(template_syn & ARM_EL_ISV) || target_el != 2 || s1ptw) { syn = syn_data_abort_no_iss(same_el, - 0, 0, s1ptw, is_write == 1, fsc); + 0, 0, s1ptw, is_write, fsc); } else { /* Fields: IL, ISV, SAS, SSE, SRT, SF and AR come from the template * syndrome created at translation time. @@ -105,7 +105,7 @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn, */ syn = syn_data_abort_with_iss(same_el, 0, 0, 0, 0, 0, - 0, 0, s1ptw, is_write == 1, fsc, + 0, 0, s1ptw, is_write, fsc, false); /* Merge the runtime syndrome with the template syndrome. */ syn |= template_syn; @@ -117,14 +117,14 @@ static inline uint32_t merge_syn_data_abort(uint32_t template_syn, * NULL, it means that the function was called in C code (i.e. not * from generated code or from helper.c) */ -void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, - uintptr_t retaddr) +void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr) { bool ret; uint32_t fsr = 0; ARMMMUFaultInfo fi = {0}; - ret = arm_tlb_fill(cs, addr, is_write, mmu_idx, &fsr, &fi); + ret = arm_tlb_fill(cs, addr, access_type, mmu_idx, &fsr, &fi); if (unlikely(ret)) { ARMCPU *cpu = ARM_CPU(cs->uc, cs); CPUARMState *env = &cpu->env; @@ -149,13 +149,15 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, /* For insn and data aborts we assume there is no instruction syndrome * information; this is always true for exceptions reported to EL1. */ - if (is_write == 2) { + if (access_type == MMU_INST_FETCH) { syn = syn_insn_abort(same_el, 0, fi.s1ptw, syn); exc = EXCP_PREFETCH_ABORT; } else { syn = merge_syn_data_abort(env->exception.syndrome, target_el, - same_el, fi.s1ptw, is_write, syn); - if (is_write == 1 && arm_feature(env, ARM_FEATURE_V6)) { + same_el, fi.s1ptw, + access_type == MMU_DATA_STORE, syn); + if (access_type == MMU_DATA_STORE + && arm_feature(env, ARM_FEATURE_V6)) { fsr |= (1 << 11); } exc = EXCP_DATA_ABORT; @@ -168,8 +170,9 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, } /* Raise a data fault alignment exception for the specified virtual address */ -void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, int is_write, - int is_user, uintptr_t retaddr) +void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, + MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr) { ARMCPU *cpu = ARM_CPU(cs->uc, cs); CPUARMState *env = &cpu->env; @@ -196,12 +199,13 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, int is_write, env->exception.fsr = 0x1; } - if (is_write == 1 && arm_feature(env, ARM_FEATURE_V6)) { + if (access_type == MMU_DATA_STORE && arm_feature(env, ARM_FEATURE_V6)) { env->exception.fsr |= (1 << 11); } syn = merge_syn_data_abort(env->exception.syndrome, target_el, - same_el, 0, is_write, 0x21); + same_el, 0, access_type == MMU_DATA_STORE, + 0x21); raise_exception(env, EXCP_DATA_ABORT, syn, target_el); } diff --git a/qemu/target-i386/mem_helper.c b/qemu/target-i386/mem_helper.c index 22878f33..5b215014 100644 --- a/qemu/target-i386/mem_helper.c +++ b/qemu/target-i386/mem_helper.c @@ -119,12 +119,12 @@ void helper_boundl(CPUX86State *env, target_ulong a0, int v) * from generated code or from helper.c) */ /* XXX: fix it to restore all registers */ -void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, - uintptr_t retaddr) +void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr) { int ret; - ret = x86_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); + ret = x86_cpu_handle_mmu_fault(cs, addr, access_type, mmu_idx); if (ret) { X86CPU *cpu = X86_CPU(cs->uc, cs); CPUX86State *env = &cpu->env; diff --git a/qemu/target-m68k/op_helper.c b/qemu/target-m68k/op_helper.c index 35e7e69b..b577ffc2 100644 --- a/qemu/target-m68k/op_helper.c +++ b/qemu/target-m68k/op_helper.c @@ -40,12 +40,12 @@ extern int semihosting_enabled; /* Try to fill the TLB and return an exception if error. If retaddr is NULL, it means that the function was called in C code (i.e. not from generated code or from helper.c) */ -void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, - uintptr_t retaddr) +void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr) { int ret; - ret = m68k_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); + ret = m68k_cpu_handle_mmu_fault(cs, addr, access_type, mmu_idx); if (unlikely(ret)) { if (retaddr) { /* now we have a real cpu fault */ diff --git a/qemu/target-mips/cpu.h b/qemu/target-mips/cpu.h index b79c88e7..757e3dd3 100644 --- a/qemu/target-mips/cpu.h +++ b/qemu/target-mips/cpu.h @@ -647,7 +647,8 @@ void mips_cpu_do_interrupt(CPUState *cpu); bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req); hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, - int is_write, int is_user, uintptr_t retaddr); + MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr); #if !defined(CONFIG_USER_ONLY) int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, diff --git a/qemu/target-mips/op_helper.c b/qemu/target-mips/op_helper.c index 0d00b39c..6376c644 100644 --- a/qemu/target-mips/op_helper.c +++ b/qemu/target-mips/op_helper.c @@ -2373,8 +2373,8 @@ void helper_wait(CPUMIPSState *env) #if !defined(CONFIG_USER_ONLY) void mips_cpu_do_unaligned_access(CPUState *cs, vaddr addr, - int access_type, int is_user, - uintptr_t retaddr) + MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr) { MIPSCPU *cpu = MIPS_CPU(cs->uc, cs); CPUMIPSState *env = &cpu->env; @@ -2395,12 +2395,12 @@ void mips_cpu_do_unaligned_access(CPUState *cs, vaddr addr, do_raise_exception_err(env, excp, error_code, retaddr); } -void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, - uintptr_t retaddr) +void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr) { int ret; - ret = mips_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); + ret = mips_cpu_handle_mmu_fault(cs, addr, access_type, mmu_idx); if (ret) { MIPSCPU *cpu = MIPS_CPU(cs->uc, cs); CPUMIPSState *env = &cpu->env; diff --git a/qemu/target-sparc/cpu.h b/qemu/target-sparc/cpu.h index dbe99d2c..1a2620b8 100644 --- a/qemu/target-sparc/cpu.h +++ b/qemu/target-sparc/cpu.h @@ -536,9 +536,10 @@ void sparc_cpu_do_interrupt(CPUState *cpu); void sparc_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, int flags); hwaddr sparc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); -void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cpu, - vaddr addr, int is_write, - int is_user, uintptr_t retaddr); +void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, + MMUAccessType access_type, + int mmu_idx, + uintptr_t retaddr); #ifndef NO_CPU_IO_DEFS /* cpu_init.c */ diff --git a/qemu/target-sparc/ldst_helper.c b/qemu/target-sparc/ldst_helper.c index d2272778..acecb2ac 100644 --- a/qemu/target-sparc/ldst_helper.c +++ b/qemu/target-sparc/ldst_helper.c @@ -2425,9 +2425,10 @@ void sparc_cpu_unassigned_access(CPUState *cs, hwaddr addr, #endif #if !defined(CONFIG_USER_ONLY) -void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cs, - vaddr addr, int is_write, - int is_user, uintptr_t retaddr) +void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cs, vaddr addr, + MMUAccessType access_type, + int mmu_idx, + uintptr_t retaddr) { SPARCCPU *cpu = SPARC_CPU(cs->uc, cs); CPUSPARCState *env = &cpu->env; @@ -2446,12 +2447,12 @@ void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cs, NULL, it means that the function was called in C code (i.e. not from generated code or from helper.c) */ /* XXX: fix it to restore all registers */ -void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, - uintptr_t retaddr) +void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr) { int ret; - ret = sparc_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); + ret = sparc_cpu_handle_mmu_fault(cs, addr, access_type, mmu_idx); if (ret) { if (retaddr) { cpu_restore_state(cs, retaddr);