From d3e5003e53a5a569230b2a4d438a046fb21ca22f Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Mon, 19 Feb 2018 01:11:38 -0500 Subject: [PATCH] target-arm: Make various system registers visible to EL3 The AArch64 system registers DACR32_EL2, IFSR32_EL2, SPSR_IRQ, SPSR_ABT, SPSR_UND and SPSR_FIQ are visible and fully functional from EL3 even if the CPU has no EL2 (unlike some others which are RES0 from EL3 in that configuration). Move them from el2_cp_reginfo[] to v8_cp_reginfo[] so they are always present. Backports commit 6a43e0b6e1f6bcd6b11656967422f4217258200a from qemu --- qemu/target-arm/helper.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/qemu/target-arm/helper.c b/qemu/target-arm/helper.c index 5fb000fb..4704af8f 100644 --- a/qemu/target-arm/helper.c +++ b/qemu/target-arm/helper.c @@ -2817,6 +2817,19 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { { "FPEXC32_EL2", 0,5,3, 3,4,0, ARM_CP_STATE_AA64, ARM_CP_ALIAS, PL2_RW, 0, NULL, 0, offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]), {0, 0}, fpexc32_access }, + { "DACR32_EL2", 0,3,0, 3,4,0, ARM_CP_STATE_AA64,0, + PL2_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.dacr32_el2), {0, 0}, + NULL, NULL, dacr_write, NULL, raw_write }, + { "IFSR32_EL2", 0,5,0, 3,4,1, ARM_CP_STATE_AA64,0, + PL2_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.ifsr32_el2) }, + { "SPSR_IRQ", 0,4,3, 3,4,0, ARM_CP_STATE_AA64, ARM_CP_ALIAS, + PL2_RW, 0, NULL, 0, offsetof(CPUARMState, banked_spsr[BANK_IRQ]) }, + { "SPSR_ABT", 0,4,3, 3,4,1, ARM_CP_STATE_AA64, ARM_CP_ALIAS, + PL2_RW, 0, NULL, 0, offsetof(CPUARMState, banked_spsr[BANK_ABT]) }, + { "SPSR_UND", 0,4,3, 3,4,2, ARM_CP_STATE_AA64, ARM_CP_ALIAS, + PL2_RW, 0, NULL, 0, offsetof(CPUARMState, banked_spsr[BANK_UND]) }, + { "SPSR_FIQ", 0,4,3, 3,4,3, ARM_CP_STATE_AA64, ARM_CP_ALIAS, + PL2_RW, 0, NULL, 0, offsetof(CPUARMState, banked_spsr[BANK_FIQ]) }, REGINFO_SENTINEL }; @@ -2911,27 +2924,14 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { { "HCR_EL2", 0,1,1, 3,4,0, ARM_CP_STATE_AA64, 0, PL2_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.hcr_el2), {0, 0}, NULL, NULL, hcr_write }, - { "DACR32_EL2", 0,3,0, 3,4,0, ARM_CP_STATE_AA64,0, - PL2_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.dacr32_el2), {0, 0}, - NULL, NULL, dacr_write, NULL, raw_write }, { "ELR_EL2", 0,4,0, 3,4,1, ARM_CP_STATE_AA64, ARM_CP_ALIAS, PL2_RW, 0, NULL, 0, offsetof(CPUARMState, elr_el[2]) }, { "ESR_EL2", 0,5,2, 3,4,0, ARM_CP_STATE_AA64, ARM_CP_ALIAS, PL2_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.esr_el[2]) }, - { "IFSR32_EL2", 0,5,0, 3,4,1, ARM_CP_STATE_AA64,0, - PL2_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.ifsr32_el2) }, { "FAR_EL2", 0,6,0, 3,4,0, ARM_CP_STATE_AA64, 0, PL2_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.far_el[2]) }, { "SPSR_EL2", 0,4,0, 3,4,0, ARM_CP_STATE_AA64, ARM_CP_ALIAS, PL2_RW, 0, NULL, 0, offsetof(CPUARMState, banked_spsr[BANK_HYP]) }, - { "SPSR_IRQ", 0,4,3, 3,4,0, ARM_CP_STATE_AA64, ARM_CP_ALIAS, - PL2_RW, 0, NULL, 0, offsetof(CPUARMState, banked_spsr[BANK_IRQ]) }, - { "SPSR_ABT", 0,4,3, 3,4,1, ARM_CP_STATE_AA64, ARM_CP_ALIAS, - PL2_RW, 0, NULL, 0, offsetof(CPUARMState, banked_spsr[BANK_ABT]) }, - { "SPSR_UND", 0,4,3, 3,4,2, ARM_CP_STATE_AA64, ARM_CP_ALIAS, - PL2_RW, 0, NULL, 0, offsetof(CPUARMState, banked_spsr[BANK_UND]) }, - { "SPSR_FIQ", 0,4,3, 3,4,3, ARM_CP_STATE_AA64, ARM_CP_ALIAS, - PL2_RW, 0, NULL, 0, offsetof(CPUARMState, banked_spsr[BANK_FIQ]) }, { "VBAR_EL2", 0,12,0, 3,4,0, ARM_CP_STATE_AA64, 0, PL2_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.vbar_el[2]), {0, 0}, NULL, NULL, vbar_write, },