From d4c59cce4e2e3494f6e32e4a2667f93c79205da2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Fri, 26 Feb 2021 12:18:06 -0500 Subject: [PATCH] target/arm: Clarify HCR_EL2 ARMCPRegInfo type In commit ce4afed839 ("target/arm: Implement AArch32 HCR and HCR2") the HCR_EL2 register has been changed from type NO_RAW (no underlying state and does not support raw access for state saving/loading) to type CONST (TCG can assume the value to be constant), removing the read/write accessors. We forgot to remove the previous type ARM_CP_NO_RAW. This is not really a problem since the field is overwritten. However it makes code review confuse, so remove it. Backports 0e5aac18bc31dbdfab51f9784240d0c31a4c5579 --- qemu/target/arm/helper.c | 1 - 1 file changed, 1 deletion(-) diff --git a/qemu/target/arm/helper.c b/qemu/target/arm/helper.c index a594650e..4b532766 100644 --- a/qemu/target/arm/helper.c +++ b/qemu/target/arm/helper.c @@ -4814,7 +4814,6 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = { .access = PL2_RW, .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore }, { .name = "HCR_EL2", .state = ARM_CP_STATE_BOTH, - .type = ARM_CP_NO_RAW, .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },