diff --git a/qemu/aarch64.h b/qemu/aarch64.h index dc4a25c9..57723e02 100644 --- a/qemu/aarch64.h +++ b/qemu/aarch64.h @@ -167,6 +167,7 @@ #define arm_gen_test_cc arm_gen_test_cc_aarch64 #define arm_generate_debug_exceptions arm_generate_debug_exceptions_aarch64 #define arm_gt_htimer_cb arm_gt_htimer_cb_aarch64 +#define arm_gt_hvtimer_cb arm_gt_hvtimer_cb_aarch64 #define arm_gt_ptimer_cb arm_gt_ptimer_cb_aarch64 #define arm_gt_stimer_cb arm_gt_stimer_cb_aarch64 #define arm_gt_vtimer_cb arm_gt_vtimer_cb_aarch64 diff --git a/qemu/aarch64eb.h b/qemu/aarch64eb.h index 3533f3c7..8ef416c6 100644 --- a/qemu/aarch64eb.h +++ b/qemu/aarch64eb.h @@ -167,6 +167,7 @@ #define arm_gen_test_cc arm_gen_test_cc_aarch64eb #define arm_generate_debug_exceptions arm_generate_debug_exceptions_aarch64eb #define arm_gt_htimer_cb arm_gt_htimer_cb_aarch64eb +#define arm_gt_hvtimer_cb arm_gt_hvtimer_cb_aarch64eb #define arm_gt_ptimer_cb arm_gt_ptimer_cb_aarch64eb #define arm_gt_stimer_cb arm_gt_stimer_cb_aarch64eb #define arm_gt_vtimer_cb arm_gt_vtimer_cb_aarch64eb diff --git a/qemu/arm.h b/qemu/arm.h index 1f835a65..a0b1b601 100644 --- a/qemu/arm.h +++ b/qemu/arm.h @@ -167,6 +167,7 @@ #define arm_gen_test_cc arm_gen_test_cc_arm #define arm_generate_debug_exceptions arm_generate_debug_exceptions_arm #define arm_gt_htimer_cb arm_gt_htimer_cb_arm +#define arm_gt_hvtimer_cb arm_gt_hvtimer_cb_arm #define arm_gt_ptimer_cb arm_gt_ptimer_cb_arm #define arm_gt_stimer_cb arm_gt_stimer_cb_arm #define arm_gt_vtimer_cb arm_gt_vtimer_cb_arm diff --git a/qemu/armeb.h b/qemu/armeb.h index 3aef3b58..9f6fd99c 100644 --- a/qemu/armeb.h +++ b/qemu/armeb.h @@ -167,6 +167,7 @@ #define arm_gen_test_cc arm_gen_test_cc_armeb #define arm_generate_debug_exceptions arm_generate_debug_exceptions_armeb #define arm_gt_htimer_cb arm_gt_htimer_cb_armeb +#define arm_gt_hvtimer_cb arm_gt_hvtimer_cb_armeb #define arm_gt_ptimer_cb arm_gt_ptimer_cb_armeb #define arm_gt_stimer_cb arm_gt_stimer_cb_armeb #define arm_gt_vtimer_cb arm_gt_vtimer_cb_armeb diff --git a/qemu/header_gen.py b/qemu/header_gen.py index b08ca35c..56f06b7d 100644 --- a/qemu/header_gen.py +++ b/qemu/header_gen.py @@ -173,6 +173,7 @@ symbols = ( 'arm_gen_test_cc', 'arm_generate_debug_exceptions', 'arm_gt_htimer_cb', + 'arm_gt_hvtimer_cb', 'arm_gt_ptimer_cb', 'arm_gt_stimer_cb', 'arm_gt_vtimer_cb', diff --git a/qemu/m68k.h b/qemu/m68k.h index 27dc87f4..abcc5284 100644 --- a/qemu/m68k.h +++ b/qemu/m68k.h @@ -167,6 +167,7 @@ #define arm_gen_test_cc arm_gen_test_cc_m68k #define arm_generate_debug_exceptions arm_generate_debug_exceptions_m68k #define arm_gt_htimer_cb arm_gt_htimer_cb_m68k +#define arm_gt_hvtimer_cb arm_gt_hvtimer_cb_m68k #define arm_gt_ptimer_cb arm_gt_ptimer_cb_m68k #define arm_gt_stimer_cb arm_gt_stimer_cb_m68k #define arm_gt_vtimer_cb arm_gt_vtimer_cb_m68k diff --git a/qemu/mips.h b/qemu/mips.h index b3ce9823..12eac6d1 100644 --- a/qemu/mips.h +++ b/qemu/mips.h @@ -167,6 +167,7 @@ #define arm_gen_test_cc arm_gen_test_cc_mips #define arm_generate_debug_exceptions arm_generate_debug_exceptions_mips #define arm_gt_htimer_cb arm_gt_htimer_cb_mips +#define arm_gt_hvtimer_cb arm_gt_hvtimer_cb_mips #define arm_gt_ptimer_cb arm_gt_ptimer_cb_mips #define arm_gt_stimer_cb arm_gt_stimer_cb_mips #define arm_gt_vtimer_cb arm_gt_vtimer_cb_mips diff --git a/qemu/mips64.h b/qemu/mips64.h index a0cea283..dd3f4a0d 100644 --- a/qemu/mips64.h +++ b/qemu/mips64.h @@ -167,6 +167,7 @@ #define arm_gen_test_cc arm_gen_test_cc_mips64 #define arm_generate_debug_exceptions arm_generate_debug_exceptions_mips64 #define arm_gt_htimer_cb arm_gt_htimer_cb_mips64 +#define arm_gt_hvtimer_cb arm_gt_hvtimer_cb_mips64 #define arm_gt_ptimer_cb arm_gt_ptimer_cb_mips64 #define arm_gt_stimer_cb arm_gt_stimer_cb_mips64 #define arm_gt_vtimer_cb arm_gt_vtimer_cb_mips64 diff --git a/qemu/mips64el.h b/qemu/mips64el.h index f8cd21be..cb0b61e4 100644 --- a/qemu/mips64el.h +++ b/qemu/mips64el.h @@ -167,6 +167,7 @@ #define arm_gen_test_cc arm_gen_test_cc_mips64el #define arm_generate_debug_exceptions arm_generate_debug_exceptions_mips64el #define arm_gt_htimer_cb arm_gt_htimer_cb_mips64el +#define arm_gt_hvtimer_cb arm_gt_hvtimer_cb_mips64el #define arm_gt_ptimer_cb arm_gt_ptimer_cb_mips64el #define arm_gt_stimer_cb arm_gt_stimer_cb_mips64el #define arm_gt_vtimer_cb arm_gt_vtimer_cb_mips64el diff --git a/qemu/mipsel.h b/qemu/mipsel.h index c0fb63c4..0fd78f82 100644 --- a/qemu/mipsel.h +++ b/qemu/mipsel.h @@ -167,6 +167,7 @@ #define arm_gen_test_cc arm_gen_test_cc_mipsel #define arm_generate_debug_exceptions arm_generate_debug_exceptions_mipsel #define arm_gt_htimer_cb arm_gt_htimer_cb_mipsel +#define arm_gt_hvtimer_cb arm_gt_hvtimer_cb_mipsel #define arm_gt_ptimer_cb arm_gt_ptimer_cb_mipsel #define arm_gt_stimer_cb arm_gt_stimer_cb_mipsel #define arm_gt_vtimer_cb arm_gt_vtimer_cb_mipsel diff --git a/qemu/powerpc.h b/qemu/powerpc.h index ffde9000..46710795 100644 --- a/qemu/powerpc.h +++ b/qemu/powerpc.h @@ -167,6 +167,7 @@ #define arm_gen_test_cc arm_gen_test_cc_powerpc #define arm_generate_debug_exceptions arm_generate_debug_exceptions_powerpc #define arm_gt_htimer_cb arm_gt_htimer_cb_powerpc +#define arm_gt_hvtimer_cb arm_gt_hvtimer_cb_powerpc #define arm_gt_ptimer_cb arm_gt_ptimer_cb_powerpc #define arm_gt_stimer_cb arm_gt_stimer_cb_powerpc #define arm_gt_vtimer_cb arm_gt_vtimer_cb_powerpc diff --git a/qemu/riscv32.h b/qemu/riscv32.h index 0fa3fd41..471f6ae0 100644 --- a/qemu/riscv32.h +++ b/qemu/riscv32.h @@ -167,6 +167,7 @@ #define arm_gen_test_cc arm_gen_test_cc_riscv32 #define arm_generate_debug_exceptions arm_generate_debug_exceptions_riscv32 #define arm_gt_htimer_cb arm_gt_htimer_cb_riscv32 +#define arm_gt_hvtimer_cb arm_gt_hvtimer_cb_riscv32 #define arm_gt_ptimer_cb arm_gt_ptimer_cb_riscv32 #define arm_gt_stimer_cb arm_gt_stimer_cb_riscv32 #define arm_gt_vtimer_cb arm_gt_vtimer_cb_riscv32 diff --git a/qemu/riscv64.h b/qemu/riscv64.h index 45377cfb..e5cbf60d 100644 --- a/qemu/riscv64.h +++ b/qemu/riscv64.h @@ -167,6 +167,7 @@ #define arm_gen_test_cc arm_gen_test_cc_riscv64 #define arm_generate_debug_exceptions arm_generate_debug_exceptions_riscv64 #define arm_gt_htimer_cb arm_gt_htimer_cb_riscv64 +#define arm_gt_hvtimer_cb arm_gt_hvtimer_cb_riscv64 #define arm_gt_ptimer_cb arm_gt_ptimer_cb_riscv64 #define arm_gt_stimer_cb arm_gt_stimer_cb_riscv64 #define arm_gt_vtimer_cb arm_gt_vtimer_cb_riscv64 diff --git a/qemu/sparc.h b/qemu/sparc.h index 3d210f1e..a2206255 100644 --- a/qemu/sparc.h +++ b/qemu/sparc.h @@ -167,6 +167,7 @@ #define arm_gen_test_cc arm_gen_test_cc_sparc #define arm_generate_debug_exceptions arm_generate_debug_exceptions_sparc #define arm_gt_htimer_cb arm_gt_htimer_cb_sparc +#define arm_gt_hvtimer_cb arm_gt_hvtimer_cb_sparc #define arm_gt_ptimer_cb arm_gt_ptimer_cb_sparc #define arm_gt_stimer_cb arm_gt_stimer_cb_sparc #define arm_gt_vtimer_cb arm_gt_vtimer_cb_sparc diff --git a/qemu/sparc64.h b/qemu/sparc64.h index ea54d204..3ded3c10 100644 --- a/qemu/sparc64.h +++ b/qemu/sparc64.h @@ -167,6 +167,7 @@ #define arm_gen_test_cc arm_gen_test_cc_sparc64 #define arm_generate_debug_exceptions arm_generate_debug_exceptions_sparc64 #define arm_gt_htimer_cb arm_gt_htimer_cb_sparc64 +#define arm_gt_hvtimer_cb arm_gt_hvtimer_cb_sparc64 #define arm_gt_ptimer_cb arm_gt_ptimer_cb_sparc64 #define arm_gt_stimer_cb arm_gt_stimer_cb_sparc64 #define arm_gt_vtimer_cb arm_gt_vtimer_cb_sparc64 diff --git a/qemu/target/arm/cpu-qom.h b/qemu/target/arm/cpu-qom.h index b0865c9f..9b3025e7 100644 --- a/qemu/target/arm/cpu-qom.h +++ b/qemu/target/arm/cpu-qom.h @@ -70,6 +70,7 @@ void arm_gt_ptimer_cb(void *opaque); void arm_gt_vtimer_cb(void *opaque); void arm_gt_htimer_cb(void *opaque); void arm_gt_stimer_cb(void *opaque); +void arm_gt_hvtimer_cb(void *opaque); #define ARM_AFF0_SHIFT 0 #define ARM_AFF0_MASK (0xFFULL << ARM_AFF0_SHIFT) diff --git a/qemu/target/arm/cpu.h b/qemu/target/arm/cpu.h index 08b1e145..98ff1dc5 100644 --- a/qemu/target/arm/cpu.h +++ b/qemu/target/arm/cpu.h @@ -134,11 +134,12 @@ typedef struct ARMGenericTimer { uint64_t ctl; /* Timer Control register */ } ARMGenericTimer; -#define GTIMER_PHYS 0 -#define GTIMER_VIRT 1 -#define GTIMER_HYP 2 -#define GTIMER_SEC 3 -#define NUM_GTIMERS 4 +#define GTIMER_PHYS 0 +#define GTIMER_VIRT 1 +#define GTIMER_HYP 2 +#define GTIMER_SEC 3 +#define GTIMER_HYPVIRT 4 +#define NUM_GTIMERS 5 typedef struct { uint64_t raw_tcr; diff --git a/qemu/target/arm/helper.c b/qemu/target/arm/helper.c index dcf92f26..d310a609 100644 --- a/qemu/target/arm/helper.c +++ b/qemu/target/arm/helper.c @@ -2336,6 +2336,7 @@ static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri, switch (timeridx) { case GTIMER_VIRT: + case GTIMER_HYPVIRT: offset = gt_virt_cnt_offset(env); break; } @@ -2352,6 +2353,7 @@ static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, switch (timeridx) { case GTIMER_VIRT: + case GTIMER_HYPVIRT: offset = gt_virt_cnt_offset(env); break; } @@ -2512,6 +2514,34 @@ static void gt_sec_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, gt_ctl_write(env, ri, GTIMER_SEC, value); } +static void gt_hv_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) +{ + gt_timer_reset(env, ri, GTIMER_HYPVIRT); +} + +static void gt_hv_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + gt_cval_write(env, ri, GTIMER_HYPVIRT, value); +} + +static uint64_t gt_hv_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return gt_tval_read(env, ri, GTIMER_HYPVIRT); +} + +static void gt_hv_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + gt_tval_write(env, ri, GTIMER_HYPVIRT, value); +} + +static void gt_hv_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + gt_ctl_write(env, ri, GTIMER_HYPVIRT, value); +} + void arm_gt_ptimer_cb(void *opaque) { ARMCPU *cpu = opaque; @@ -2540,6 +2570,13 @@ void arm_gt_stimer_cb(void *opaque) gt_recalc_timer(cpu, GTIMER_SEC); } +void arm_gt_hvtimer_cb(void *opaque) +{ + ARMCPU *cpu = opaque; + + gt_recalc_timer(cpu, GTIMER_HYPVIRT); +} + static const ARMCPRegInfo generic_timer_cp_reginfo[] = { /* Note that CNTFRQ is purely reads-as-written for the benefit * of software; writing it doesn't actually change the timer frequency. @@ -5950,6 +5987,25 @@ static const ARMCPRegInfo vhe_reginfo[] = { .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 1, .access = PL2_RW, .writefn = vmsa_tcr_ttbr_el2_write, .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el[2]) }, +#ifndef CONFIG_USER_ONLY + { .name = "CNTHV_CVAL_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 3, .opc2 = 2, + .fieldoffset = + offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYPVIRT].cval), + .type = ARM_CP_IO, .access = PL2_RW, + .writefn = gt_hv_cval_write, .raw_writefn = raw_write }, + { .name = "CNTHV_TVAL_EL2", .state = ARM_CP_STATE_BOTH, + .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 3, .opc2 = 0, + .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL2_RW, + .resetfn = gt_hv_timer_reset, + .readfn = gt_hv_tval_read, .writefn = gt_hv_tval_write }, + { .name = "CNTHV_CTL_EL2", .state = ARM_CP_STATE_BOTH, + .type = ARM_CP_IO, + .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 3, .opc2 = 1, + .access = PL2_RW, + .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYPVIRT].ctl), + .writefn = gt_hv_ctl_write, .raw_writefn = raw_write }, +#endif REGINFO_SENTINEL }; diff --git a/qemu/x86_64.h b/qemu/x86_64.h index d654ff56..bcbe7b06 100644 --- a/qemu/x86_64.h +++ b/qemu/x86_64.h @@ -167,6 +167,7 @@ #define arm_gen_test_cc arm_gen_test_cc_x86_64 #define arm_generate_debug_exceptions arm_generate_debug_exceptions_x86_64 #define arm_gt_htimer_cb arm_gt_htimer_cb_x86_64 +#define arm_gt_hvtimer_cb arm_gt_hvtimer_cb_x86_64 #define arm_gt_ptimer_cb arm_gt_ptimer_cb_x86_64 #define arm_gt_stimer_cb arm_gt_stimer_cb_x86_64 #define arm_gt_vtimer_cb arm_gt_vtimer_cb_x86_64