From d6a8d25015820e943b3f3daafd13ba94bfd477a6 Mon Sep 17 00:00:00 2001 From: Mateja Marjanovic Date: Tue, 28 May 2019 19:39:19 -0400 Subject: [PATCH] target/mips: Refactor and fix COPY_U. instructions The old version of the helper for the COPY_U. MSA instructions has been replaced with four helpers that don't use switch, and change the endianness of the given index, when executed on a big endian host. Backports commit 41d288582782cf8d63241ecb6efa1e4160fe78f7 from qemu --- qemu/header_gen.py | 4 ++- qemu/mips.h | 4 ++- qemu/mips64.h | 4 ++- qemu/mips64el.h | 4 ++- qemu/mipsel.h | 4 ++- qemu/target/mips/helper.h | 4 ++- qemu/target/mips/msa_helper.c | 59 ++++++++++++++++++++++------------- qemu/target/mips/translate.c | 21 ++++++++++++- 8 files changed, 76 insertions(+), 28 deletions(-) diff --git a/qemu/header_gen.py b/qemu/header_gen.py index b08fbcc5..a187ad45 100644 --- a/qemu/header_gen.py +++ b/qemu/header_gen.py @@ -4976,7 +4976,9 @@ mips_symbols = ( 'helper_msa_copy_s_d', 'helper_msa_copy_s_h', 'helper_msa_copy_s_w', - 'helper_msa_copy_u_df', + 'helper_msa_copy_u_b', + 'helper_msa_copy_u_h', + 'helper_msa_copy_u_w', 'helper_msa_ctcmsa', 'helper_msa_div_s_df', 'helper_msa_div_u_df', diff --git a/qemu/mips.h b/qemu/mips.h index 25143a40..2cbd65c7 100644 --- a/qemu/mips.h +++ b/qemu/mips.h @@ -3864,7 +3864,9 @@ #define helper_msa_copy_s_d helper_msa_copy_s_d_mips #define helper_msa_copy_s_h helper_msa_copy_s_h_mips #define helper_msa_copy_s_w helper_msa_copy_s_w_mips -#define helper_msa_copy_u_df helper_msa_copy_u_df_mips +#define helper_msa_copy_u_b helper_msa_copy_u_b_mips +#define helper_msa_copy_u_h helper_msa_copy_u_h_mips +#define helper_msa_copy_u_w helper_msa_copy_u_w_mips #define helper_msa_ctcmsa helper_msa_ctcmsa_mips #define helper_msa_div_s_df helper_msa_div_s_df_mips #define helper_msa_div_u_df helper_msa_div_u_df_mips diff --git a/qemu/mips64.h b/qemu/mips64.h index 0cbf852e..ef3966ab 100644 --- a/qemu/mips64.h +++ b/qemu/mips64.h @@ -3864,7 +3864,9 @@ #define helper_msa_copy_s_d helper_msa_copy_s_d_mips64 #define helper_msa_copy_s_h helper_msa_copy_s_h_mips64 #define helper_msa_copy_s_w helper_msa_copy_s_w_mips64 -#define helper_msa_copy_u_df helper_msa_copy_u_df_mips64 +#define helper_msa_copy_u_b helper_msa_copy_u_b_mips64 +#define helper_msa_copy_u_h helper_msa_copy_u_h_mips64 +#define helper_msa_copy_u_w helper_msa_copy_u_w_mips64 #define helper_msa_ctcmsa helper_msa_ctcmsa_mips64 #define helper_msa_div_s_df helper_msa_div_s_df_mips64 #define helper_msa_div_u_df helper_msa_div_u_df_mips64 diff --git a/qemu/mips64el.h b/qemu/mips64el.h index 77f9be29..3bbfa494 100644 --- a/qemu/mips64el.h +++ b/qemu/mips64el.h @@ -3864,7 +3864,9 @@ #define helper_msa_copy_s_d helper_msa_copy_s_d_mips64el #define helper_msa_copy_s_h helper_msa_copy_s_h_mips64el #define helper_msa_copy_s_w helper_msa_copy_s_w_mips64el -#define helper_msa_copy_u_df helper_msa_copy_u_df_mips64el +#define helper_msa_copy_u_b helper_msa_copy_u_b_mips64el +#define helper_msa_copy_u_h helper_msa_copy_u_h_mips64el +#define helper_msa_copy_u_w helper_msa_copy_u_w_mips64el #define helper_msa_ctcmsa helper_msa_ctcmsa_mips64el #define helper_msa_div_s_df helper_msa_div_s_df_mips64el #define helper_msa_div_u_df helper_msa_div_u_df_mips64el diff --git a/qemu/mipsel.h b/qemu/mipsel.h index 18713b00..be88164f 100644 --- a/qemu/mipsel.h +++ b/qemu/mipsel.h @@ -3864,7 +3864,9 @@ #define helper_msa_copy_s_d helper_msa_copy_s_d_mipsel #define helper_msa_copy_s_h helper_msa_copy_s_h_mipsel #define helper_msa_copy_s_w helper_msa_copy_s_w_mipsel -#define helper_msa_copy_u_df helper_msa_copy_u_df_mipsel +#define helper_msa_copy_u_b helper_msa_copy_u_b_mipsel +#define helper_msa_copy_u_h helper_msa_copy_u_h_mipsel +#define helper_msa_copy_u_w helper_msa_copy_u_w_mipsel #define helper_msa_ctcmsa helper_msa_ctcmsa_mipsel #define helper_msa_div_s_df helper_msa_div_s_df_mipsel #define helper_msa_div_u_df helper_msa_div_u_df_mipsel diff --git a/qemu/target/mips/helper.h b/qemu/target/mips/helper.h index 7208ef94..e5898a5a 100644 --- a/qemu/target/mips/helper.h +++ b/qemu/target/mips/helper.h @@ -877,7 +877,6 @@ DEF_HELPER_5(msa_hsub_u_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_sldi_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_splati_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_copy_u_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_insert_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_insve_df, void, env, i32, i32, i32, i32) DEF_HELPER_3(msa_ctcmsa, void, env, tl, i32) @@ -942,6 +941,9 @@ DEF_HELPER_4(msa_copy_s_b, void, env, i32, i32, i32) DEF_HELPER_4(msa_copy_s_h, void, env, i32, i32, i32) DEF_HELPER_4(msa_copy_s_w, void, env, i32, i32, i32) DEF_HELPER_4(msa_copy_s_d, void, env, i32, i32, i32) +DEF_HELPER_4(msa_copy_u_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_copy_u_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_copy_u_w, void, env, i32, i32, i32) DEF_HELPER_4(msa_fclass_df, void, env, i32, i32, i32) DEF_HELPER_4(msa_ftrunc_s_df, void, env, i32, i32, i32) diff --git a/qemu/target/mips/msa_helper.c b/qemu/target/mips/msa_helper.c index 0fa59892..1d3eee47 100644 --- a/qemu/target/mips/msa_helper.c +++ b/qemu/target/mips/msa_helper.c @@ -1298,29 +1298,46 @@ void helper_msa_copy_s_d(CPUMIPSState *env, uint32_t rd, env->active_tc.gpr[rd] = (int64_t)env->active_fpu.fpr[ws].wr.d[n]; } -void helper_msa_copy_u_df(CPUMIPSState *env, uint32_t df, uint32_t rd, - uint32_t ws, uint32_t n) +void helper_msa_copy_u_b(CPUMIPSState *env, uint32_t rd, + uint32_t ws, uint32_t n) { - n %= DF_ELEMENTS(df); - - switch (df) { - case DF_BYTE: - env->active_tc.gpr[rd] = (uint8_t)env->active_fpu.fpr[ws].wr.b[n]; - break; - case DF_HALF: - env->active_tc.gpr[rd] = (uint16_t)env->active_fpu.fpr[ws].wr.h[n]; - break; - case DF_WORD: - env->active_tc.gpr[rd] = (uint32_t)env->active_fpu.fpr[ws].wr.w[n]; - break; -#ifdef TARGET_MIPS64 - case DF_DOUBLE: - env->active_tc.gpr[rd] = (uint64_t)env->active_fpu.fpr[ws].wr.d[n]; - break; -#endif - default: - assert(0); + n %= 16; +#if defined(HOST_WORDS_BIGENDIAN) + if (n < 8) { + n = 8 - n - 1; + } else { + n = 24 - n - 1; } +#endif + env->active_tc.gpr[rd] = (uint8_t)env->active_fpu.fpr[ws].wr.b[n]; +} + +void helper_msa_copy_u_h(CPUMIPSState *env, uint32_t rd, + uint32_t ws, uint32_t n) +{ + n %= 8; +#if defined(HOST_WORDS_BIGENDIAN) + if (n < 4) { + n = 4 - n - 1; + } else { + n = 12 - n - 1; + } +#endif + env->active_tc.gpr[rd] = (uint16_t)env->active_fpu.fpr[ws].wr.h[n]; +} + +void helper_msa_copy_u_w(CPUMIPSState *env, uint32_t rd, + uint32_t ws, uint32_t n) +{ + n %= 4; +#if defined(HOST_WORDS_BIGENDIAN) + if (n < 2) { + n = 2 - n - 1; + } else { + n = 6 - n - 1; + } +#endif + env->active_tc.gpr[rd] = (uint32_t)env->active_fpu.fpr[ws].wr.w[n]; } void helper_msa_insert_df(CPUMIPSState *env, uint32_t df, uint32_t wd, diff --git a/qemu/target/mips/translate.c b/qemu/target/mips/translate.c index ca725f19..1c53fb4c 100644 --- a/qemu/target/mips/translate.c +++ b/qemu/target/mips/translate.c @@ -28458,6 +28458,11 @@ static void gen_msa_elm_df(CPUMIPSState *env, DisasContext *ctx, uint32_t df, generate_exception_end(ctx, EXCP_RI); break; } + if ((MASK_MSA_ELM(ctx->opcode) == OPC_COPY_U_df) && + (df == DF_WORD)) { + generate_exception_end(ctx, EXCP_RI); + break; + } #endif switch (MASK_MSA_ELM(ctx->opcode)) { case OPC_COPY_S_df: @@ -28484,7 +28489,21 @@ static void gen_msa_elm_df(CPUMIPSState *env, DisasContext *ctx, uint32_t df, break; case OPC_COPY_U_df: if (likely(wd != 0)) { - gen_helper_msa_copy_u_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, tn); + switch (df) { + case DF_BYTE: + gen_helper_msa_copy_u_b(tcg_ctx, tcg_ctx->cpu_env, twd, tws, tn); + break; + case DF_HALF: + gen_helper_msa_copy_u_h(tcg_ctx, tcg_ctx->cpu_env, twd, tws, tn); + break; +#if defined(TARGET_MIPS64) + case DF_WORD: + gen_helper_msa_copy_u_w(tcg_ctx, tcg_ctx->cpu_env, twd, tws, tn); + break; +#endif + default: + assert(0); + } } break; case OPC_INSERT_df: