From d8d0d082628597c62009e3e41e463813f0f0ddf6 Mon Sep 17 00:00:00 2001
From: Paolo Bonzini <pbonzini@redhat.com>
Date: Mon, 26 Feb 2018 02:34:12 -0500
Subject: [PATCH] target-i386: fix ordering of fields in CPUX86State

Make sure reset zeroes TSC_AUX, XCR0, PKRU. Move XSTATE_BV from the
"vmstate only" section to the "KVM only" section.

Backports commit 7616f1c2da1c0f336a474a56ad6d32e15ccd666e from qemu
---
 qemu/target-i386/cpu.h | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/qemu/target-i386/cpu.h b/qemu/target-i386/cpu.h
index 2d7e3c1b..bc02eaef 100644
--- a/qemu/target-i386/cpu.h
+++ b/qemu/target-i386/cpu.h
@@ -1036,6 +1036,9 @@ typedef struct CPUX86State {
     uint64_t tsc;
     uint64_t tsc_adjust;
     uint64_t tsc_deadline;
+    uint64_t tsc_aux;
+
+    uint64_t xcr0;
 
     uint64_t mcg_status;
     uint64_t msr_ia32_misc_enable;
@@ -1052,6 +1055,8 @@ typedef struct CPUX86State {
     uint64_t pat;
     uint32_t smbase;
 
+    uint32_t pkru;
+
     /* End of state preserved by INIT (dummy marker).  */
     //struct {} end_init_save;
     int end_init_save;
@@ -1129,19 +1134,15 @@ typedef struct CPUX86State {
     uint64_t mcg_ext_ctl;
     uint64_t mce_banks[MCE_BANKS_DEF*4];
 
-    uint64_t tsc_aux;
+    uint64_t xstate_bv;
 
     /* vmstate */
     uint16_t fpus_vmstate;
     uint16_t fptag_vmstate;
     uint16_t fpregs_format_vmstate;
-    uint64_t xstate_bv;
 
-    uint64_t xcr0;
     uint64_t xss;
 
-    uint32_t pkru;
-
     TPRAccess tpr_access_type;
 
     // Unicorn engine