From d9184b16a9e970e8ebdc47a6f99e7d076c7c2c62 Mon Sep 17 00:00:00 2001
From: Richard Henderson <richard.henderson@linaro.org>
Date: Wed, 20 Nov 2019 12:14:58 -0500
Subject: [PATCH] target/arm: Convert T16 add/sub (3 low, 2 low and imm)

Backports commit c4d3095bb62bdac0b4f9cb180bd7aa0b40c2c270 from qemu
---
 qemu/target/arm/t16.decode  | 16 ++++++++++++++++
 qemu/target/arm/translate.c | 26 ++------------------------
 2 files changed, 18 insertions(+), 24 deletions(-)

diff --git a/qemu/target/arm/t16.decode b/qemu/target/arm/t16.decode
index a7a437f9..2b5f368d 100644
--- a/qemu/target/arm/t16.decode
+++ b/qemu/target/arm/t16.decode
@@ -117,3 +117,19 @@ ADD_rri         10101 rd:3 ........ \
 
 STM             11000 ... ........              @ldstm
 LDM_t16         11001 ... ........              @ldstm
+
+# Add/subtract (three low registers)
+
+@addsub_3       ....... rm:3 rn:3 rd:3 \
+                &s_rrr_shi %s shim=0 shty=0
+
+ADD_rrri        0001100 ... ... ...             @addsub_3
+SUB_rrri        0001101 ... ... ...             @addsub_3
+
+# Add/subtract (two low registers and immediate)
+
+@addsub_2i      ....... imm:3 rn:3 rd:3 \
+                &s_rri_rot %s rot=0
+
+ADD_rri         0001 110 ... ... ...            @addsub_2i
+SUB_rri         0001 111 ... ... ...            @addsub_2i
diff --git a/qemu/target/arm/translate.c b/qemu/target/arm/translate.c
index dacf6479..17ff8b52 100644
--- a/qemu/target/arm/translate.c
+++ b/qemu/target/arm/translate.c
@@ -11043,31 +11043,9 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
              * 0b0001_1xxx_xxxx_xxxx
              *  - Add, subtract (three low registers)
              *  - Add, subtract (two low registers and immediate)
+             * In decodetree.
              */
-            rn = (insn >> 3) & 7;
-            tmp = load_reg(s, rn);
-            if (insn & (1 << 10)) {
-                /* immediate */
-                tmp2 = tcg_temp_new_i32(tcg_ctx);
-                tcg_gen_movi_i32(tcg_ctx, tmp2, (insn >> 6) & 7);
-            } else {
-                /* reg */
-                rm = (insn >> 6) & 7;
-                tmp2 = load_reg(s, rm);
-            }
-            if (insn & (1 << 9)) {
-                if (s->condexec_mask)
-                    tcg_gen_sub_i32(tcg_ctx, tmp, tmp, tmp2);
-                else
-                    gen_sub_CC(s, tmp, tmp, tmp2);
-            } else {
-                if (s->condexec_mask)
-                    tcg_gen_add_i32(tcg_ctx, tmp, tmp, tmp2);
-                else
-                    gen_add_CC(s, tmp, tmp, tmp2);
-            }
-            tcg_temp_free_i32(tcg_ctx, tmp2);
-            store_reg(s, rd, tmp);
+            goto illegal_op;
         } else {
             /* shift immediate */
             rm = (insn >> 3) & 7;