diff --git a/qemu/target/arm/translate-neon.inc.c b/qemu/target/arm/translate-neon.inc.c
index f5ccfdfc..6977895a 100644
--- a/qemu/target/arm/translate-neon.inc.c
+++ b/qemu/target/arm/translate-neon.inc.c
@@ -3045,7 +3045,7 @@ static bool trans_VREV64(DisasContext *s, arg_VREV64 *a)
                 tcg_gen_bswap32_i32(tcg_ctx, tmp[half], tmp[half]);
                 break;
             case 1:
-                gen_swap_half(s, tmp[half]);
+                gen_swap_half(s, tmp[half], tmp[half]);
                 break;
             case 2:
                 break;
diff --git a/qemu/target/arm/translate.c b/qemu/target/arm/translate.c
index a1d5250e..b8316f4f 100644
--- a/qemu/target/arm/translate.c
+++ b/qemu/target/arm/translate.c
@@ -386,10 +386,10 @@ static void gen_revsh(DisasContext *s, TCGv_i32 dest, TCGv_i32 var)
 }
 
 /* Swap low and high halfwords.  */
-static void gen_swap_half(DisasContext *s, TCGv_i32 var)
+static void gen_swap_half(DisasContext *s, TCGv_i32 dest, TCGv_i32 var)
 {
     TCGContext *tcg_ctx = s->uc->tcg_ctx;
-    tcg_gen_rotri_i32(tcg_ctx, var, var, 16);
+    tcg_gen_rotri_i32(tcg_ctx, dest, var, 16);
 }
 
 /* Dual 16-bit add.  Result placed in t0 and t1 is marked as dead.
@@ -5065,7 +5065,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
                         case NEON_2RM_VREV32:
                             switch (size) {
                             case 0: tcg_gen_bswap32_i32(tcg_ctx, tmp, tmp); break;
-                            case 1: gen_swap_half(s, tmp); break;
+                            case 1: gen_swap_half(s, tmp, tmp); break;
                             default: abort();
                             }
                             break;
@@ -8308,7 +8308,7 @@ static bool op_smlad(DisasContext *s, arg_rrrr *a, bool m_swap, bool sub)
     t1 = load_reg(s, a->rn);
     t2 = load_reg(s, a->rm);
     if (m_swap) {
-        gen_swap_half(s, t2);
+        gen_swap_half(s, t2, t2);
     }
     gen_smul_dual(s, t1, t2);
 
@@ -8367,7 +8367,7 @@ static bool op_smlald(DisasContext *s, arg_rrrr *a, bool m_swap, bool sub)
     t1 = load_reg(s, a->rn);
     t2 = load_reg(s, a->rm);
     if (m_swap) {
-        gen_swap_half(s, t2);
+        gen_swap_half(s, t2, t2);
     }
     gen_smul_dual(s, t1, t2);