diff --git a/qemu/header_gen.py b/qemu/header_gen.py index 17ef2bed..81011ff3 100644 --- a/qemu/header_gen.py +++ b/qemu/header_gen.py @@ -7295,6 +7295,10 @@ riscv_symbols = ( 'helper_vrgather_vx_h', 'helper_vrgather_vx_w', 'helper_vrgather_vx_d', + 'helper_vcompress_vm_b', + 'helper_vcompress_vm_h', + 'helper_vcompress_vm_w', + 'helper_vcompress_vm_d', 'pmp_hart_has_privs', 'pmpaddr_csr_read', 'pmpaddr_csr_write', diff --git a/qemu/riscv32.h b/qemu/riscv32.h index 246aab91..c472d27f 100644 --- a/qemu/riscv32.h +++ b/qemu/riscv32.h @@ -4731,6 +4731,10 @@ #define helper_vrgather_vx_h helper_vrgather_vx_h_riscv32 #define helper_vrgather_vx_w helper_vrgather_vx_w_riscv32 #define helper_vrgather_vx_d helper_vrgather_vx_d_riscv32 +#define helper_vcompress_vm_b helper_vcompress_vm_b_riscv32 +#define helper_vcompress_vm_h helper_vcompress_vm_h_riscv32 +#define helper_vcompress_vm_w helper_vcompress_vm_w_riscv32 +#define helper_vcompress_vm_d helper_vcompress_vm_d_riscv32 #define pmp_hart_has_privs pmp_hart_has_privs_riscv32 #define pmpaddr_csr_read pmpaddr_csr_read_riscv32 #define pmpaddr_csr_write pmpaddr_csr_write_riscv32 diff --git a/qemu/riscv64.h b/qemu/riscv64.h index 5d012221..b4bb0c8f 100644 --- a/qemu/riscv64.h +++ b/qemu/riscv64.h @@ -4731,6 +4731,10 @@ #define helper_vrgather_vx_h helper_vrgather_vx_h_riscv64 #define helper_vrgather_vx_w helper_vrgather_vx_w_riscv64 #define helper_vrgather_vx_d helper_vrgather_vx_d_riscv64 +#define helper_vcompress_vm_b helper_vcompress_vm_b_riscv64 +#define helper_vcompress_vm_h helper_vcompress_vm_h_riscv64 +#define helper_vcompress_vm_w helper_vcompress_vm_w_riscv64 +#define helper_vcompress_vm_d helper_vcompress_vm_d_riscv64 #define pmp_hart_has_privs pmp_hart_has_privs_riscv64 #define pmpaddr_csr_read pmpaddr_csr_read_riscv64 #define pmpaddr_csr_write pmpaddr_csr_write_riscv64 diff --git a/qemu/target/riscv/helper.h b/qemu/target/riscv/helper.h index 8ff9b1f5..6a1b25a6 100644 --- a/qemu/target/riscv/helper.h +++ b/qemu/target/riscv/helper.h @@ -1148,3 +1148,8 @@ DEF_HELPER_6(vrgather_vx_b, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vrgather_vx_h, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vrgather_vx_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vrgather_vx_d, void, ptr, ptr, tl, ptr, env, i32) + +DEF_HELPER_6(vcompress_vm_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vcompress_vm_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vcompress_vm_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vcompress_vm_d, void, ptr, ptr, ptr, ptr, env, i32) diff --git a/qemu/target/riscv/insn32.decode b/qemu/target/riscv/insn32.decode index 80d5ff74..bdd85630 100644 --- a/qemu/target/riscv/insn32.decode +++ b/qemu/target/riscv/insn32.decode @@ -577,6 +577,7 @@ vslide1down_vx 001111 . ..... ..... 110 ..... 1010111 @r_vm vrgather_vv 001100 . ..... ..... 000 ..... 1010111 @r_vm vrgather_vx 001100 . ..... ..... 100 ..... 1010111 @r_vm vrgather_vi 001100 . ..... ..... 011 ..... 1010111 @r_vm +vcompress_vm 010111 - ..... ..... 010 ..... 1010111 @r vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm vsetvl 1000000 ..... ..... 111 ..... 1010111 @r diff --git a/qemu/target/riscv/insn_trans/trans_rvv.inc.c b/qemu/target/riscv/insn_trans/trans_rvv.inc.c index 5a1b6145..14cfb429 100644 --- a/qemu/target/riscv/insn_trans/trans_rvv.inc.c +++ b/qemu/target/riscv/insn_trans/trans_rvv.inc.c @@ -2915,3 +2915,37 @@ static bool trans_vrgather_vi(DisasContext *s, arg_rmrr *a) } return true; } + +/* Vector Compress Instruction */ +static bool vcompress_vm_check(DisasContext *s, arg_r *a) +{ + return (vext_check_isa_ill(s) && + vext_check_reg(s, a->rd, false) && + vext_check_reg(s, a->rs2, false) && + vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs1, 1) && + (a->rd != a->rs2)); +} + +static bool trans_vcompress_vm(DisasContext *s, arg_r *a) +{ + TCGContext *tcg_ctx = s->uc->tcg_ctx; + + if (vcompress_vm_check(s, a)) { + uint32_t data = 0; + static gen_helper_gvec_4_ptr * const fns[4] = { + gen_helper_vcompress_vm_b, gen_helper_vcompress_vm_h, + gen_helper_vcompress_vm_w, gen_helper_vcompress_vm_d, + }; + TCGLabel *over = gen_new_label(tcg_ctx); + tcg_gen_brcondi_tl(tcg_ctx, TCG_COND_EQ, tcg_ctx->cpu_vl_risc, 0, over); + + data = FIELD_DP32(data, VDATA, MLEN, s->mlen); + data = FIELD_DP32(data, VDATA, LMUL, s->lmul); + tcg_gen_gvec_4_ptr(tcg_ctx, vreg_ofs(s, a->rd), vreg_ofs(s, 0), + vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2), + tcg_ctx->cpu_env, 0, s->vlen / 8, data, fns[s->sew]); + gen_set_label(tcg_ctx, over); + return true; + } + return false; +} diff --git a/qemu/target/riscv/vector_helper.c b/qemu/target/riscv/vector_helper.c index 7117e06e..b29f70fa 100644 --- a/qemu/target/riscv/vector_helper.c +++ b/qemu/target/riscv/vector_helper.c @@ -4847,3 +4847,29 @@ GEN_VEXT_VRGATHER_VX(vrgather_vx_b, uint8_t, H1, clearb) GEN_VEXT_VRGATHER_VX(vrgather_vx_h, uint16_t, H2, clearh) GEN_VEXT_VRGATHER_VX(vrgather_vx_w, uint32_t, H4, clearl) GEN_VEXT_VRGATHER_VX(vrgather_vx_d, uint64_t, H8, clearq) + +/* Vector Compress Instruction */ +#define GEN_VEXT_VCOMPRESS_VM(NAME, ETYPE, H, CLEAR_FN) \ +void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ + CPURISCVState *env, uint32_t desc) \ +{ \ + uint32_t mlen = vext_mlen(desc); \ + uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \ + uint32_t vl = env->vl; \ + uint32_t num = 0, i; \ + \ + for (i = 0; i < vl; i++) { \ + if (!vext_elem_mask(vs1, mlen, i)) { \ + continue; \ + } \ + *((ETYPE *)vd + H(num)) = *((ETYPE *)vs2 + H(i)); \ + num++; \ + } \ + CLEAR_FN(vd, num, num * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \ +} + +/* Compress into vd elements of vs2 where vs1 is enabled */ +GEN_VEXT_VCOMPRESS_VM(vcompress_vm_b, uint8_t, H1, clearb) +GEN_VEXT_VCOMPRESS_VM(vcompress_vm_h, uint16_t, H2, clearh) +GEN_VEXT_VCOMPRESS_VM(vcompress_vm_w, uint32_t, H4, clearl) +GEN_VEXT_VCOMPRESS_VM(vcompress_vm_d, uint64_t, H8, clearq)