diff --git a/qemu/target-arm/translate-a64.c b/qemu/target-arm/translate-a64.c index 88b5ea22..adde3896 100644 --- a/qemu/target-arm/translate-a64.c +++ b/qemu/target-arm/translate-a64.c @@ -11280,8 +11280,9 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu, //tcg_ctx->gen_opc_icount[lj] = num_insns; } tcg_gen_insn_start(tcg_ctx, dc->pc); + num_insns++; - //if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) { + //if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) { // gen_io_start(); //} @@ -11296,7 +11297,7 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu, * "did not step an insn" case, and so the syndrome ISV and EX * bits should be zero. */ - assert(num_insns == 0); + assert(num_insns == 1); gen_exception(dc, EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0)); dc->is_jmp = DISAS_EXC; break; @@ -11314,7 +11315,6 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu, * Also stop translation when a page boundary is reached. This * ensures prefetch aborts occur at the right place. */ - num_insns++; } while (!dc->is_jmp && !tcg_op_buf_full(tcg_ctx) && !cs->singlestep_enabled && !dc->ss_active && diff --git a/qemu/target-arm/translate.c b/qemu/target-arm/translate.c index cc222f96..4c6af1b4 100644 --- a/qemu/target-arm/translate.c +++ b/qemu/target-arm/translate.c @@ -11478,8 +11478,9 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu, //tcg_ctx->gen_opc_icount[lj] = num_insns; } tcg_gen_insn_start(tcg_ctx, dc->pc); + num_insns++; - //if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) { + //if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) { // gen_io_start(); //} @@ -11494,7 +11495,7 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu, * "did not step an insn" case, and so the syndrome ISV and EX * bits should be zero. */ - assert(num_insns == 0); + assert(num_insns == 1); gen_exception(dc, EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0)); goto done_generating; } @@ -11537,7 +11538,6 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu, * Otherwise the subsequent code could get translated several times. * Also stop translation when a page boundary is reached. This * ensures prefetch aborts occur at the right place. */ - num_insns ++; } while (!dc->is_jmp && !tcg_op_buf_full(tcg_ctx) && !cs->singlestep_enabled && !dc->ss_active && diff --git a/qemu/target-i386/translate.c b/qemu/target-i386/translate.c index 3ad6114e..793f30f2 100644 --- a/qemu/target-i386/translate.c +++ b/qemu/target-i386/translate.c @@ -8730,15 +8730,15 @@ static inline void gen_intermediate_code_internal(uint8_t *gen_opc_cc_op, // tcg_ctx->gen_opc_icount[lj] = num_insns; } tcg_gen_insn_start(tcg_ctx, pc_start); + num_insns++; - //if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) { + //if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) { // gen_io_start(); //} // Unicorn: save current PC address to sync EIP dc->prev_pc = pc_ptr; pc_ptr = disas_insn(env, dc, pc_ptr); - num_insns++; /* stop translation if indicated */ if (dc->is_jmp) break; diff --git a/qemu/target-m68k/translate.c b/qemu/target-m68k/translate.c index 51b84fed..86c34896 100644 --- a/qemu/target-m68k/translate.c +++ b/qemu/target-m68k/translate.c @@ -3137,14 +3137,14 @@ gen_intermediate_code_internal(M68kCPU *cpu, TranslationBlock *tb, //tcg_ctx.gen_opc_icount[lj] = num_insns; } tcg_gen_insn_start(tcg_ctx, s->pc); + num_insns++; - //if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) { + //if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) { // gen_io_start(); //} dc->insn_pc = dc->pc; disas_m68k_insn(env, dc); - num_insns++; } while (!dc->is_jmp && !tcg_op_buf_full(tcg_ctx) && !cs->singlestep_enabled && (pc_offset) < (TARGET_PAGE_SIZE - 32) && diff --git a/qemu/target-mips/translate.c b/qemu/target-mips/translate.c index 34a50005..d310df29 100644 --- a/qemu/target-mips/translate.c +++ b/qemu/target-mips/translate.c @@ -19256,8 +19256,9 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb, tcg_ctx->gen_opc_icount[lj] = num_insns; } tcg_gen_insn_start(tcg_ctx, ctx->pc); + num_insns++; - //if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) { + //if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) { // gen_io_start(); //} @@ -19319,8 +19320,6 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb, } ctx.pc += insn_bytes; - num_insns++; - /* Execute a branch and its delay slot as a single instruction. This is what GDB expects and is consistent with what the hardware does (e.g. if a delay slot instruction faults, the diff --git a/qemu/target-sparc/translate.c b/qemu/target-sparc/translate.c index a0d0d67f..6405283f 100644 --- a/qemu/target-sparc/translate.c +++ b/qemu/target-sparc/translate.c @@ -5443,8 +5443,9 @@ static inline void gen_intermediate_code_internal(SPARCCPU *cpu, } } tcg_gen_insn_start(tcg_ctx, dc->pc); + num_insns++; - //if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) { + //if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) { // gen_io_start(); //} @@ -5459,7 +5460,6 @@ static inline void gen_intermediate_code_internal(SPARCCPU *cpu, } disas_sparc_insn(dc, insn, true); - num_insns++; if (dc->is_br) break;