From dd9e33bb6d3d2acd80a00c0701c0c6794bd5bddc Mon Sep 17 00:00:00 2001
From: Sergey Fedorov <serge.fdrv@gmail.com>
Date: Mon, 12 Feb 2018 20:44:07 -0500
Subject: [PATCH] target-arm: rename c1_coproc to cpacr_el1

Rename the field holding CPACR_EL1 system register state in AArch64
naming style.

Backports commit 7ebd5f2e03a00889619bb97e83062d27066d4a26 from qemu
---
 qemu/target-arm/cpu.c             | 4 ++--
 qemu/target-arm/cpu.h             | 4 ++--
 qemu/target-arm/helper.c          | 4 ++--
 qemu/target-arm/unicorn_aarch64.c | 4 ++--
 4 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/qemu/target-arm/cpu.c b/qemu/target-arm/cpu.c
index ec9d342d..256aa202 100644
--- a/qemu/target-arm/cpu.c
+++ b/qemu/target-arm/cpu.c
@@ -107,7 +107,7 @@ static void arm_cpu_reset(CPUState *s)
         /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
         env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE;
         /* and to the FP/Neon instructions */
-        env->cp15.c1_coproc = deposit64(env->cp15.c1_coproc, 20, 2, 3);
+        env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3);
 #else
         /* Reset into the highest available EL */
         if (arm_feature(env, ARM_FEATURE_EL3)) {
@@ -122,7 +122,7 @@ static void arm_cpu_reset(CPUState *s)
     } else {
 #if defined(CONFIG_USER_ONLY)
         /* Userspace expects access to cp10 and cp11 for FP/Neon */
-        env->cp15.c1_coproc = deposit64(env->cp15.c1_coproc, 20, 4, 0xf);
+        env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf);
 #endif
     }
 
diff --git a/qemu/target-arm/cpu.h b/qemu/target-arm/cpu.h
index eab57395..ee26df81 100644
--- a/qemu/target-arm/cpu.h
+++ b/qemu/target-arm/cpu.h
@@ -205,7 +205,7 @@ typedef struct CPUARMState {
             };
             uint64_t sctlr_el[4];
         };
-        uint64_t c1_coproc; /* Coprocessor access register.  */
+        uint64_t cpacr_el1; /* Architectural feature access control register */
         uint32_t c1_xscaleauxcr; /* XScale auxiliary control register.  */
         uint64_t sder; /* Secure debug enable register. */
         uint32_t nsacr; /* Non-secure access control register. */
@@ -1838,7 +1838,7 @@ static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
     int fpen;
 
     if (arm_feature(env, ARM_FEATURE_V6)) {
-        fpen = extract32(env->cp15.c1_coproc, 20, 2);
+        fpen = extract32(env->cp15.cpacr_el1, 20, 2);
     } else {
         /* CPACR doesn't exist before v6, so VFP is always accessible */
         fpen = 3;
diff --git a/qemu/target-arm/helper.c b/qemu/target-arm/helper.c
index a3970f90..7ad64ab5 100644
--- a/qemu/target-arm/helper.c
+++ b/qemu/target-arm/helper.c
@@ -473,7 +473,7 @@ static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
         }
         value &= mask;
     }
-    env->cp15.c1_coproc = value;
+    env->cp15.cpacr_el1 = value;
 }
 
 static const ARMCPRegInfo v6_cp_reginfo[] = {
@@ -495,7 +495,7 @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
     { "WFAR", 15,6,0, 0,0,1, 0,
       ARM_CP_CONST, PL1_RW, 0, NULL, 0, },
     { "CPACR", 0,1,0, 3,0,2, ARM_CP_STATE_BOTH, 
-      0, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c1_coproc), {0, 0},
+      0, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.cpacr_el1), {0, 0},
       NULL, NULL, cpacr_write },
     REGINFO_SENTINEL
 };
diff --git a/qemu/target-arm/unicorn_aarch64.c b/qemu/target-arm/unicorn_aarch64.c
index 32f9d772..3bd7004b 100644
--- a/qemu/target-arm/unicorn_aarch64.c
+++ b/qemu/target-arm/unicorn_aarch64.c
@@ -77,7 +77,7 @@ int arm64_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int co
             switch(regid) {
                 default: break;
                 case UC_ARM64_REG_CPACR_EL1:
-                    *(uint32_t *)value = ARM_CPU(uc, mycpu)->env.cp15.c1_coproc;
+                    *(uint32_t *)value = ARM_CPU(uc, mycpu)->env.cp15.cpacr_el1;
                     break;
                 case UC_ARM64_REG_ESR:
                     *(uint32_t *)value = ARM_CPU(uc, mycpu)->env.exception.syndrome;
@@ -154,7 +154,7 @@ int arm64_reg_write(struct uc_struct *uc, unsigned int *regs, void* const* vals,
             switch(regid) {
                 default: break;
                 case UC_ARM64_REG_CPACR_EL1:
-                    ARM_CPU(uc, mycpu)->env.cp15.c1_coproc = *(uint32_t *)value;
+                    ARM_CPU(uc, mycpu)->env.cp15.cpacr_el1 = *(uint32_t *)value;
                     break;
                 case UC_ARM64_REG_TPIDR_EL0:
                     ARM_CPU(uc, mycpu)->env.cp15.tpidr_el[0] = *(uint64_t *)value;