From dfa3d51a0f26f9c7e5146db846a2718254013678 Mon Sep 17 00:00:00 2001 From: Petar Jovanovic Date: Thu, 15 Feb 2018 15:42:18 -0500 Subject: [PATCH] target-mips: remove wrong checks for recip.fmt and rsqrt.fmt Instructions recip.{s|d} and rsqrt.{s|d} do not require 64-bit FPU neither they require any particular mode for its FPU. This patch removes the checks that may break a program that uses these instructions. Backports commit ca6c7803d2beae43299a80f4549d36579881fc0b from qemu --- qemu/target-mips/translate.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/qemu/target-mips/translate.c b/qemu/target-mips/translate.c index e285c26e..efd91a8d 100644 --- a/qemu/target-mips/translate.c +++ b/qemu/target-mips/translate.c @@ -9375,7 +9375,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, opn = "movn.s"; break; case OPC_RECIP_S: - check_cop1x(ctx); { TCGv_i32 fp0 = tcg_temp_new_i32(tcg_ctx); @@ -9387,7 +9386,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, opn = "recip.s"; break; case OPC_RSQRT_S: - check_cop1x(ctx); { TCGv_i32 fp0 = tcg_temp_new_i32(tcg_ctx); @@ -9920,7 +9918,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, opn = "movn.d"; break; case OPC_RECIP_D: - check_cp1_64bitmode(ctx); + check_cp1_registers(ctx, fs | fd); { TCGv_i64 fp0 = tcg_temp_new_i64(tcg_ctx); @@ -9932,7 +9930,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, opn = "recip.d"; break; case OPC_RSQRT_D: - check_cp1_64bitmode(ctx); + check_cp1_registers(ctx, fs | fd); { TCGv_i64 fp0 = tcg_temp_new_i64(tcg_ctx);