From e4ce0e92b1c322c780940f2795f991eb76efe5b4 Mon Sep 17 00:00:00 2001 From: "Maciej W. Rozycki" Date: Sun, 11 Feb 2018 16:48:11 -0500 Subject: [PATCH] target-mips: Also apply the CP0.Status mask to MTTC0 Make CP0.Status writes made with the MTTC0 instruction respect this register's mask just like all the other places. Also preserve the current values of masked out bits. Backports commit 1d725ae952a14b30c84b7bc81b218b8ba77dd311 from qemu --- qemu/target-mips/op_helper.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/qemu/target-mips/op_helper.c b/qemu/target-mips/op_helper.c index 3499fc92..b56a82c3 100644 --- a/qemu/target-mips/op_helper.c +++ b/qemu/target-mips/op_helper.c @@ -1412,9 +1412,10 @@ void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1) void helper_mttc0_status(CPUMIPSState *env, target_ulong arg1) { int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + uint32_t mask = env->CP0_Status_rw_bitmask & ~0xf1000018; CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); - other->CP0_Status = arg1 & ~0xf1000018; + other->CP0_Status = (other->CP0_Status & ~mask) | (arg1 & mask); sync_c0_status(env, other, other_tc); }