From e5797bb0b70d2eb3b77a5dca617eb96d70a74717 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Sat, 10 Nov 2018 08:02:23 -0500 Subject: [PATCH] target/arm: V8M should not imply V7VE Instantiating mps2-an505 (cortex-m33) will fail make check when V7VE asserts that ID_ISAR0.Divide includes ARM division. It is also wrong to include ARM_FEATURE_LPAE. Backports commit 5256df880d1312a58472af3fb0a3c51e708f2161 from qemu --- qemu/target/arm/cpu.c | 6 +++++- qemu/target/arm/helper.c | 2 +- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/qemu/target/arm/cpu.c b/qemu/target/arm/cpu.c index b9adde78..d66c63d7 100644 --- a/qemu/target/arm/cpu.c +++ b/qemu/target/arm/cpu.c @@ -593,7 +593,11 @@ static int arm_cpu_realizefn(struct uc_struct *uc, DeviceState *dev, Error **err /* Some features automatically imply others: */ if (arm_feature(env, ARM_FEATURE_V8)) { - set_feature(env, ARM_FEATURE_V7VE); + if (arm_feature(env, ARM_FEATURE_M)) { + set_feature(env, ARM_FEATURE_V7); + } else { + set_feature(env, ARM_FEATURE_V7VE); + } } if (arm_feature(env, ARM_FEATURE_V7VE)) { /* v7 Virtualization Extensions. In real hardware this implies diff --git a/qemu/target/arm/helper.c b/qemu/target/arm/helper.c index cbdb4b86..bbcf498e 100644 --- a/qemu/target/arm/helper.c +++ b/qemu/target/arm/helper.c @@ -4400,7 +4400,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) * define these regs. */ { "ID_AA64PFR0_EL1", 0,0,4, 3,0,0, ARM_CP_STATE_AA64, - ARM_CP_NO_RAW, PL1_R, 0, NULL, cpu->id_aa64pfr0, 0, {0, 0}, + ARM_CP_NO_RAW, PL1_R, 0, NULL, cpu->isar.id_aa64pfr0, 0, {0, 0}, NULL, id_aa64pfr0_read, arm_cp_write_ignore }, { "ID_AA64PFR1_EL1", 0,0,4, 3,0,1, ARM_CP_STATE_AA64, ARM_CP_CONST, PL1_R, 0, NULL, cpu->isar.id_aa64pfr1},