diff --git a/qemu/target-sparc/translate.c b/qemu/target-sparc/translate.c
index 60c7ba20..f0ad799f 100644
--- a/qemu/target-sparc/translate.c
+++ b/qemu/target-sparc/translate.c
@@ -2632,7 +2632,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
 
     // Unicorn: trace this instruction on request
     if (dc->uc->hook_insn) {
-        struct hook_struct *trace = hook_find((uch)dc->uc, UC_HOOK_CODE, dc->pc);
+        struct hook_struct *trace = hook_find(dc->uc, UC_HOOK_CODE, dc->pc);
         if (trace)
             gen_uc_tracecode(tcg_ctx, 4, trace->callback, dc->uc, dc->pc, trace->user_data);
         // if requested to emulate only some instructions, check if
@@ -5406,7 +5406,7 @@ static inline void gen_intermediate_code_internal(SPARCCPU *cpu,
 
     // Unicorn: trace this block on request
     if (env->uc->hook_block) {
-        struct hook_struct *trace = hook_find((uch)env->uc, UC_HOOK_BLOCK, pc_start);
+        struct hook_struct *trace = hook_find(env->uc, UC_HOOK_BLOCK, pc_start);
         if (trace) {
             // save block address to see if we need to patch block size later
             env->uc->block_addr = pc_start;
diff --git a/qemu/target-sparc/unicorn.c b/qemu/target-sparc/unicorn.c
index 31c79cd7..2ca74743 100644
--- a/qemu/target-sparc/unicorn.c
+++ b/qemu/target-sparc/unicorn.c
@@ -32,12 +32,10 @@ static void sparc_set_pc(struct uc_struct *uc, uint64_t address)
     ((CPUSPARCState *)uc->current_cpu->env_ptr)->npc = address + 4;
 }
 
-void sparc_reg_reset(uch handle)
+void sparc_reg_reset(struct uc_struct *uc)
 {
-    struct uc_struct *uc = (struct uc_struct *) handle;
-    CPUArchState *env;
+    CPUArchState *env = first_cpu->env_ptr;
 
-    env = first_cpu->env_ptr;
     memset(env->gregs, 0, sizeof(env->gregs));
     memset(env->fpr, 0, sizeof(env->fpr));
     memset(env->regbase, 0, sizeof(env->regbase));
@@ -46,9 +44,8 @@ void sparc_reg_reset(uch handle)
     env->npc = 0;
 }
 
-int sparc_reg_read(uch handle, unsigned int regid, void *value)
+int sparc_reg_read(struct uc_struct *uc, unsigned int regid, void *value)
 {
-    struct uc_struct *uc = (struct uc_struct *) handle;
     CPUState *mycpu = first_cpu;
 
     if (regid >= UC_SPARC_REG_G0 && regid <= UC_SPARC_REG_G7)
@@ -71,9 +68,8 @@ int sparc_reg_read(uch handle, unsigned int regid, void *value)
 #define WRITE_BYTE_H(x, b) (x = (x & ~0xff00) | (b & 0xff))
 #define WRITE_BYTE_L(x, b) (x = (x & ~0xff) | (b & 0xff))
 
-int sparc_reg_write(uch handle, unsigned int regid, const void *value)
+int sparc_reg_write(struct uc_struct *uc, unsigned int regid, const void *value)
 {
-    struct uc_struct *uc = (struct uc_struct *) handle;
     CPUState *mycpu = first_cpu;
 
     if (regid >= UC_SPARC_REG_G0 && regid <= UC_SPARC_REG_G7)
diff --git a/qemu/target-sparc/unicorn.h b/qemu/target-sparc/unicorn.h
index 492a7ffb..89771827 100644
--- a/qemu/target-sparc/unicorn.h
+++ b/qemu/target-sparc/unicorn.h
@@ -5,10 +5,10 @@
 #define UC_QEMU_TARGET_SPARC_H
 
 // functions to read & write registers
-int sparc_reg_read(uch handle, unsigned int regid, void *value);
-int sparc_reg_write(uch handle, unsigned int regid, const void *value);
+int sparc_reg_read(struct uc_struct *uc, unsigned int regid, void *value);
+int sparc_reg_write(struct uc_struct *uc, unsigned int regid, const void *value);
 
-void sparc_reg_reset(uch handle);
+void sparc_reg_reset(struct uc_struct *uc);
 
 void sparc_uc_init(struct uc_struct* uc);
 void sparc64_uc_init(struct uc_struct* uc);
diff --git a/qemu/target-sparc/unicorn64.c b/qemu/target-sparc/unicorn64.c
index f9baef0c..20a3928e 100644
--- a/qemu/target-sparc/unicorn64.c
+++ b/qemu/target-sparc/unicorn64.c
@@ -15,12 +15,10 @@
 #define READ_BYTE_L(x) (x & 0xff)
 
 
-void sparc_reg_reset(uch handle)
+void sparc_reg_reset(struct uc_struct *uc)
 {
-    struct uc_struct *uc = (struct uc_struct *) handle;
-    CPUArchState *env;
+    CPUArchState *env = first_cpu->env_ptr;
 
-    env = first_cpu->env_ptr;
     memset(env->gregs, 0, sizeof(env->gregs));
     memset(env->fpr, 0, sizeof(env->fpr));
     memset(env->regbase, 0, sizeof(env->regbase));
@@ -29,9 +27,8 @@ void sparc_reg_reset(uch handle)
     env->npc = 0;
 }
 
-int sparc_reg_read(uch handle, unsigned int regid, void *value)
+int sparc_reg_read(struct uc_struct *uc, unsigned int regid, void *value)
 {
-    struct uc_struct *uc = (struct uc_struct *) handle;
     CPUState *mycpu = first_cpu;
 
     if (regid >= UC_SPARC_REG_G0 && regid <= UC_SPARC_REG_G7)
@@ -54,9 +51,8 @@ int sparc_reg_read(uch handle, unsigned int regid, void *value)
 #define WRITE_BYTE_H(x, b) (x = (x & ~0xff00) | (b & 0xff))
 #define WRITE_BYTE_L(x, b) (x = (x & ~0xff) | (b & 0xff))
 
-int sparc_reg_write(uch handle, unsigned int regid, const void *value)
+int sparc_reg_write(struct uc_struct *uc, unsigned int regid, const void *value)
 {
-    struct uc_struct *uc = (struct uc_struct *) handle;
     CPUState *mycpu = first_cpu;
 
     if (regid >= UC_SPARC_REG_G0 && regid <= UC_SPARC_REG_G7)