diff --git a/qemu/aarch64.h b/qemu/aarch64.h index b3beb366..35dbd562 100644 --- a/qemu/aarch64.h +++ b/qemu/aarch64.h @@ -3663,6 +3663,13 @@ #define helper_sve_saddv_b helper_sve_saddv_b_aarch64 #define helper_sve_saddv_h helper_sve_saddv_h_aarch64 #define helper_sve_saddv_s helper_sve_saddv_s_aarch64 +#define helper_sve_scvt_dd helper_sve_scvt_dd_aarch64 +#define helper_sve_scvt_dh helper_sve_scvt_dh_aarch64 +#define helper_sve_scvt_ds helper_sve_scvt_ds_aarch64 +#define helper_sve_scvt_hh helper_sve_scvt_hh_aarch64 +#define helper_sve_scvt_sh helper_sve_scvt_sh_aarch64 +#define helper_sve_scvt_sd helper_sve_scvt_sd_aarch64 +#define helper_sve_scvt_ss helper_sve_scvt_ss_aarch64 #define helper_sve_sdiv_zpzz_d helper_sve_sdiv_zpzz_d_aarch64 #define helper_sve_sdiv_zpzz_s helper_sve_sdiv_zpzz_s_aarch64 #define helper_sve_sel_pppp helper_sve_sel_pppp_aarch64 @@ -3759,6 +3766,13 @@ #define helper_sve_uaddv_d helper_sve_uaddv_d_aarch64 #define helper_sve_uaddv_h helper_sve_uaddv_h_aarch64 #define helper_sve_uaddv_s helper_sve_uaddv_s_aarch64 +#define helper_sve_ucvt_dd helper_sve_ucvt_dd_aarch64 +#define helper_sve_ucvt_dh helper_sve_ucvt_dh_aarch64 +#define helper_sve_ucvt_ds helper_sve_ucvt_ds_aarch64 +#define helper_sve_ucvt_hh helper_sve_ucvt_hh_aarch64 +#define helper_sve_ucvt_sh helper_sve_ucvt_sh_aarch64 +#define helper_sve_ucvt_sd helper_sve_ucvt_sd_aarch64 +#define helper_sve_ucvt_ss helper_sve_ucvt_ss_aarch64 #define helper_sve_udiv_zpzz_d helper_sve_udiv_zpzz_d_aarch64 #define helper_sve_udiv_zpzz_s helper_sve_udiv_zpzz_s_aarch64 #define helper_sve_umax_zpzz_b helper_sve_umax_zpzz_b_aarch64 diff --git a/qemu/aarch64eb.h b/qemu/aarch64eb.h index 218a630b..366b4cf6 100644 --- a/qemu/aarch64eb.h +++ b/qemu/aarch64eb.h @@ -3663,6 +3663,13 @@ #define helper_sve_saddv_b helper_sve_saddv_b_aarch64eb #define helper_sve_saddv_h helper_sve_saddv_h_aarch64eb #define helper_sve_saddv_s helper_sve_saddv_s_aarch64eb +#define helper_sve_scvt_dd helper_sve_scvt_dd_aarch64eb +#define helper_sve_scvt_dh helper_sve_scvt_dh_aarch64eb +#define helper_sve_scvt_ds helper_sve_scvt_ds_aarch64eb +#define helper_sve_scvt_hh helper_sve_scvt_hh_aarch64eb +#define helper_sve_scvt_sh helper_sve_scvt_sh_aarch64eb +#define helper_sve_scvt_sd helper_sve_scvt_sd_aarch64eb +#define helper_sve_scvt_ss helper_sve_scvt_ss_aarch64eb #define helper_sve_sdiv_zpzz_d helper_sve_sdiv_zpzz_d_aarch64eb #define helper_sve_sdiv_zpzz_s helper_sve_sdiv_zpzz_s_aarch64eb #define helper_sve_sel_pppp helper_sve_sel_pppp_aarch64eb @@ -3759,6 +3766,13 @@ #define helper_sve_uaddv_d helper_sve_uaddv_d_aarch64eb #define helper_sve_uaddv_h helper_sve_uaddv_h_aarch64eb #define helper_sve_uaddv_s helper_sve_uaddv_s_aarch64eb +#define helper_sve_ucvt_dd helper_sve_ucvt_dd_aarch64eb +#define helper_sve_ucvt_dh helper_sve_ucvt_dh_aarch64eb +#define helper_sve_ucvt_ds helper_sve_ucvt_ds_aarch64eb +#define helper_sve_ucvt_hh helper_sve_ucvt_hh_aarch64eb +#define helper_sve_ucvt_sh helper_sve_ucvt_sh_aarch64eb +#define helper_sve_ucvt_sd helper_sve_ucvt_sd_aarch64eb +#define helper_sve_ucvt_ss helper_sve_ucvt_ss_aarch64eb #define helper_sve_udiv_zpzz_d helper_sve_udiv_zpzz_d_aarch64eb #define helper_sve_udiv_zpzz_s helper_sve_udiv_zpzz_s_aarch64eb #define helper_sve_umax_zpzz_b helper_sve_umax_zpzz_b_aarch64eb diff --git a/qemu/header_gen.py b/qemu/header_gen.py index 8a294f05..c37eda4c 100644 --- a/qemu/header_gen.py +++ b/qemu/header_gen.py @@ -3684,6 +3684,13 @@ aarch64_symbols = ( 'helper_sve_saddv_b', 'helper_sve_saddv_h', 'helper_sve_saddv_s', + 'helper_sve_scvt_dd', + 'helper_sve_scvt_dh', + 'helper_sve_scvt_ds', + 'helper_sve_scvt_hh', + 'helper_sve_scvt_sh', + 'helper_sve_scvt_sd', + 'helper_sve_scvt_ss', 'helper_sve_sdiv_zpzz_d', 'helper_sve_sdiv_zpzz_s', 'helper_sve_sel_pppp', @@ -3780,6 +3787,13 @@ aarch64_symbols = ( 'helper_sve_uaddv_d', 'helper_sve_uaddv_h', 'helper_sve_uaddv_s', + 'helper_sve_ucvt_dd', + 'helper_sve_ucvt_dh', + 'helper_sve_ucvt_ds', + 'helper_sve_ucvt_hh', + 'helper_sve_ucvt_sh', + 'helper_sve_ucvt_sd', + 'helper_sve_ucvt_ss', 'helper_sve_udiv_zpzz_d', 'helper_sve_udiv_zpzz_s', 'helper_sve_umax_zpzz_b', diff --git a/qemu/target/arm/helper-sve.h b/qemu/target/arm/helper-sve.h index b7681289..185112e1 100644 --- a/qemu/target/arm/helper-sve.h +++ b/qemu/target/arm/helper-sve.h @@ -720,6 +720,36 @@ DEF_HELPER_FLAGS_5(gvec_rsqrts_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(gvec_rsqrts_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_scvt_hh, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_scvt_sh, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_scvt_dh, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_scvt_ss, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_scvt_sd, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_scvt_ds, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_scvt_dd, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_5(sve_ucvt_hh, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_ucvt_sh, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_ucvt_dh, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_ucvt_ss, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_ucvt_sd, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_ucvt_ds, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_ucvt_dd, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + DEF_HELPER_FLAGS_4(sve_ld1bb_r, TCG_CALL_NO_WG, void, env, ptr, tl, i32) DEF_HELPER_FLAGS_4(sve_ld2bb_r, TCG_CALL_NO_WG, void, env, ptr, tl, i32) DEF_HELPER_FLAGS_4(sve_ld3bb_r, TCG_CALL_NO_WG, void, env, ptr, tl, i32) diff --git a/qemu/target/arm/sve.decode b/qemu/target/arm/sve.decode index c7f4731f..2a6c7338 100644 --- a/qemu/target/arm/sve.decode +++ b/qemu/target/arm/sve.decode @@ -127,6 +127,9 @@ @rd_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 &rpr_esz @rd_pg4_pn ........ esz:2 ... ... .. pg:4 . rn:4 rd:5 &rpr_esz +# One register operand, with governing predicate, no vector element size +@rd_pg_rn_e0 ........ .. ... ... ... pg:3 rn:5 rd:5 &rpr_esz esz=0 + # Three register operand, with governing predicate, vector element size @rda_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 rd:5 \ &rprrr_esz ra=%reg_movprfx @@ -681,6 +684,25 @@ FTSMUL 01100101 .. 0 ..... 000 011 ..... ..... @rd_rn_rm FRECPS 01100101 .. 0 ..... 000 110 ..... ..... @rd_rn_rm FRSQRTS 01100101 .. 0 ..... 000 111 ..... ..... @rd_rn_rm +### SVE FP Unary Operations Predicated Group + +# SVE integer convert to floating-point +SCVTF_hh 01100101 01 010 01 0 101 ... ..... ..... @rd_pg_rn_e0 +SCVTF_sh 01100101 01 010 10 0 101 ... ..... ..... @rd_pg_rn_e0 +SCVTF_dh 01100101 01 010 11 0 101 ... ..... ..... @rd_pg_rn_e0 +SCVTF_ss 01100101 10 010 10 0 101 ... ..... ..... @rd_pg_rn_e0 +SCVTF_sd 01100101 11 010 00 0 101 ... ..... ..... @rd_pg_rn_e0 +SCVTF_ds 01100101 11 010 10 0 101 ... ..... ..... @rd_pg_rn_e0 +SCVTF_dd 01100101 11 010 11 0 101 ... ..... ..... @rd_pg_rn_e0 + +UCVTF_hh 01100101 01 010 01 1 101 ... ..... ..... @rd_pg_rn_e0 +UCVTF_sh 01100101 01 010 10 1 101 ... ..... ..... @rd_pg_rn_e0 +UCVTF_dh 01100101 01 010 11 1 101 ... ..... ..... @rd_pg_rn_e0 +UCVTF_ss 01100101 10 010 10 1 101 ... ..... ..... @rd_pg_rn_e0 +UCVTF_sd 01100101 11 010 00 1 101 ... ..... ..... @rd_pg_rn_e0 +UCVTF_ds 01100101 11 010 10 1 101 ... ..... ..... @rd_pg_rn_e0 +UCVTF_dd 01100101 11 010 11 1 101 ... ..... ..... @rd_pg_rn_e0 + ### SVE Memory - 32-bit Gather and Unsized Contiguous Group # SVE load predicate register diff --git a/qemu/target/arm/sve_helper.c b/qemu/target/arm/sve_helper.c index 6c4acfc1..16e452bb 100644 --- a/qemu/target/arm/sve_helper.c +++ b/qemu/target/arm/sve_helper.c @@ -3330,3 +3330,41 @@ void HELPER(sve_st4dd_r)(CPUARMState *env, void *vg, addr += 4 * 8; } } + +/* Fully general two-operand expander, controlled by a predicate, + * With the extra float_status parameter. + */ +#define DO_ZPZ_FP(NAME, TYPE, H, OP) \ +void HELPER(NAME)(void *vd, void *vn, void *vg, void *status, uint32_t desc) \ +{ \ + intptr_t i = simd_oprsz(desc); \ + uint64_t *g = vg; \ + do { \ + uint64_t pg = g[(i - 1) >> 6]; \ + do { \ + i -= sizeof(TYPE); \ + if (likely((pg >> (i & 63)) & 1)) { \ + TYPE nn = *(TYPE *)(vn + H(i)); \ + *(TYPE *)(vd + H(i)) = OP(nn, status); \ + } \ + } while (i & 63); \ + } while (i != 0); \ +} + +DO_ZPZ_FP(sve_scvt_hh, uint16_t, H1_2, int16_to_float16) +DO_ZPZ_FP(sve_scvt_sh, uint32_t, H1_4, int32_to_float16) +DO_ZPZ_FP(sve_scvt_ss, uint32_t, H1_4, int32_to_float32) +DO_ZPZ_FP(sve_scvt_sd, uint64_t, , int32_to_float64) +DO_ZPZ_FP(sve_scvt_dh, uint64_t, , int64_to_float16) +DO_ZPZ_FP(sve_scvt_ds, uint64_t, , int64_to_float32) +DO_ZPZ_FP(sve_scvt_dd, uint64_t, , int64_to_float64) + +DO_ZPZ_FP(sve_ucvt_hh, uint16_t, H1_2, uint16_to_float16) +DO_ZPZ_FP(sve_ucvt_sh, uint32_t, H1_4, uint32_to_float16) +DO_ZPZ_FP(sve_ucvt_ss, uint32_t, H1_4, uint32_to_float32) +DO_ZPZ_FP(sve_ucvt_sd, uint64_t, , uint32_to_float64) +DO_ZPZ_FP(sve_ucvt_dh, uint64_t, , uint64_to_float16) +DO_ZPZ_FP(sve_ucvt_ds, uint64_t, , uint64_to_float32) +DO_ZPZ_FP(sve_ucvt_dd, uint64_t, , uint64_to_float64) + +#undef DO_ZPZ_FP diff --git a/qemu/target/arm/translate-sve.c b/qemu/target/arm/translate-sve.c index 21372f2e..6dae90f7 100644 --- a/qemu/target/arm/translate-sve.c +++ b/qemu/target/arm/translate-sve.c @@ -3567,6 +3567,96 @@ DO_FP3(FRSQRTS, rsqrts) #undef DO_FP3 +/* + *** SVE Floating Point Unary Operations Predicated Group + */ + +static bool do_zpz_ptr(DisasContext *s, int rd, int rn, int pg, + bool is_fp16, gen_helper_gvec_3_ptr *fn) +{ + if (sve_access_check(s)) { + TCGContext *tcg_ctx = s->uc->tcg_ctx; + unsigned vsz = vec_full_reg_size(s); + TCGv_ptr status = get_fpstatus_ptr(tcg_ctx, is_fp16); + tcg_gen_gvec_3_ptr(tcg_ctx, vec_full_reg_offset(s, rd), + vec_full_reg_offset(s, rn), + pred_full_reg_offset(s, pg), + status, vsz, vsz, 0, fn); + tcg_temp_free_ptr(tcg_ctx, status); + } + return true; +} + +static bool trans_SCVTF_hh(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +{ + return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_scvt_hh); +} + +static bool trans_SCVTF_sh(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +{ + return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_scvt_sh); +} + +static bool trans_SCVTF_dh(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +{ + return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_scvt_dh); +} + +static bool trans_SCVTF_ss(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +{ + return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_scvt_ss); +} + +static bool trans_SCVTF_ds(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +{ + return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_scvt_ds); +} + +static bool trans_SCVTF_sd(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +{ + return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_scvt_sd); +} + +static bool trans_SCVTF_dd(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +{ + return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_scvt_dd); +} + +static bool trans_UCVTF_hh(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +{ + return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_ucvt_hh); +} + +static bool trans_UCVTF_sh(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +{ + return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_ucvt_sh); +} + +static bool trans_UCVTF_dh(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +{ + return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_ucvt_dh); +} + +static bool trans_UCVTF_ss(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +{ + return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_ucvt_ss); +} + +static bool trans_UCVTF_ds(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +{ + return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_ucvt_ds); +} + +static bool trans_UCVTF_sd(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +{ + return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_ucvt_sd); +} + +static bool trans_UCVTF_dd(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +{ + return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_ucvt_dd); +} + /* *** SVE Memory - 32-bit Gather and Unsized Contiguous Group */